Xiyuan Tang - RankMe

120 papers A* 5A 10C 4Journal 47Unranked 54

Year	Rank	Type	Title / Venue / Authors
2026	—	`conf`	11.1 A 14b 400MS/s TDC-Assisted Pipelined-SAR ADC with Rail-to-Rail Input VTC and Background Time-Domain Error Calibration. ISSCC Jingpeng Wang, Bingrui Li, Haoyang Luo, Mingtao Zhan, Xiyu He, Dawei Shen, Lu Jie, Xiyuan Tang
2026	—	`conf`	32.3 An 85.1dB-SNDR 8MS/s Incremental Pipeline ADC with Dual-Residue-Assisted Exponential Quantization. ISSCC Zongnan Wang, Bingrui Li, Haoyang Luo, Chenyuan Chu, Jiachang Yang, Yuan Wang, Xiyuan Tang
2026	J	`jnl`	A 1131-kb/mm IEEE J. Solid State Circuits Jiahao Song, Xiyuan Tang, Bocheng Xu, Haikang Diao, Haoyang Luo, Zihan Wu, Yuan Wang, Runsheng Wang, Ru Huang
2026	—	`conf`	A 28nm Mode-Reconfigurable CAM-CIM Hybrid Complete 3-SAT Solver Supporting Conflict-Driven Clause Learning with 100% Solvability. ISSCC Zihan Wu, Xiyuan Tang, Lishan Lin, Youming Yang, Haoyang Luo, Bocheng Xu, Yitao Liang, Xiaochen Bo, Yuan Wang
2026	—	`conf`	A Relaxation Oscillator with 2.93μJ/cycle Energy Efficiency and 0.068% Period Jitter. ASP-DAC Yongjuan Shi, Xun Liu, Chen Hu, Xiyuan Tang, Junmin Jiang
2026	J	`jnl`	An Easy-Driving Incremental Zoom ADC With Skipped Sampling Scheme and NS-SAR Quantizer. IEEE J. Solid State Circuits Zongnan Wang, Lu Jie, Zichen Kong, Mingtao Zhan, Yi Zhong, Yuan Wang, Xiyuan Tang
2026	J	`jnl`	SKADI: A 28-nm Complete K-SAT Solver Featuring Bidirectional In-Memory Deduction and Incremental Updating. IEEE J. Solid State Circuits Zihan Wu, Xiyuan Tang, Tao Zhang, Lishan Lin, Haoyang Luo, Bocheng Xu, Zhongyi Wu, Jiahao Song, Yitao Liang, Xiaochen Bo, Yuan Wang
2026	J	`jnl`	T-800: An 800 Hz Data Glove for Precise Hand Gesture Tracking. CoRR Haoyang Luo, Zihang Zhao, Leiyao Cui, Saiyao Zhang, Liu Yang, Zhi Han, Xiyuan Tang, Yixin Zhu
2025	—	`conf`	37.5 SKADI: A 28nm Complete K-SAT Solver Featuring Dual-Path SRAM-Based Macro and Incremental Update with 100% Solvability. ISSCC Zihan Wu, Xiyuan Tang, Tao Zhang, Lishan Lin, Haoyang Luo, Bocheng Xu, Zhongyi Wu, Jiahao Song, Yitao Liang, Xiaochen Bo, Yuan Wang
2025	J	`jnl`	A 12.6-pJ/Conversion Temperature Sensor With 0.98-mV/K Temperature-Voltage Sensitivity. IEEE Trans. Circuits Syst. II Express Briefs Jiajun Tang, Xiyuan Tang
2025	—	`conf`	A 184.8dB-FoMs 1.6MS/s Incremental Noise-Shaping Pipeline ADC with Single-Amplification-Based kT/C Noise Cancellation Technique. ISSCC Zongnan Wang, Bingrui Li, Jiajun Tang, Zhongyi Wu, Haoyang Luo, Yuan Wang, Xiyuan Tang
2025	—	`conf`	A 185.2dB-FoMs 8.7aFrms Zoomed Capacitance-to-Digital Converter with Chopping-Based kT/C Noise Cancellation and Add-Then-Subtract Phase-Domain Lead-Compensation Technique. ISSCC Bingrui Li, Zilong Shen, Haoyang Luo, Jiachang Yang, Zongnan Wang, Yuan Wang, Xiyuan Tang
2025	—	`conf`	A 4.82-µW 183.4dB-FoMSNDR CT Incremental Tracking-Zoom Sensor Readout Frontend with Floating-Gm-CCO Integrator. CICC Haoyang Luo, Zongnan Wang, Jiarui Wang, Bingrui Li, Zilong Shen, Yang Liu, Xiaojie Duan, Yuan Wang, Xiyuan Tang
2025	J	`jnl`	A Computing-in-Memory Engine Supporting One-Shot Floating-Point NN Inference and On-Device Fine-Tuning for Edge AI. IEEE J. Solid State Circuits Haikang Diao, Haoyang Luo, Jiahao Song, Bocheng Xu, Runsheng Wang, Yuan Wang, Xiyuan Tang
2025	J	`jnl`	A Dual Slope Boosted Relaxation Oscillator With 2.93 μJ/Cycle Energy Efficiency and 0.068% Period Jitter in 180 nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. Yongjuan Shi, Xun Liu, Chen Hu, Xiyuan Tang, Junmin Jiang
2025	J	`jnl`	A Multiply-Less Approximate SRAM Compute-In-Memory Macro for Neural-Network Inference. IEEE J. Solid State Circuits Haikang Diao, Yifan He, Xuan Li, Chen Tang, Wenbin Jia, Jinshan Yue, Haoyang Luo, Jiahao Song, Xueqing Li, Huazhong Yang, Hongyang Jia, Yongpan Liu, Yuan Wang, Xiyuan Tang
2025	J	`jnl`	A Variation-Tolerant Continuous-Time Ising Machine With eDRAM-Based Spin Interaction and Leaked Negative Feedback Annealing. IEEE J. Solid State Circuits Zihan Wu, Jiahao Song, Xiyuan Tang, Bocheng Xu, Haoyang Luo, Youming Yang, Runsheng Wang, Xiaochen Bo, Yuan Wang
2025	A	`conf`	Adder-DCIM: A Parallel Bit-Flexible Digital CIM Accelerator Joint Model Compression Framework for AdderNet Inference. ICCAD Haikang Diao, Chuyue Tang, Bocheng Xu, Haoyang Luo, Meng Li, Yuan Wang, Xiyuan Tang
2025	J	`jnl`	LayoutCopilot: An LLM-Powered Multiagent Collaborative Framework for Interactive Analog Layout Design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Bingyang Liu, Haoyi Zhang, Xiaohan Gao, Zichen Kong, Xiyuan Tang, Yibo Lin, Runsheng Wang, Ru Huang
2025	C	`conf`	LayoutCopilot: LLM-Empowered Analog Layout Design towards Enhanced Human-Machine Interaction. ISCAS Bingyang Liu, Haoyi Zhang, Xiaohan Gao, Xiyuan Tang, Yibo Lin, Runsheng Wang, Ru Huang
2025	A	`conf`	SEGA-DCIM: Design Space Exploration-Guided Automatic Digital CIM Compiler with Multiple Precision Support. DATE Haikang Diao, Haoyi Zhang, Jiahao Song, Haoyang Luo, Yibo Lin, Runsheng Wang, Yuan Wang, Xiyuan Tang
2025	J	`jnl`	SEGA-DCIM: Design Space Exploration-Guided Automatic Digital CIM Compiler with Multiple Precision Support. CoRR Haikang Diao, Haoyi Zhang, Jiahao Song, Haoyang Luo, Yibo Lin, Runsheng Wang, Yuan Wang, Xiyuan Tang
2025	J	`jnl`	TopoSizing: An LLM-aided Framework of Topology-based Understanding and Sizing for AMS Circuits. CoRR Ziming Wei, Zichen Kong, Yuan Wang, David Z. Pan, Xiyuan Tang
2024	—	`conf`	30.5 A Variation-Tolerant In-eDRAM Continuous-Time Ising Machine Featuring 15-Level Coefficients and Leaked Negative-Feedback Annealing. ISSCC Jiahao Song, Zihan Wu, Xiyuan Tang, Bocheng Xu, Haoyang Luo, Youming Yang, Yuan Wang, Runsheng Wang, Ru Huang
2024	J	`jnl`	A 0.004-mm IEEE J. Solid State Circuits Mingtao Zhan, Lu Jie, Xiyuan Tang, Yi Zhong, Nan Sun
2024	J	`jnl`	A 16.38TOPS and 4.55POPS/W SRAM Computing-in-Memory Macro for Signed Operands Computation and Batch Normalization Implementation. IEEE Trans. Circuits Syst. I Regul. Pap. Xin Qiao, Qingyu Guo, Xiyuan Tang, Jiahao Song, Renjie Wei, Meng Li, Runsheng Wang, Yuan Wang
2024	—	`conf`	A 181.8dB FoMs Zoom Capacitance-to-Digital Converter with kT/C Noise Cancellation and Dead Band Operation. CICC Zilong Shen, Jiajun Tang, Haoyang Luo, Zhongyi Wu, Zongnan Wang, Xing Zhang, Xiyuan Tang, Yuan Wang
2024	J	`jnl`	A 266F IEEE Trans. Circuits Syst. II Express Briefs Haoyi Zhang, Jiahao Song, Haoyang Luo, Xiyuan Tang, Yuan Wang, Runsheng Wang, Ru Huang
2024	—	`conf`	A 28nm 128TFLOPS/W Computing-In-Memory Engine Supporting One-Shot Floating-Point NN Inference and On-Device Fine-Tuning for Edge AI. CICC Haikang Diao, Haoyang Luo, Jiahao Song, Bocheng Xu, Runsheng Wang, Yuan Wang, Xiyuan Tang
2024	J	`jnl`	A 4-bit Calibration-Free Computing-In-Memory Macro With 3T1C Current-Programed Dynamic-Cascode Multi-Level-Cell eDRAM. IEEE J. Solid State Circuits Jiahao Song, Xiyuan Tang, Haoyang Luo, Haoyi Zhang, Xin Qiao, Zixuan Sun, Xiangxing Yang, Zihan Wu, Yuan Wang, Runsheng Wang, Ru Huang
2024	—	`conf`	An Amplitude and Slope Based Nonlinearity Calibration Algorithm for LC-ADC. BioCAS Xiyuan Tang, Qiao Cai, Yanxing Suo, Xinzi Xu, Yunfang Zhang, Yong Lian, Yang Zhao
2024	J	`jnl`	CASCADE: A Framework for CNN Accelerator Synthesis With Concatenation and Refreshing Dataflow. IEEE Trans. Circuits Syst. I Regul. Pap. Qingyu Guo, Haoyang Luo, Meng Li, Xiyuan Tang, Yuan Wang
2024	A*	`conf`	EasyACIM: An End-to-End Automated Analog CIM with Synthesizable Architecture and Agile Design Space Exploration. DAC Haoyi Zhang, Jiahao Song, Xiaohan Gao, Xiyuan Tang, Yibo Lin, Runsheng Wang, Ru Huang
2024	J	`jnl`	EasyACIM: An End-to-End Automated Analog CIM with Synthesizable Architecture and Agile Design Space Exploration. CoRR Haoyi Zhang, Jiahao Song, Xiaohan Gao, Xiyuan Tang, Yibo Lin, Runsheng Wang, Ru Huang
2024	J	`jnl`	LayoutCopilot: An LLM-powered Multi-agent Collaborative Framework for Interactive Analog Layout Design. CoRR Bingyang Liu, Haoyi Zhang, Xiaohan Gao, Zichen Kong, Xiyuan Tang, Yibo Lin, Runsheng Wang, Ru Huang
2024	—	`conf`	MixCIM: A Hybrid-Cell-Based Computing-in-Memory Macro with Less-Data-Movement and Activation-Memory-Reuse for Depthwise Separable Neural Networks. CICC Xin Qiao, Jiahao Song, Youming Yang, Renjie Wei, Xiyuan Tang, Meng Li, Runsheng Wang, Yuan Wang
2024	A*	`conf`	PVTSizing: A TuRBO-RL-Based Batch-Sampling Optimization Framework for PVT-Robust Analog Circuit Synthesis. DAC Zichen Kong, Xiyuan Tang, Wei Shi, Yiheng Du, Yibo Lin, Yuan Wang
2024	A	`conf`	SAGERoute 2.0: Hierarchical Analog and Mixed Signal Routing Considering Versatile Routing Scenarios. DATE Haoyi Zhang, Xiaohan Gao, Zilong Shen, Jiahao Song, Xiaoxu Cheng, Xiyuan Tang, Yibo Lin, Runsheng Wang, Ru Huang
2023	—	`conf`	A 150kHz-BW 15-ENOB Incremental Zoom ADC with Skipped Sampling and Single Buffer Embedded Noise-Shaping SAR Quantizer. ISSCC Zongnan Wang, Lu Jie, Zichen Kong, Mingtao Zhan, Yi Zhong, Yuan Wang, Xiyuan Tang
2023	J	`jnl`	A 28 nm 16 Kb Bit-Scalable Charge-Domain Transpose 6T SRAM In-Memory Computing Macro. IEEE Trans. Circuits Syst. I Regul. Pap. Jiahao Song, Xiyuan Tang, Xin Qiao, Yuan Wang, Runsheng Wang, Ru Huang
2023	—	`conf`	A 28nm 38-to-102-TOPS/W 8b Multiply-Less Approximate Digital SRAM Compute-In-Memory Macro for Neural-Network Inference. ISSCC Yifan He, Haikang Diao, Chen Tang, Wenbin Jia, Xiyuan Tang, Yuan Wang, Jinshan Yue, Xueqing Li, Huazhong Yang, Hongyang Jia, Yongpan Liu
2023	—	`conf`	A 9.7fJ/Conv.-Step Capacitive Sensor Readout Circuit with Incremental Zoomed Time Domain Quantization. CICC Zilong Shen, Xiyuan Tang, Zhongyi Wu, Haoyang Luo, Zongnan Wang, Mingjie Liu, Xing Zhang, Yuan Wang
2023	J	`jnl`	A Bandwidth-Adaptive Pipelined SAR ADC With Three-Stage Cascoded Floating Inverter Amplifier. IEEE J. Solid State Circuits Xiyuan Tang, Xiangxing Yang, Jiaxin Liu, Zongnan Wang, Wei Shi, David Z. Pan, Nan Sun
2023	—	`conf`	A Calibration-Free 15-level/Cell eDRAM Computing-in-Memory Macro with 3T1C Current-Programmed Dynamic-Cascoded MLC achieving 233-to-304-TOPS/W 4b MAC. CICC Jiahao Song, Xiyuan Tang, Haoyang Luo, Haoyi Zhang, Xin Qiao, Zixuan Sun, Xiangxing Yang, Yuan Wang, Runsheng Wang, Ru Huang
2023	J	`jnl`	A Power-Efficient 13-Tap FIR Filter and an IIR Filter Embedded in a 10-Bit SAR ADC. IEEE Trans. Circuits Syst. I Regul. Pap. Xin Xin, Linxiao Shen, Xiyuan Tang, Yi Shen, Jueping Cai, Xingyuan Tong, Nan Sun
2023	—	`conf`	An 80.2-to-89.1dB-SNDR 24k-to-200kHz-BW VCO-Based Synthesized ?S ADC with 105dB SFDR in 28-nm CMOS. CICC Yi Zhong, Mingtao Zhan, Wei Wang, Xiyuan Tang, Lu Jie, Nan Sun
2023	J	`jnl`	An In-Memory-Computing Charge-Domain Ternary CNN Classifier. IEEE J. Solid State Circuits Xiangxing Yang, Keren Zhu, Xiyuan Tang, Meizhi Wang, Mingtao Zhan, Nanshu Lu, Jaydeep P. Kulkarni, David Z. Pan, Yongpan Liu, Nan Sun
2023	C	`conf`	An NS-SAR ADC with Full-bit High-order Mismatch Shaped CDAC. ISCAS Xiao Han, Xiyuan Tang, Zibo Ma, Xinzi Xu, Yanxing Suo, Qiao Cai, Yang Zhao
2023	A	`conf`	SAGERoute: Synergistic Analog Routing Considering Geometric and Electrical Constraints with Manual Design Compatibility. DATE Haoyi Zhang, Xiaohan Gao, Haoyang Luo, Jiahao Song, Xiyuan Tang, Junhua Liu, Yibo Lin, Runsheng Wang, Ru Huang
2022	—	`conf`	A 0.004mm ISSCC Mingtao Zhan, Lu Jie, Xiyuan Tang, Nan Sun
2022	—	`conf`	A 0.014mm ISSCC Lu Jie, Mingtao Zhan, Xiyuan Tang, Nan Sun
2022	—	`conf`	A 0.37mm CICC Wei Shi, Xing Wang, Xiyuan Tang, Abhishek Mukherjee, Raviteja Theertham, Shanthi Pavan, Lu Jie, Nan Sun
2022	J	`jnl`	A 10-bit 100-MS/s SAR ADC With Always-On Reference Ripple Cancellation. IEEE Trans. Circuits Syst. I Regul. Pap. Yi Shen, Xiyuan Tang, Xin Xin, Shubin Liu, Zhangming Zhu, Nan Sun
2022	J	`jnl`	A 65 nm 73 kb SRAM-Based Computing-In-Memory Macro With Dynamic-Sparsity Controlling. IEEE Trans. Circuits Syst. II Express Briefs Xin Qiao, Jiahao Song, Xiyuan Tang, Haoyang Luo, Nanbing Pan, Xiaoxin Cui, Runsheng Wang, Yuan Wang
2022	—	`conf`	A Vector Pair Based DWA Algorithm for Linearity Enhancement of CDACs in the NS-SAR ADC. APCCAS Xiao Han, Xiyuan Tang, Yanxing Suo, Qiao Cai, Xinzi Xu, Tianwei Wan, Yang Zhao
2022	—	`conf`	Generative-Adversarial-Network-Guided Well-Aware Placement for Analog Circuits. ASP-DAC Keren Zhu, Hao Chen, Mingjie Liu, Xiyuan Tang, Wei Shi, Nan Sun, David Z. Pan
2022	J	`jnl`	Low-Power SAR ADC Design: Overview and Survey of State-of-the-Art Techniques. IEEE Trans. Circuits Syst. I Regul. Pap. Xiyuan Tang, Jiaxin Liu, Yi Shen, Shaolan Li, Linxiao Shen, Arindam Sanyal, Kareem Ragab, Nan Sun
2021	—	`conf`	10.4 A 3.7mW 12.5MHz 81dB-SNDR 4th-Order CTDSM with Single-OTA and 2nd-Order NS-SAR. ISSCC Wei Shi, Jiaxin Liu, Abhishek Mukherjee, Xiangxing Yang, Xiyuan Tang, Linxiao Shen, Wenda Zhao, Nan Sun
2021	—	`conf`	27.1 A 250kHz-BW 93dB-SNDR 4 ISSCC Jiaxin Liu, Dengquan Li, Yi Zhong, Xiyuan Tang, Nan Sun
2021	—	`conf`	A 0.4-to-40MS/s 75.7dB-SNDR Fully Dynamic Event-Driven Pipelined ADC with 3-Stage Cascoded Floating Inverter Amplifier. ISSCC Xiyuan Tang, Xiangxing Yang, Jiaxin Liu, Wei Shi, David Z. Pan, Nan Sun
2021	J	`jnl`	A 13.8-ENOB Fully Dynamic Third-Order Noise-Shaping SAR ADC in a Single-Amplifier EF-CIFF Structure With Hardware-Reusing kT/C Noise Cancellation. IEEE J. Solid State Circuits Tzu-Han Wang, Ruowei Wu, Vasu Gupta, Xiyuan Tang, Shaolan Li
2021	—	`conf`	A 16Kb Transpose 6T SRAM In-Memory-Computing Macro based on Robust Charge-Domain Computing. A-SSCC Jiahao Song, Yuan Wang, Xiyuan Tang, Runsheng Wang, Ru Huang
2021	J	`jnl`	A 74.5-dB Dynamic Range 10-MHz BW CT-ΔΣ ADC With Distributed-Input VCO and Embedded Capacitive-π Network in 40-nm CMOS. IEEE J. Solid State Circuits Abhishek Mukherjee, Miguel Gandara, Xiangxing Yang, Linxiao Shen, Xiyuan Tang, Chen-Kai Hsu, Nan Sun
2021	J	`jnl`	A 77.1-dB-SNDR 6.25-MHz-BW Pipeline SAR ADC With Enhanced Interstage Gain Error Shaping and Quantization Noise Shaping. IEEE J. Solid State Circuits Chen-Kai Hsu, Xiyuan Tang, Jiaxin Liu, Rui Xu, Wenda Zhao, Abhishek Mukherjee, Timothy R. Andeen, Nan Sun
2021	J	`jnl`	A 90-dB-SNDR Calibration-Free Fully Passive Noise-Shaping SAR ADC With 4× Passive Gain and Second-Order DAC Mismatch Error Shaping. IEEE J. Solid State Circuits Jiaxin Liu, Xing Wang, Zijie Gao, Mingtao Zhan, Xiyuan Tang, Chen-Kai Hsu, Nan Sun
2021	—	`conf`	An 81.5dB-DR 1.25MHz-BW VCO-Based CT ΔΣ ADC with Double-PFD Quantizer. CICC Yi Zhong, Xiyuan Tang, Jiaxin Liu, Wenda Zhao, Shaolan Li, Nan Sun
2021	—	`conf`	An In-Memory-Computing Charge-Domain Ternary CNN Classifier. CICC Xiangxing Yang, Keren Zhu, Xiyuan Tang, Meizhi Wang, Mingtao Zhan, Nanshu Lu, Jaydeep P. Kulkarni, David Z. Pan, Yongpan Liu, Nan Sun
2021	—	`conf`	MAGICAL 1.0: An Open-Source Fully-Automated AMS Layout Synthesis Framework Verified With a 40-nm 1GS/s Δ∑ ADC. CICC Hao Chen, Mingjie Liu, Xiyuan Tang, Keren Zhu, Abhishek Mukherjee, Nan Sun, David Z. Pan
2021	J	`jnl`	MAGICAL: An Open- Source Fully Automated Analog IC Layout System from Netlist to GDSII. IEEE Des. Test Hao Chen, Mingjie Liu, Biying Xu, Keren Zhu, Xiyuan Tang, Shaolan Li, Yibo Lin, Nan Sun, David Z. Pan
2021	A	`conf`	OpenSAR: An Open Source Automated End-to-end SAR ADC Compiler. ICCAD Mingjie Liu, Xiyuan Tang, Keren Zhu, Hao Chen, Nan Sun, David Z. Pan
2021	J	`jnl`	TD-SRAM: Time-Domain-Based In-Memory Computing Macro for Binary Neural Networks. IEEE Trans. Circuits Syst. I Regul. Pap. Jiahao Song, Yuan Wang, Minguang Guo, Xiang Ji, Kaili Cheng, Yixuan Hu, Xiyuan Tang, Runsheng Wang, Ru Huang
2021	A*	`conf`	Universal Symmetry Constraint Extraction for Analog and Mixed-Signal Circuits with Graph Neural Networks. DAC Hao Chen, Keren Zhu, Mingjie Liu, Xiyuan Tang, Nan Sun, David Z. Pan
2020	—	`conf`	16.5 A 13b 0.005mm ISSCC Jiaxin Liu, Xiyuan Tang, Wenda Zhao, Linxiao Shen, Nan Sun
2020	—	`conf`	9.3 A 40kHz-BW 90dB-SNDR Noise-Shaping SAR with 4× Passive Gain and 2 ISSCC Jiaxin Liu, Xing Wang, Zijie Gao, Mingtao Zhan, Xiyuan Tang, Nan Sun
2020	—	`conf`	9.5 A 13.5b-ENOB Second-Order Noise-Shaping SAR with PVT-Robust Closed-Loop Dynamic Amplifier. ISSCC Xiyuan Tang, Xiangxing Yang, Wenda Zhao, Chen-Kai Hsu, Jiaxin Liu, Linxiao Shen, Abhishek Mukherjee, Wei Shi, David Z. Pan, Nan Sun
2020	J	`jnl`	A 0.025-mm IEEE J. Solid State Circuits Wenda Zhao, Shaolan Li, Biying Xu, Xiangxing Yang, Xiyuan Tang, Linxiao Shen, Nanshu Lu, David Z. Pan, Nan Sun
2020	—	`conf`	A 10-Bit 100-MS/s SAR ADC with Always-on Reference Ripple Cancellation. VLSI Circuits Xiyuan Tang, Yi Shen, Xin Xin, Shubin Liu, Jueping Cai, Zhangming Zhu, Nan Sun
2020	J	`jnl`	A 10-bit 120-MS/s SAR ADC With Reference Ripple Cancellation Technique. IEEE J. Solid State Circuits Yi Shen, Xiyuan Tang, Linxiao Shen, Wenda Zhao, Xin Xin, Shubin Liu, Zhangming Zhu, Visvesh Sathe, Nan Sun
2020	J	`jnl`	A 13-bit 0.005-mm IEEE J. Solid State Circuits Jiaxin Liu, Xiyuan Tang, Wenda Zhao, Linxiao Shen, Nan Sun
2020	J	`jnl`	A 13.5-ENOB, 107-μW Noise-Shaping SAR ADC With PVT-Robust Closed-Loop Dynamic Amplifier. IEEE J. Solid State Circuits Xiyuan Tang, Xiangxing Yang, Wenda Zhao, Chen-Kai Hsu, Jiaxin Liu, Linxiao Shen, Abhishek Mukherjee, Wei Shi, Shaolan Li, David Z. Pan, Nan Sun
2020	—	`conf`	A 77.1-dB 6.25-MHz-BW Pipeline SAR ADC with Enhanced Interstage Gain Error Shaping and Quantization Error Shaping. CICC Chen-Kai Hsu, Xiyuan Tang, Wenda Zhao, Rui Xu, Abhishek Mukherjee, Timothy R. Andeen, Nan Sun
2020	J	`jnl`	A Fractional- IEEE J. Solid State Circuits Yanlong Zhang, Arindam Sanyal, Xueyi Yu, Xing Quan, Kailin Wen, Xiyuan Tang, Gang Jin, Li Geng, Nan Sun
2020	—	`conf`	A Power-Efficient 13-Tap FIR filter and an IIR Filter Embedded in a 10-bit SAR ADC. A-SSCC Xin Xin, Linxiao Shen, Xiyuan Tang, Yi Shen, Jueping Cai, Nan Sun
2020	—	`conf`	A SAR ADC with Reduced kT/C Noise by Decoupling Noise PSD and BW. VLSI Circuits Zhelu Li, Arnab Dutta, Abhishek Mukherjee, Xiyuan Tang, Linxiao Shen, Lenian He, Nan Sun
2020	J	`jnl`	A Second-Order Purely VCO-Based CT ΔΣ ADC Using a Modified DPLL Structure in 40-nm CMOS. IEEE J. Solid State Circuits Yi Zhong, Shaolan Li, Xiyuan Tang, Linxiao Shen, Wenda Zhao, Siliang Wu, Nan Sun
2020	J	`jnl`	An Energy-Efficient Comparator With Dynamic Floating Inverter Amplifier. IEEE J. Solid State Circuits Xiyuan Tang, Linxiao Shen, Begum Kasap, Xiangxing Yang, Wei Shi, Abhishek Mukherjee, David Z. Pan, Nan Sun
2020	C	`conf`	An Energy-Efficient Flexible Capacitive Pressure Sensing System. ISCAS Yuxuan Huang, Qinghang Zhao, Xiyuan Tang, Fang Su, Nan Sun, Huazhong Yang, Yongpan Liu
2020	J	`jnl`	An Energy-Efficient Time-Domain Incremental Zoom Capacitance-to-Digital Converter. IEEE J. Solid State Circuits Xiyuan Tang, Shaolan Li, Xiangxing Yang, Linxiao Shen, Wenda Zhao, Randall P. Williams, Jiaxin Liu, Zhichao Tan, Neal A. Hall, David Z. Pan, Nan Sun
2020	A*	`conf`	Closing the Design Loop: Bayesian Optimization Assisted Hierarchical Analog Layout Synthesis. DAC Mingjie Liu, Keren Zhu, Xiyuan Tang, Biying Xu, Wei Shi, Nan Sun, David Z. Pan
2020	A	`conf`	Effective Analog/Mixed-Signal Circuit Placement Considering System Signal Flow. ICCAD Keren Zhu, Hao Chen, Mingjie Liu, Xiyuan Tang, Nan Sun, David Z. Pan
2020	—	`conf`	S ASP-DAC Mingjie Liu, Wuxi Li, Keren Zhu, Biying Xu, Yibo Lin, Linxiao Shen, Xiyuan Tang, Nan Sun, David Z. Pan
2020	A	`conf`	Toward Silicon-Proven Detailed Routing for Analog and Mixed-Signal Circuits. ICCAD Hao Chen, Keren Zhu, Mingjie Liu, Xiyuan Tang, Nan Sun, David Z. Pan
2020	A	`conf`	Towards Decrypting the Art of Analog Layout: Placement Quality Prediction via Transfer Learning. DATE Mingjie Liu, Keren Zhu, Jiaqi Gu, Linxiao Shen, Xiyuan Tang, Nan Sun, David Z. Pan
2019	—	`conf`	A 0.01mm ISSCC Linxiao Shen, Yi Shen, Xiyuan Tang, Chen-Kai Hsu, Wei Shi, Shaolan Li, Wenda Zhao, Abhishek Mukherjee, Nan Sun
2019	—	`conf`	A 0.025-mm CICC Shaolan Li, Wenda Zhao, Biying Xu, Xiangxing Yang, Xiyuan Tang, Linxiao Shen, Nanshu Lu, David Z. Pan, Nan Sun
2019	—	`conf`	A 0.6-V Tail-Less Inverter Stacking Amplifier with 0.96 PEF. VLSI Circuits Linxiao Shen, Abhishek Mukherjee, Shaolan Li, Xiyuan Tang, Nanshu Lu, Nan Sun
2019	J	`jnl`	A 10-b 600-MS/s 2-Way Time-Interleaved SAR ADC With Mean Absolute Deviation-Based Background Timing-Skew Calibration. IEEE Trans. Circuits Syst. I Regul. Pap. Jeonggoo Song, Kareem Ragab, Xiyuan Tang, Nan Sun
2019	—	`conf`	A 10b 120MS/s SAR ADC with Reference Ripple Cancellation Technique. CICC Xiyuan Tang, Yi Shen, Linxiao Shen, Wenda Zhao, Zhangming Zhu, Visvesh Sathe, Nan Sun
2019	—	`conf`	A 16fJ/Conversion-Step Time-Domain Two-Step Capacitance-to-Digital Converter. ISSCC Xiyuan Tang, Shaolan Li, Linxiao Shen, Wenda Zhao, Xiangxing Yang, Randy Williams, Jiaxin Liu, Zhichao Tan, Neal A. Hall, Nan Sun
2019	—	`conf`	A 2.4-GHz ΔΣ Fractional-N Synthesizer with Space-Time Averaging for Noise Reduction. CICC Yanlong Zhang, Arindam Sanyal, Xing Quan, Kailin Wen, Xiyuan Tang, Gang Jin, Li Geng, Nan Sun
2019	J	`jnl`	A Two-Step ADC With a Continuous-Time SAR-Based First Stage. IEEE J. Solid State Circuits Linxiao Shen, Nan Sun, Yi Shen, Zhelu Li, Wei Shi, Xiyuan Tang, Shaolan Li, Wenda Zhao, Mantian Zhang, Zhangming Zhu
2019	J	`jnl`	Advances in Voltage-Controlled-Oscillator-Based ΔΣ ADCs. IEICE Trans. Electron. Shaolan Li, Arindam Sanyal, Kyoungtae Lee, Yeonam Yoon, Xiyuan Tang, Yi Zhong, Kareem Ragab, Nan Sun
2019	—	`conf`	An Energy-Efficient Comparator with Dynamic Floating Inverter Pre-Amplifier. VLSI Circuits Xiyuan Tang, Begum Kasap, Linxiao Shen, Xiangxing Yang, Wei Shi, Nan Sun
2019	J	`jnl`	Error-Feedback Mismatch Error Shaping for High-Resolution Data Converters. IEEE Trans. Circuits Syst. I Regul. Pap. Jiaxin Liu, Chen-Kai Hsu, Xiyuan Tang, Shaolan Li, Guangjun Wen, Nan Sun
2019	A	`conf`	GeniusRoute: A New Analog Routing Paradigm Using Generative Neural Network Guidance. ICCAD Keren Zhu, Mingjie Liu, Yibo Lin, Biying Xu, Shaolan Li, Xiyuan Tang, Nan Sun, David Z. Pan
2019	A	`conf`	MAGICAL: Toward Fully Automated Analog IC Layout Leveraging Human and Machine Intelligence: Invited Paper. ICCAD Biying Xu, Keren Zhu, Mingjie Liu, Yibo Lin, Shaolan Li, Xiyuan Tang, Nan Sun, David Z. Pan
2019	—	`conf`	S ASP-DAC Mohamed Baker Alawieh, Xiyuan Tang, David Z. Pan
2019	A*	`conf`	WellGAN: Generative-Adversarial-Network-Guided Well Generation for Analog/Mixed-Signal Circuit Layout. DAC Biying Xu, Yibo Lin, Xiyuan Tang, Shaolan Li, Linxiao Shen, Nan Sun, David Z. Pan
2018	—	`conf`	A Second-Order Purely VCO-Based CT Δ∑ ADC Using a Modified DPLL in 40-nm CMOS. A-SSCC Yi Zhong, Shaolan Li, Arindam Sanyal, Xiyuan Tang, Linxiao Shen, Siliang Wu, Nan Sun
2017	J	`jnl`	A 0.7-V 0.6-µW 100-kS/s Low-Power SAR ADC With Statistical Estimation-Based Noise Reduction. IEEE J. Solid State Circuits Long Chen, Xiyuan Tang, Arindam Sanyal, Yeonam Yoon, Jie Cong, Nan Sun
2017	J	`jnl`	A 0.95-mW 6-b 700-MS/s Single-Channel Loop-Unrolled SAR ADC in 40-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs Long Chen, Kareem Ragab, Xiyuan Tang, Jeonggoo Song, Arindam Sanyal, Nan Sun
2017	—	`conf`	A 1.5fJ/conv-step 10b 100kS/s SAR ADC with gain-boosted dynamic comparator. A-SSCC Xiyuan Tang, Long Chen, Jeonggoo Song, Nan Sun
2017	—	`conf`	A 10-b 2b/cycle 300MS/s SAR ADC with a single differential DAC in 40nm CMOS. CICC Jeonggoo Song, Xiyuan Tang, Nan Sun
2017	J	`jnl`	A 10-b 800-MS/s Time-Interleaved SAR ADC With Fast Variance-Based Timing-Skew Calibration. IEEE J. Solid State Circuits Jeonggoo Song, Kareem Ragab, Xiyuan Tang, Nan Sun
2017	—	`conf`	A pipelined SAR ADC reusing the comparator as residue amplifier. CICC Miguel Gandara, Wenjuan Guo, Xiyuan Tang, Long Chen, Yeonam Yoon, Nan Sun
2016	—	`conf`	A 10-b 750µW 200MS/s fully dynamic single-channel SAR ADC in 40nm CMOS. ESSCIRC Xiyuan Tang, Long Chen, Jeonggoo Song, Nan Sun
2016	—	`conf`	A 10-b 800MS/s time-interleaved SAR ADC with fast timing-skew calibration. A-SSCC Jeonggoo Song, Kareem Ragab, Xiyuan Tang, Nan Sun
2016	C	`conf`	Comparator common-mode variation effects analysis and its application in SAR ADCs. ISCAS Long Chen, Arindam Sanyal, Ji Ma, Xiyuan Tang, Nan Sun
2015	—	`conf`	A 0.04-mm CICC Yeonam Yoon, Kyoungtae Lee, Sungjin Hong, Xiyuan Tang, Long Chen, Nan Sun
2015	—	`conf`	A 10.5-b ENOB 645 nW 100kS/s SAR ADC with statistical estimation based noise reduction. CICC Long Chen, Xiyuan Tang, Arindam Sanyal, Yeonam Yoon, Jie Cong, Nan Sun