Xiuyuan Bi

17 papers A* 1A 7C 1Journal 4Unranked 4
YearRankTypeTitle / Venue / Authors
2021 J jnl
Exploring Applications of STT-RAM in GPU Architectures.
IEEE Trans. Circuits Syst. I Regul. Pap.
Xiaoxiao Liu, Mengjie Mao, Xiuyuan Bi, Hai Helen Li, Yiran Chen
2017 J jnl
Cross-Layer Optimization for Multilevel Cell STT-RAM Caches.
IEEE Trans. Very Large Scale Integr. Syst.
Xiuyuan Bi, Mengjie Mao, Danghui Wang, Hai Helen Li
2016 J jnl
Array Organization and Data Management Exploration in Racetrack Memory.
IEEE Trans. Computers
Zhenyu Sun, Xiuyuan Bi, Wenqing Wu, Sungjoo Yoo, Hai (Helen) Li
2016 A conf
Design and Implementation of a 4Kb STT-MRAM with Innovative 200nm Nano-ring Shaped MTJ.
ISLPED
Zheng Li, Xiuyuan Bi, Hai (Helen) Li, Yiran Chen, Jianying Qin, Peng Guo, Wenjie Kong, Wenshan Zhan, Xiufeng Han, Hong Zhang, Lingling Wang, Guanping Wu, Hanming Wu
2015 — conf
An efficient STT-RAM-based register file in GPU architectures.
ASP-DAC
Xiaoxiao Liu, Mengjie Mao, Xiuyuan Bi, Hai Li, Yiran Chen
2015 — conf
The evolutionary spintronic technologies and their usage in high performance computing.
SoCC
Hai (Helen) Li, Xiuyuan Bi, Zhenyu Sun
2014 A conf
Design exploration of racetrack lower-level caches.
ISLPED
Zhenyu Sun, Xiuyuan Bi, Alex K. Jones, Hai Li
2014 C conf
Optimizing MLC-based STT-RAM caches by dynamic block size reconfiguration.
ICCD
Jianxing Wang, Pooja Roy, Weng-Fai Wong, Xiuyuan Bi, Hai Li
2014 J jnl
STT-RAM Cache Hierarchy With Multiretention MTJ Designs.
IEEE Trans. Very Large Scale Integr. Syst.
Zhenyu Sun, Xiuyuan Bi, Hai Li, Weng-Fai Wong, Xiaochun Zhu
2013 — conf
A pseudo-weighted sensing scheme for memristor based cross-point memory.
NANOARCH
Zhijie Chen, Lu Zhang, Xiuyuan Bi, Hai Li
2013 A conf
STT-RAM designs supporting dual-port accesses.
DATE
Xiuyuan Bi, Mohamed Anis Weldon, Hai Li
2013 A conf
Unleashing the potential of MLC STT-RAM caches.
ICCAD
Xiuyuan Bi, Mengjie Mao, Danghui Wang, Hai Li
2012 — conf
Analysis and Optimization of Thermal Effect on STT-RAM Based 3-D Stacked Cache Design.
ISVLSI
Xiuyuan Bi, Hai Li, Jae-Joon Kim
2012 A conf
Probabilistic design methodology to improve run-time stability and performance of STT-RAM caches.
ICCAD
Xiuyuan Bi, Zhenyu Sun, Hai Li, Wenqing Wu
2012 A conf
Process variation aware data management for STT-RAM cache design.
ISLPED
Zhenyu Sun, Xiuyuan Bi, Hai Li
2012 A conf
Spintronic memristor based temperature sensor design with CMOS current reference.
DATE
Xiuyuan Bi, Chao Zhang, Hai Li, Yiran Chen, Robinson E. Pino
2011 A* conf
Multi retention level STT-RAM cache designs with a dynamic refresh scheme.
MICRO
Zhenyu Sun, Xiuyuan Bi, Hai (Helen) Li, Weng-Fai Wong, Zhong-Liang Ong, Xiaochun Zhu, Wenqing Wu