Xiumin Xu

16 papers Journal 12Unranked 4
YearRankTypeTitle / Venue / Authors
2026 J jnl
A Phase-Walk-Based True Random Number Generator Exploiting Dual-Ring Phase Jitter Comparison.
IEEE Trans. Circuits Syst. II Express Briefs
Liang Yao, Peiyang Kang, Jiahao Zhang, Yaohua Xu, Ying Zhang, Xiumin Xu, Huaguo Liang, Zhengfeng Huang, Yingchun Lu
2026 J jnl
Design of a dynamic obfuscation-based strong PUF resistant to modeling attacks and mutual authentication protocol.
Integr.
Yingchun Lu, Hongliang Lu, Yujie Liu, Huaguo Liang, Zhengfeng Huang, Jinlin Chen, Xiumin Xu, Liang Yao
2026 J jnl
FTPUF:Feedback structure of TERO PUF for high reliability.
Integr.
Yingchun Lu, Xinkai Wu, Jinlin Chen, Huaguo Liang, Zhengfeng Huang, Xiumin Xu, Bo Liu
2026 J jnl
X-RAM: a novel and efficient multi-ported memory for AI accelerator.
Integr.
Xiumin Xu, Liang Yao
2025 — conf
Design of a Dynamic Obfuscation-Based Strong PUF Resistant to Modeling Attacks.
SBCCI
Yingchun Lu, Hongliang Lu, Yujie Liu, Huaguo Liang, Cuiyun Jiang, Zhengfeng Huang, Xiumin Xu, Liang Yao
2025 J jnl
High-Throughput TRNG Design with Novelty Adjustable TDC Based on STR.
ACM Trans. Reconfigurable Technol. Syst.
Yongkang Feng, Liang Yao, Hongli Zhou, Minjie Wu, Shuai Xiang, Wanting Sun, Xiumin Xu, Yingchun Lu
2025 J jnl
TUTPFL: Triple Node Upset-Tolerant and Single-Event Transient-Filtered Low-Power Latch With HSPICE and FPGA-Based Verifications.
IEEE Trans. Very Large Scale Integr. Syst.
Aibin Yan, Jiajia Zhang, Xiumin Xu, Hanxiang Li, Na Bai, Zhengfeng Huang, Xiaolei Wang, Xiaoqing Wen, Patrick Girard
2018 — conf
A High Reliability FPGA Chip Identification Generator Based on PDLs.
ATS
Kai Zhou, Huaguo Liang, Yue Jiang, Zhengfeng Huang, Maoxiang Yi, Xiumin Xu, Yao Yao
2018 — conf
A Low-Cost High-Efficiency True Random Number Generator on FPGAs.
ATS
Gaoliang Ma, Huaguo Liang, Liang Yao, Zhengfeng Huang, Maoxiang Yi, Xiumin Xu, Kai Zhou
2018 — conf
An All-Digital and Jitter-Quantizing True Random Number Generator in SRAM-Based FPGAs.
ATS
Xiumin Xu, Huaguo Liang, Kai Zhou, Gaoliang Ma, Zhengfeng Huang, Maoxiang Yi, Tianming Ni, Yingchun Lu
2017 J jnl
A Region-Based Through-Silicon via Repair Method for Clustered Faults.
IEICE Trans. Electron.
Tianming Ni, Huaguo Liang, Mu Nie, Xiumin Xu, Aibin Yan, Zhengfeng Huang
2017 J jnl
A highly reliable butterfly PUF in SRAM-based FPGAs.
IEICE Electron. Express
Xiumin Xu, Huaguo Liang, Zhengfeng Huang, Cuiyun Jiang, Yiming Ouyang, Xiangsheng Fang, Tianming Ni, Maoxiang Yi
2017 J jnl
A single event transient detector in SRAM-based FPGAs.
IEICE Electron. Express
Xiumin Xu, Huaguo Liang, Zhengfeng Huang, Cuiyun Jiang, Yingchun Lu, Aibin Yan, Tianming Ni, Maoxiang Yi
2017 J jnl
Double-Node-Upset-Resilient Latch Design for Nanoscale CMOS Technology.
IEEE Trans. Very Large Scale Integr. Syst.
Aibin Yan, Zhengfeng Huang, Maoxiang Yi, Xiumin Xu, Yiming Ouyang, Huaguo Liang
2017 J jnl
Highly Robust Double Node Upset Resilient Hardened Latch Design.
IEICE Trans. Electron.
Huaguo Liang, Xin Li, Zhengfeng Huang, Aibin Yan, Xiumin Xu
2017 J jnl
Vernier ring based pre-bond through silicon vias test in 3D ICs.
IEICE Electron. Express
Tianming Ni, Mu Nie, Huaguo Liang, Jingchang Bian, Xiumin Xu, Xiangsheng Fang, Zhengfeng Huang, Xiaoqing Wen