Xinyu Liu - RankMe

42 papers C 1Journal 35Unranked 6

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	A low-voltage input buffer with linearity-enhancement scheme for a 500MS/s Pipelined-SAR ADC achieving SFDR > 79dBc. Microelectron. J. Fangyuan Xu, Yina Shangguan, Xuan Guo, Hanbo Jia, Yun Bai, Kai Sun, Xinyu Liu
2026	J	`jnl`	A novel fast and wide range background timing mismatch calibration algorithm for TIADCs. Microelectron. J. Jiahui Luo, Hanbo Jia, Xuan Guo, Linzhen Wu, Yuzhen Zhang, Xiuheng Wu, Kai Sun, Xinyu Liu
2025	J	`jnl`	A 1.5 GS/s 13-bit partial-interleaving pipelined-SAR ADC with 1/gm load and current-biased ring amplifier. Microelectron. J. Jingyuan Xu, Kai Sun, Xuan Guo, Wenhao Ren, Fangyuan Xu, Hanbo Jia, Xinyu Liu
2025	J	`jnl`	A 100 Gb/s PAM4 receiver analog front-end with 33.1-dB boost in 28-nm CMOS process. IEICE Electron. Express Qiuyue Zhang, Xuqiang Zheng, Fangxu Lv, Wenxiang Zhen, Mingche Lai, Zhi Jin, Xinyu Liu
2025	J	`jnl`	A 100-MHz bandwidth continuous-time sigma-delta ADC with 1 V supply in 28 nm CMOS. Microelectron. J. Ben He, Xuan Guo, Hanbo Jia, Xinyu Liu
2025	J	`jnl`	A 112-Gb/s PAM-4 Retimer Transceiver With Jitter-Filtering Clocking Scheme and BER Optimization Technique in 28-nm CMOS. IEEE J. Solid State Circuits Hua Xu, Mingche Lai, Xuqiang Zheng, Zedong Wang, Jiang Xu, Sai Li, Fangxu Lv, Min Liu, Weijie Li, Zhanhao Wen, Xuan Guo, Xinhua Wang, Zhi Jin, Xinyu Liu
2025	J	`jnl`	A 14-GS/s 8-bit time-interleaved SAR ADC with multi-path bootstrapped switch and low-jitter sampling PLL in 28-nm CMOS. Microelectron. J. Jiawei Ding, Xuan Guo, Shan Lu, Qing Su, Tao Liu, Hanbo Jia, Yihan Li, Xinyu Liu
2025	J	`jnl`	A 25-GS/s 8-bit Current-Steering DAC With ADC-Based Duty-Cycle Detection in 40-nm CMOS. IEEE Trans. Very Large Scale Integr. Syst. Xing Li, Lei Zhou, Xuan Guo, Hanbo Jia, DanYu Wu, Jin Wu, Xinyu Liu
2025	J	`jnl`	A 500 MS/s 12b single channel SAR-assisted pipelined ADC with two-stage open-loop dynamic amplifier. Microelectron. J. Qing Su, Xuan Guo, Hanbo Jia, Heping Ma, Linzhen Wu, Kai Sun, Xinyu Liu
2025	J	`jnl`	A 500MS/s 14-bit Pipelined ADC With Startup Protection Circuit in 40 nm CMOS. IEEE Access Ben He, Xuan Guo, Hanbo Jia, Kai Sun, Xinyu Liu
2025	J	`jnl`	A 55-nm 10-GS/s 6-b Time-Interleaved SAR ADC With Bandwidth Boosting Techniques. IEEE Trans. Circuits Syst. II Express Briefs Xiuheng Wu, Yuzhen Zhang, Xuan Guo, Hanbo Jia, Linzhen Wu, Dandan Wang, Kai Sun, Xinyu Liu
2025	J	`jnl`	A Depletion-Mode GaN-Based Envelope Tracking Supply Modulator Utilizing a Novel Coupled PWM Generator. IEEE Trans. Circuits Syst. II Express Briefs Chenhao Li, Chunyue Bo, Xiaoyu Hu, Xiangcong Zhai, Ke Wei, Xinyu Liu, Weijun Luo
2025	J	`jnl`	A Low-Jitter and Low-Reference-Spur Ring-VCO-Based Injection-Locked Clock Multiplier Utilizing a Complementary-Injection Scheme and an Adaptive Pulsewidth Adjustment. IEEE J. Solid State Circuits Zedong Wang, Xuqiang Zheng, Yu He, Hua Xu, Sai Li, Zunsong Yang, Fangxu Lv, Mingche Lai, Xinyu Liu
2025	J	`jnl`	A Quad-Core VCO Incorporating Area-Saving Folded S-Shaped Tail Filtering in 28-nm CMOS. IEEE Trans. Very Large Scale Integr. Syst. Shan Lu, DanYu Wu, Xuan Guo, Hanbo Jia, Yong Chen, Xinyu Liu
2025	J	`jnl`	A dither-based background calibration circuit for pipelined ADCs in 40 nm CMOS. IEICE Electron. Express Ben He, Xuan Guo, Hanbo Jia, Kai Sun, Lei Zhou, Zhijie Chen, Xinyu Liu
2025	J	`jnl`	A genetic algorithm-based capacitor mismatch calibration scheme for SAR ADCs. Microelectron. J. Yuzhen Zhang, Xuan Guo, Hanbo Jia, Li Luo, Linzhen Wu, Dandan Wang, Xinyu Liu
2025	J	`jnl`	A high-speed single channel reconfigurable 1-GS/s to 1.5-GS/s, 8-bit to 6-bit SAR ADC in 28 nm CMOS. IEICE Electron. Express Qing Su, Xuan Guo, Hanbo Jia, Yihan Li, Kai Sun, Xinyu Liu
2025	J	`jnl`	An 8-bit 1-GHz SAR ADC with charge-sharing sampling and embedded auto-zero comparator for ultra-high-speed wireline systems. IEICE Electron. Express Jiang Xu, Xuqiang Zheng, Zedong Wang, Hua Xu, Wenxiang Zhen, Xuan Guo, Xinyu Liu
2025	J	`jnl`	An input buffer with opamp-based bootstrap circuit and cross-coupled substrate technique for 1.5-GS/s pipelined ADC in 40-nm CMOS process. IEICE Electron. Express Zeyu Li, Fangyuan Xu, Xuan Guo, Hanbo Jia, Kai Sun, Xinyu Liu
2024	J	`jnl`	A 1.25-GS/s 10-bit single-channel ring amplifier-based pipelined ADC in 28-nm CMOS. Microelectron. J. Heng Zhang, Xuan Guo, Ben He, Hanbo Jia, Xinyu Liu
2024	J	`jnl`	A 1.25-GS/s 14-bit pipelined ADC using a current-feedback flipped input buffer and large dither technique to achieve high linearity. IEICE Electron. Express Zeyu Li, Xuan Guo, Hanbo Jia, Xinyu Liu
2024	J	`jnl`	A 12bit 1.6 GS/s pipelined ADC with multi-level dither injection achieving 68 dB SFDR over PVT. Microelectron. J. Feitong Wu, Hanbo Jia, Xuan Guo, Zilin Jiang, Xinyu Liu
2024	J	`jnl`	A 16-Bit 5 GS/s DAC With Redundant-MSB-Based Digital Pre-Distortion Achieving SFDR >61 dBc Up to 2.4 GHz in 40-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs Xing Li, Lei Zhou, Xuan Guo, Hanbo Jia, DanYu Wu, Jin Wu, Xinyu Liu
2024	J	`jnl`	A 28-nm Dual-Mode Explicit Class-F₂₃ VCO With Low-Loss CM Return Path Achieving 70-400-kHz 1/f³ PN Corner Over 4.9-7.3-GHz TR. IEEE Trans. Very Large Scale Integr. Syst. Shan Lu, DanYu Wu, Xuan Guo, Hanbo Jia, Yong Chen, Xinyu Liu
2024	J	`jnl`	A wideband front-end with integrated high-voltage assisted input buffer for high-speed ADC. IEICE Electron. Express Zilin Jiang, DanYu Wu, Xuan Guo, Hanbo Jia, Shuangbao Jia, Heping Ma, Kai Sun, Xinyu Liu
2024	—	`conf`	An Injection-Locked Clock Multiplier with Adaptive Pulsewidth Adjustment and Phase Error Cancellation Achieving 43.9fs RMS Jitter and -255.5dB FoM. CICC Yu He, Xuqiang Zhenq, Zedong Wang, Zunsong Yanq, Hua Xu, Fangxu Lv, Mingche Lai, Xinyu Liu
2023	J	`jnl`	A 1-GS/s 12-bit Single-Channel Pipelined ADC in 28-nm CMOS With Input-Split Fully Differential Ring Amplifier. IEEE Trans. Very Large Scale Integr. Syst. Heng Zhang, Ben He, Xuan Guo, DanYu Wu, Xinyu Liu
2023	—	`conf`	A 64Gbps 1.36 Vppd 1.44pJ/b Fully CMOS-Style Transmitter with Active Hybrid Driver in 28nm CMOS. MWSCAS Da Fu, DanYu Wu, Xuan Guo, Hanbo Jia, Jie Fu, Shan Lu, Xinyu Liu
2021	—	`conf`	A 1.4-Vppd 64-Gb/s PAM-4 Transmitter with 4-Tap Hybrid FFE Employing Fractionally-Spaced Pre-Emphasis and Baud-Spaced De-Emphasis in 28-nm CMOS. ESSCIRC Chen Cai, Xuqiang Zheng, Yong Chen, DanYu Wu, Jian Luan, Lei Zhou, Jin Wu, Xinyu Liu
2021	—	`conf`	A Real-Time Output 50-GS/s 8-bit TI-ADC with Dedicated Calibration Techniques and Deterministic Latency. ESSCIRC Jian Luan, DanYu Wu, Xuqiang Zheng, Chen Cai, Linzhen Wu, Lei Zhou, Jin Wu, Xinyu Liu
2020	J	`jnl`	A 50-112-Gb/s PAM-4 Transmitter With a Fractional-Spaced FFE in 65-nm CMOS. IEEE J. Solid State Circuits Xuqiang Zheng, Hao Ding, Feng Zhao, DanYu Wu, Lei Zhou, Jin Wu, Fangxu Lv, Jianye Wang, Xinyu Liu
2020	J	`jnl`	Frequency-Domain Modeling and Analysis of Injection-Locked Oscillators. IEEE J. Solid State Circuits Xuqiang Zheng, Fangxu Lv, Lei Zhou, DanYu Wu, Jin Wu, Chun Zhang, Woogeun Rhee, Xinyu Liu
2019	J	`jnl`	A 1 GS/s 12-bit pipelined folding ADC with a novel encoding algorithm. IEICE Electron. Express Huasen Liu, DanYu Wu, Lei Zhou, Jian Luan, Xuan Guo, Dong Wang, Jin Wu, Xinyu Liu
2019	J	`jnl`	A 10-GS/s 8-bit 4-way interleaved folding ADC in 0.18 µm SiGe-BiCMOS. IEICE Electron. Express Huasen Liu, DanYu Wu, Lei Zhou, Yinkun Huang, Jian Luan, Xuan Guo, Dong Wang, Xuqiang Zheng, Jin Wu, Xinyu Liu
2019	C	`conf`	A 10-GS/s 8-bit SiGe ADC with Isolated 4×4 Analog Input Multiplexer. ISCAS DanYu Wu, Lei Zhou, Huasen Liu, Yinkun Huang, Jian Luan, Xuan Guo, Jin Wu, Xinyu Liu
2019	—	`conf`	A 112-Gb/s PAM-4 Transmitter With a 2-Tap Fractional-Spaced FFE in 65-nm CMOS. ESSCIRC Hao Ding, Xuqiang Zheng, DanYu Wu, Lei Zhou, Jin Wu, Fangxu Lv, Jianye Wang, Xinyu Liu
2019	J	`jnl`	An 8 GSps 14 bit RF DAC With IM3<-62 dBc up to 3.6 GHz. IEEE Trans. Circuits Syst. II Express Briefs Dong Wang, Lei Zhou, DanYu Wu, Chonghe Ma, Jinxin Xue, Xuan Guo, Jian Luan, Huasen Liu, Jin Wu, Xinyu Liu
2017	J	`jnl`	A 400-MS/s 10-b 8 interleaved SAR ADC in 0.13 um CMOS. IEICE Electron. Express Xiaoge Zhu, Lei Zhou, DanYu Wu, Jin Wu, Xinyu Liu
2017	J	`jnl`	A 6 mW 325 MS/s 8 bit SAR ADC with background offset calibration. IEICE Electron. Express Xiaoge Zhu, DanYu Wu, Lei Zhou, Chonghe Ma, Dandan Wang, Jian Luan, Yinkun Huang, Jin Wu, Xinyu Liu
2017	J	`jnl`	A four-channel time-interleaved 30-GS/s 6-bit ADC in 0.18 μm SiGe BiCMOS technology. Sci. China Inf. Sci. Xiaoge Zhu, DanYu Wu, Lei Zhou, Yinkun Huang, Jin Wu, Xinyu Liu
2016	—	`conf`	A 30Gsps 6bit DAC in SiGe BiCMOS technology. ICECS Lei Zhou, Weizhong Li, DanYu Wu, Fan Jiang, Daojun Xue, Jin Wu, Xinyu Liu
2014	J	`jnl`	A 4-GS/s 8-bit two-channel time-interleaved folding and interpolating ADC. Sci. China Inf. Sci. Fan Jiang, DanYu Wu, Lei Zhou, Jin Wu, Zhi Jin, Xinyu Liu