Xingyun Qi

25 papers A 1B 1C 7Journal 8Unranked 8
YearRankTypeTitle / Venue / Authors
2026 J jnl
CXL-DMSim: A Full-System CXL Disaggregated Memory Simulator With Comprehensive Silicon Validation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yanjing Wang, Lizhou Wu, Wentao Hong, Yang Ou, Zicong Wang, Sunfeng Gao, Jie Zhang, Sheng Ma, Dezun Dong, Xingyun Qi, Mingche Lai, Nong Xiao
2025 J jnl
A Novel High-Speed Adaptive Duobinary Digital Detector Based on the Feed-Forward Equalizer and the Maximum Likelihood Sequence Detector for Wireline Transceivers.
IEEE Trans. Very Large Scale Integr. Syst.
Chaolong Xu, Fangxu Lv, Mingche Lai, Xingyun Qi, Qiang Wang, Zhang Luo, Shijie Li, Geng Zhang
2025 J jnl
A high speed adaptive reflection cancellation equalization circuit with Floating Tap FFE and Loop-Refactored DFE for ADC-DSP-based wireline receiver.
Microelectron. J.
Cewen Liu, Xingyun Qi, Fangxu Lv, Qiang Wang, Liquan Xiao, Xiaoyue Hu, Chaolong Xu, Zhouhao Yang, Meng Li, Mingche Lai
2025 C conf
Enhancing Transformer Inference Efficiency on FPGA Through Fully Fusion and Integer-Only Quantization Techniques.
ICCD
Zhenqi Li, Yuan Li, Mingche Lai, Puguang Liu, Qiang Wang, Yankang Zhao, Hanyuan Li, Xingyun Qi
2025 — conf
FPAMM: Fine-Grained Pipeline Architecture Accelerator for the Novel Transformer Architecture - Monarch Mixer.
ICA3PP (2)
Hanyuan Li, Mingche Lai, Xingyun Qi, Puguang Liu, Qiang Wang, Zhenqi Li, Yihang Lu, Yuan Li
2025 — conf
PSCA: A FPGA-based Protein Structure Comparison Accelerator with Symmetric Simplified Matrix.
ICA3PP (6)
Hui Su, Yuan Li, Xingyun Qi, Qiang Wang, Puguang Liu, Haoyu Liao, Mingche Lai
2025 — conf
Sumeru: An Efficient Hybrid-Granularity Cache Management Scheme for CXL-SSDs.
ICA3PP (1)
Junjie Li, Xuchao Xie, Xinyu Xu, Qiulin Wu, Xingyun Qi, Zhenlong Song
2024 J jnl
A Comprehensive Simulation Framework for CXL Disaggregated Memory.
CoRR
Yanjing Wang, Lizhou Wu, Wentao Hong, Yang Ou, Zicong Wang, Sunfeng Gao, Jie Zhang, Sheng Ma, Dezun Dong, Xingyun Qi, Mingche Lai, Nong Xiao
2024 C conf
A High-performance Hardware Accelerator for Genome Alignment.
ISPA
Haoyu Liao, Yuan Li, Qiang Wang, Mingche Lai, Hui Su, Ziwen Li, Xingyun Qi
2024 J jnl
A fully digital timing background calibration algorithm based on first-order auto-correlation for time-interleaved ADCs.
Microelectron. J.
Meng Li, Fangxu Lv, Mingche Lai, Xuqiang Zheng, Heng Huang, Xingyun Qi, Geng Zhang
2024 J jnl
A low jitter and low reference spur 5GHz PLL with quadrature charge-sampling PD in 28nm CMOS process.
IEICE Electron. Express
Wenchen Wang, Fangxu Lv, Zhengbin Pang, Heng Huang, Zhang Luo, Xingyun Qi, Jiaqing Xu, Geng Zhang, Kewei Xin, Chengzhuo Zhao
2024 — conf
A reduced complexity MLSD-based adaptive Duo-PAM4 detector in 28-nm CMOS for 56-Gb/s wireline receiver.
A-SSCC
Chaolong Xu, Fangxu Lv, Mingche Lai, Zhang Luo, Xingyun Qi, Jiaqing Xu, Qiang Wang, Liquan Xiao, Cewen Liu, Hua Xu
2024 C conf
Automatic Implementation of Large-Scale CNNs on FPGA Cluster Based on HLS4ML.
ISPA
Yihang Lu, Xingyun Qi, Yuan Li, Mingche Lai, Yankang Zhao, Zhenqi Li, Hanyuan Li, Qiang Wang
2024 C conf
Optimization of TDM Using Single-ended Transmission for Multi-FPGA Platforms.
ISCAS
Haoyu Liao, Yuan Li, Puguang Liu, Qiang Wang, Mingche Lai, Xingyun Qi
2022 J jnl
A 33.33 Gb/s/wire pin-efficient 1.06 pJ/bit wireline transceiver based on CNRZ-5 for Chiplet in 28 nm CMOS.
Microelectron. J.
Mingche Lai, Geng Zhang, Fangxu Lv, Xuqiang Zheng, Heming Wang, Dongbin Lv, Chaolong Xu, Xingyun Qi
2022 J jnl
A CNRZ-7 Based Wireline Transceiver With High-Bandwidth-Density, Low-Power for D2D Communication.
IEEE Access
Geng Zhang, Mingche Lai, Fangxu Lyu, Xuqiang Zheng, Heming Wang, Dongbin Lv, Chaolong Xu, Xingyun Qi, Qing Liu
2021 C conf
MPICC: Multi-Path INT-Based Congestion Control in Datacenter Networks.
NPC
Guoyuan Yuan, Dezun Dong, Xingyun Qi, Baokang Zhao
2021 C conf
Microarchitecture of a Configurable High-Radix Router for the Post-Moore Era.
ISC
Yi Dai, Kai Lu, Junsheng Chang, Xingyun Qi, Jijun Cao, Jianmin Zhang
2021 B conf
PFT: A Congestion Avoidance Method based on Proactive Flow Throttling at Endpoints.
IM
Xingyun Qi, Mingche Lai, Dezun Dong, Yi Dai, Junsheng Chang, Jijun Cao
2020 — conf
MPLEG: A Multi-mode Physical Layer Error Generator for Link Layer Fault Tolerance Test.
ACA
Xingyun Qi, Pingjing Lu, Jijun Cao, Yi Dai, Mingche Lai, Junsheng Chang
2020 — conf
Optimal Implementation of In-Band Network Management for High-Radix Switches.
ACA
Jijun Cao, Mingche Lai, Xingyun Qi, Yi Dai, Zhengbin Pang
2017 A conf
A Scalable and Resilient Microarchitecture Based on Multiport Binding for High-Radix Router Design.
IPDPS
Yi Dai, Kefei Wang, Gang Qu, Liquan Xiao, Dezun Dong, Xingyun Qi
2009 — conf
A Fault Tolerant Bufferless Optical Interconnection Network.
ACIS-ICIS
Xingyun Qi, Quanyou Feng, Yongran Chen, Qiang Dou, Wenhua Dou
2009 C conf
BOIN: A novel Bufferless Optical Interconnection Network for high performance computer.
AICCSA
Xingyun Qi, Wei Yang, Yongran Chen, Qiang Dou, Quanyou Feng, Wenhua Dou
2006 — conf
PMPS(3): A Performance Model of Parallel Systems.
Asia-Pacific Computer Systems Architecture Conference
Yongran Chen, Xingyun Qi, Yue Qian, Wenhua Dou