Xinghua Wang

24 papers C 1Journal 13Unranked 10
YearRankTypeTitle / Venue / Authors
2026 J jnl
A 28-nm 88.3-TFLOPS/W POSIT-Approximate-Calculation-Based Digital Computing-in-Memory Macro Incorporating Final-Cycle Fusion and Joint Skipping.
IEEE J. Solid State Circuits
Hao Wu, Yong Chen, Ming Li, Bingxin Zhang, Rui Zhang, Yiyang Yuan, Yiming Yang, Jinshan Yue, Xinghua Wang, Xiaoran Li, Feng Zhang
2026 J jnl
Fama: An FPGA-Oriented Multiscalar Multiplication Accelerator Optimized via Algorithm-Hardware Co-Design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yan Xu, Jingqi Zhang, Xiyan Dong, An Wang, Xinghua Wang, Liehuang Zhu
2025 — conf
14.5 A 28nm 192.3TFLOPS/W Accurate/Approximate Dual-Mode-Transpose Digital 6T-SRAM CIM Macro for Floating-Point Edge Training and Inference.
ISSCC
Yiyang Yuan, Bingxin Zhang, Yiming Yang, Yishan Luo, Qirui Chen, Shidong Lv, Hao Wu, Cailian Ma, Ming Li, Jinshan Yue, Xinghua Wang, Guozhong Xing, Pui-In Mak, Xiaoran Li, Feng Zhang
2025 J jnl
A 28-nm 19.9-to-258.5-TOPS/W 8b Digital Computing-in-Memory Processor With Two-Cycle Macro Featuring Winograd-Domain Convolution and Macro-Level Parallel Dual-Side Sparsity.
IEEE J. Solid State Circuits
Hao Wu, Yong Chen, Yiyang Yuan, Jinshan Yue, Xinghua Wang, Xiaoran Li, Feng Zhang
2025 J jnl
A 7.2-16 GHz 50%-LO Receiver With Enhanced Linearity and High Dynamic Range in 55-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs
Xuzhi Liu, Zicheng Liu, Fang Han, Quanwen Qi, Xinghua Wang, Zhiming Chen
2025 — conf
Design and Implementation of Broadband Real-time Spectrum Analysis System Based on FPGA.
BDICN
Meini Tang, Shiwei Ren, Pengjie Li, Fang Si, Lei Zhang, Xiyan Dong, Xiaoran Li, Xinghua Wang
2024 — conf
34.6 A 28nm 72.12TFLOPS/W Hybrid-Domain Outer-Product Based Floating-Point SRAM Computing-in-Memory Macro with Logarithm Bit-Width Residual ADC.
ISSCC
Yiyang Yuan, Yiming Yang, Xinghua Wang, Xiaoran Li, Cailian Ma, Qirui Chen, Meini Tang, Xi Wei, Zhixian Hou, Jialiang Zhu, Hao Wu, Qirui Ren, Guozhong Xing, Pui-In Mak, Feng Zhang
2024 J jnl
A 28-nm Computing-in-Memory-Based Super-Resolution Accelerator Incorporating Macro-Level Pipeline and Texture/Algebraic Sparsity.
IEEE Trans. Circuits Syst. I Regul. Pap.
Hao Wu, Yong Chen, Yiyang Yuan, Jinshan Yue, Xiangqu Fu, Qirui Ren, Qing Luo, Pui-In Mak, Xinghua Wang, Feng Zhang
2023 J jnl
A Security-Enhanced, Charge-Pump-Free, ISO14443-A-/ISO10373-6-Compliant RFID Tag With 16.2-μW Embedded RRAM and Reconfigurable Strong PUF.
IEEE Trans. Very Large Scale Integr. Syst.
Qirui Ren, Qiang Huo, Zhisheng Chen, Qi Gao, Yiming Wang, Yiming Yang, Hao Wu, Xiangqu Fu, Xiaoxin Xu, Qing Luo, Jianfeng Gao, Chengying Chen, Xiaojin Zhao, Dengyun Lei, Xinghua Wang, Feng Zhang, Yong Chen, Pui-In Mak
2023 J jnl
An N-Path Sub-GHz Ultra-Low Power Receiver Exploiting an N-Path Notch Filter Topology in 90 nm CMOS.
IEEE Access
Lei Lei, Xiao Li, Xiaoran Li, Zicheng Liu, Quanwen Qi, Xinghua Wang, Weijiang Wang
2022 — conf
Design of a Time Detector with Adjustable Resolution.
EITCE
Xiaofan Liu, Zhiming Chen, Xiaoran Li, Xinghua Wang, Lei Zhang
2021 — conf
A 4×25-Gb/s Serializer with Integrated CDR and 3-Tap FFE Driver for NIC Optical Interconnects.
ICTA
Ming Zhong, Qingwen Wang, Yong Chen, Jian Liu, Liyuan Liu, Xinghua Wang, Xiaoming Xiong, Nan Qi
2021 J jnl
Design of a Wideband dB-Linear Variable Gain Amplifier With Continuous Gain Adjusting in 90-nm CMOS Technology.
IEEE Access
Chenxuan Fan, Zhiming Chen, Zicheng Liu, Xiao Li, Xiaoran Li, Quanwen Qi, Wei Gu, Xinghua Wang
2020 J jnl
A ReRAM-Based Computing-in-Memory Convolutional-Macro With Customized 2T2R Bit-Cell for AIoT Chip IP Applications.
IEEE Trans. Circuits Syst. II Express Briefs
Fei Tan, Yiming Wang, Yiming Yang, Liran Li, Tian Wang, Feng Zhang, Xinghua Wang, Jianfeng Gao, Yongpan Liu
2019 J jnl
A Few-Step and Low-Cost Memristor Logic Based on MIG Logic for Frequent-Off Instant-On Circuits in IoT Applications.
IEEE Trans. Circuits Syst. II Express Briefs
Yiming Wang, Yun Li, Haihua Shen, Dongyu Fan, Wei Wang, Ling Li, Qi Liu, Feng Zhang, Xinghua Wang, Meng-Fan Chang, Ming Liu
2018 J jnl
A 0.6V, 8.4uW AFE circuit for biomedical signal recording.
Microelectron. J.
Chengying Chen, Liming Chen, Xinghua Wang, Feng Zhang
2018 C conf
A 66-dB SNDR, 8-μW analog front-end for ECG/EEG recording application.
ISCAS
Chengying Chen, Liming Chen, Xinghua Wang, Feng Zhang
2017 — conf
A 76μW, 58-dB SNDR analog front-end chip for implantable intraocular pressure detection.
ASICON
Chengying Chen, Liming Chen, Xinghua Wang, Feng Zhang
2017 J jnl
A CMOS digital step X-type attenuator with low process variations.
IEICE Electron. Express
Jiayue Wan, Zhiming Chen, Xinghua Wang
2017 J jnl
DOA estimation based on the difference and sum coarray for coprime arrays.
Digit. Signal Process.
Xinghua Wang, Zhenhong Chen, Shiwei Ren, Shan Cao
2013 — conf
A Whole Integrated System for Detection of Neural Signal and Wireless Transmission.
GreenCom/iThings/CPScom
Hua Dang, Ruoyuan Qu, Zhiming Chen, Xiaoyan Gui, Xinghua Wang
2013 — conf
Circuit Design of Analog Front-End for Neural Signal Detection.
GreenCom/iThings/CPScom
Hua Dang, Lei Zhang, Zhiming Chen, Xiaoyan Gui, Xinghua Wang
2013 — conf
Design and Implementation of a CMOS 1Gsps 5bit Flash ADC with Offset Calibration.
GreenCom/iThings/CPScom
Shiwen Li, Hua Dang, Peng Gao, Xiaoyan Gui, Zhiming Chen, Xinghua Wang, Shun'an Zhong
2013 — conf
Design and Implementation of a Circuit System for Neural Signal Detection.
GreenCom/iThings/CPScom
Hua Dang, Xiao Li, Zhiming Chen, Xiaoyan Gui, Xinghua Wang, Shun'an Zhong