Xing Li - RankMe

45 papers A* 9A 5B 2C 1Journal 25Unranked 3

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	Beyond Speedup - Utilizing KV Cache for Sampling and Reasoning. CoRR Zeyu Xing, Xing Li, Hui-Ling Zhen, Mingxuan Yuan, Sinno Jialin Pan
2026	J	`jnl`	ReThinker: Scientific Reasoning by Rethinking with Guided Reflection and Confidence Control. CoRR Zhentao Tang, Yuqi Cui, Shixiong Kai, Wenqian Zhao, Ke Ye, Xing Li, Anxin Tian, Zehua Pei, Hui-Ling Zhen, Shoubo Hu, Xiaoguang Li, Yunhe Wang, Mingxuan Yuan
2026	J	`jnl`	SwiftMem: Fast Agentic Memory via Query-aware Indexing. CoRR Anxin Tian, Yiming Li, Xing Li, Hui-Ling Zhen, Lei Chen, Xianzhi Yu, Zhenhua Dong, Mingxuan Yuan
2026	J	`jnl`	Unleashing Low-Bit Inference on Ascend NPUs: A Comprehensive Evaluation of HiFloat Formats. CoRR Pengxiang Zhao, Hui-Ling Zhen, Xing Li, Han Bao, Weizhe Lin, Zhiyuan Yang, Manyi Zhang, Yuanyong Luo, Ziwei Yu, Xin Wang, Mingxuan Yuan, Xianzhi Yu, Zhenhua Dong
2026	J	`jnl`	What Matters For Safety Alignment? CoRR Xing Li, Hui-Ling Zhen, Lihao Yin, Xianzhi Yu, Zhenhua Dong, Mingxuan Yuan
2026	J	`jnl`	Why Attention Patterns Exist: A Unifying Temporal Perspective Analysis. CoRR Qingyue Yang, Jie Wang, Xing Li, Yinqi Bai, Xialiang Tong, Huiling Zhen, Jianye Hao, Mingxuan Yuan, Bin Li
2025	J	`jnl`	A Delay-Driven Iterative Technology Mapping Framework. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Junfeng Liu, Liwei Ni, Lei Chen, Xing Li, Qinghua Zhao, Xingquan Li, Shuai Ma
2025	J	`jnl`	A Unified Parallel Framework for LUT Mapping and Logic Optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Tianji Liu, Yang Sun, Lei Chen, Xing Li, Mingxuan Yuan, Evangeline F. Y. Young
2025	J	`jnl`	AttentionPredictor: Temporal Pattern Matters for Efficient LLM Inference. CoRR Qingyue Yang, Jie Wang, Xing Li, Zhihai Wang, Chen Chen, Lei Chen, Xianzhi Yu, Wulong Liu, Jianye Hao, Mingxuan Yuan, Bin Li
2025	J	`jnl`	Behavioral Fingerprinting of Large Language Models. CoRR Zehua Pei, Hui-Ling Zhen, Yingchun Zhang, Zhiyuan Yang, Xing Li, Xianzhi Yu, Mingxuan Yuan, Bei Yu
2025	—	`conf`	Circuit Synthesis based on Hierarchical Conditional Diffusion. ACM Great Lakes Symposium on VLSI Xinyi Zhou, Xing Li, Yingzhao Lian, Yiwen Wang, Lei Chen, Mingxuan Yuan, Jianye Hao, Guangyong Chen, Pheng-Ann Heng
2025	A*	`conf`	Circuit Transformer: A Transformer That Preserves Logical Equivalence. ICLR Xihan Li, Xing Li, Lei Chen, Xing Zhang, Mingxuan Yuan, Jun Wang
2025	A*	`conf`	EDGE: DBMS-Empowered Boolean Decomposition for GIG Synthesis. DAC Ruofei Tang, Xuliang Zhu, Xinyi Zhang, Lei Chen, Xing Li, Mingxuan Yuan, Jianliang Xu
2025	A*	`conf`	ELF: Efficient Logic Synthesis by Pruning Redundancy in Refactoring. DAC Dimitris Tsaras, Xing Li, Lei Chen, Zhiyao Xie, Mingxuan Yuan
2025	J	`jnl`	ELF: Efficient Logic Synthesis by Pruning Redundancy in Refactoring. CoRR Dimitris Tsaras, Xing Li, Lei Chen, Zhiyao Xie, Mingxuan Yuan
2025	A*	`conf`	KVTuner: Sensitivity-Aware Layer-Wise Mixed-Precision KV Cache Quantization for Efficient and Nearly Lossless LLM Inference. ICML Xing Li, Zeyu Xing, Yiming Li, Linping Qu, Hui-Ling Zhen, Yiwu Yao, Wulong Liu, Sinno Jialin Pan, Mingxuan Yuan
2025	J	`jnl`	KVTuner: Sensitivity-Aware Layer-wise Mixed Precision KV Cache Quantization for Efficient and Nearly Lossless LLM Inference. CoRR Xing Li, Zeyu Xing, Yiming Li, Linping Qu, Hui-Ling Zhen, Wulong Liu, Yiwu Yao, Sinno Jialin Pan, Mingxuan Yuan
2025	—	`conf`	MTLSO: A Multi-Task Learning Approach for Logic Synthesis Optimization. ASP-DAC Faezeh Faez, Raika Karimi, Yingxue Zhang, Xing Li, Lei Chen, Mingxuan Yuan, Mahdi Biparva
2025	A	`conf`	Maximum Fanout-Free Window Enumeration: Towards Multi-Output Sub-Structure Synthesis. DATE Ruofei Tang, Xuliang Zhu, Lei Chen, Xing Li, Xin Huang, Mingxuan Yuan, Jianliang Xu
2025	J	`jnl`	SVDq: 1.25-bit and 410x Key Cache Compression for LLM Attention. CoRR Hong Yankun, Xing Li, Hui-Ling Zhen, Xianzhi Yu, Wulong Liu, Mingxuan Yuan
2025	J	`jnl`	Scaling Up, Speeding Up: A Benchmark of Speculative Decoding for Efficient LLM Test-Time Scaling. CoRR Shengyin Sun, Yiming Li, Xing Li, Yingzhao Lian, Weizhe Lin, Hui-Ling Zhen, Zhiyuan Yang, Chen Chen, Xianzhi Yu, Mingxuan Yuan, Chen Ma
2025	J	`jnl`	Towards Efficient Agents: A Co-Design of Inference Architecture and System. CoRR Weizhe Lin, Hui-Ling Zhen, Shuai Yang, Xian Wang, Renxi Liu, Hanting Chen, Wangze Zhang, Chuansai Zhou, Yiming Li, Chen Chen, Xing Li, Zhiyuan Yang, Xiaosong Li, Xianzhi Yu, Zhenhua Dong, Mingxuan Yuan, Yunhe Wang
2025	J	`jnl`	TrimR: Verifier-based Training-Free Thinking Compression for Efficient Test-Time Scaling. CoRR Weizhe Lin, Xing Li, Zhiyuan Yang, Xiaojin Fu, Hui-Ling Zhen, Yaoyuan Wang, Xianzhi Yu, Wulong Liu, Xiaosong Li, Mingxuan Yuan
2025	J	`jnl`	Unlocking Efficient Long-to-Short LLM Reasoning with Model Merging. CoRR Han Wu, Yuxuan Yao, Shuqi Liu, Zehua Liu, Xiaojin Fu, Xiongwei Han, Xing Li, Hui-Ling Zhen, Tao Zhong, Mingxuan Yuan
2024	A*	`conf`	A Circuit Domain Generalization Framework for Efficient Logic Synthesis in Chip Design. ICML Zhihai Wang, Lei Chen, Jie Wang, Yinqi Bai, Xing Li, Xijun Li, Mingxuan Yuan, Jianye Hao, Yongdong Zhang, Feng Wu
2024	J	`jnl`	Circuit Transformer: End-to-end Circuit Design by Predicting the Next Gate. CoRR Xihan Li, Xing Li, Lei Chen, Xing Zhang, Mingxuan Yuan, Jun Wang
2024	B	`conf`	FineMap: A Fine-grained GPU-parallel LUT Mapping Engine. ASPDAC Tianji Liu, Lei Chen, Xing Li, Mingxuan Yuan, Evangeline F. Y. Young
2024	J	`jnl`	Logic Synthesis Optimization with Predictive Self-Supervision via Causal Transformers. CoRR Raika Karimi, Faezeh Faez, Yingxue Zhang, Xing Li, Lei Chen, Mingxuan Yuan, Mahdi Biparva
2024	J	`jnl`	Logic Synthesis with Generative Deep Neural Networks. CoRR Xihan Li, Xing Li, Lei Chen, Xing Zhang, Mingxuan Yuan, Jun Wang
2024	J	`jnl`	MTLSO: A Multi-Task Learning Approach for Logic Synthesis Optimization. CoRR Faezeh Faez, Raika Karimi, Yingxue Zhang, Xing Li, Lei Chen, Mingxuan Yuan, Mahdi Biparva
2024	A	`conf`	RTLRewriter: Methodologies for Large Models aided RTL Code Optimization. ICCAD Xufeng Yao, Yiwen Wang, Xing Li, Yingzhao Lian, Ran Chen, Lei Chen, Mingxuan Yuan, Hong Xu, Bei Yu
2024	J	`jnl`	RTLRewriter: Methodologies for Large Models aided RTL Code Optimization. CoRR Xufeng Yao, Yiwen Wang, Xing Li, Yingzhao Lian, Ran Chen, Lei Chen, Mingxuan Yuan, Hong Xu, Bei Yu
2024	J	`jnl`	SeaDAG: Semi-autoregressive Diffusion for Conditional Directed Acyclic Graph Generation. CoRR Xinyi Zhou, Xing Li, Yingzhao Lian, Yiwen Wang, Lei Chen, Mingxuan Yuan, Jianye Hao, Guangyong Chen, Pheng-Ann Heng
2024	A*	`conf`	Towards Next-Generation Logic Synthesis: A Scalable Neural Circuit Generation Framework. NeurIPS Zhihai Wang, Jie Wang, Qingyue Yang, Yinqi Bai, Xing Li, Lei Chen, Jianye Hao, Mingxuan Yuan, Bin Li, Yongdong Zhang, Feng Wu
2023	J	`jnl`	A Circuit Domain Generalization Framework for Efficient Logic Synthesis in Chip Design. CoRR Zhihai Wang, Lei Chen, Jie Wang, Xing Li, Yinqi Bai, Xijun Li, Mingxuan Yuan, Jianye Hao, Yongdong Zhang, Feng Wu
2023	A*	`conf`	A Database Dependent Framework for K-Input Maximum Fanout-Free Window Rewriting. DAC Xuliang Zhu, Ruofei Tang, Lei Chen, Xing Li, Xin Huang, Mingxuan Yuan, Weihua Sheng, Jianliang Xu
2023	C	`conf`	AiMap: Learning to Improve Technology Mapping for ASICs via Delay Prediction. ICCD Junfeng Liu, Liwei Ni, Xingquan Li, Min Zhou, Lei Chen, Xing Li, Qinghua Zhao, Shuai Ma
2023	—	`conf`	CPP: A Multi-Level Circuit Partitioning Predictor for Hardware Verification Systems. ACM Great Lakes Symposium on VLSI Xinshi Zang, Lei Chen, Xing Li, Wilson W. K. Thong, Weihua Sheng, Evangeline F. Y. Young, Martin D. F. Wong
2023	A	`conf`	EasyMap: Improving Technology Mapping via Exploration-Enhanced Heuristics and Adaptive Sequencing. ICCAD Peiyu Wang, Anqi Lu, Xing Li, Junjie Ye, Lei Chen, Mingxuan Yuan, Jianye Hao, Junchi Yan
2023	A	`conf`	EffiSyn: Efficient Logic Synthesis with Dynamic Scoring and Pruning. ICCAD Xing Li, Lei Chen, Jiantang Zhang, Shuang Wen, Weihua Sheng, Yu Huang, Mingxuan Yuan
2023	A*	`conf`	Lightweight Structural Choices Operator for Technology Mapping. DAC Antoine Grosnit, Matthieu Zimmer, Rasul Tutunov, Xing Li, Lei Chen, Fan Yang, Mingxuan Yuan, Haitham Bou-Ammar
2023	B	`conf`	SGDP: A Stream-Graph Neural Network Based Data Prefetcher. IJCNN Yiyuan Yang, Rongshang Li, Qiquan Shi, Xijun Li, Gang Hu, Xing Li, Mingxuan Yuan
2023	J	`jnl`	SGDP: A Stream-Graph Neural Network Based Data Prefetcher. CoRR Yiyuan Yang, Rongshang Li, Qiquan Shi, Xijun Li, Gang Hu, Xing Li, Mingxuan Yuan
2022	A*	`conf`	HIMap: a heuristic and iterative logic synthesis approach. DAC Xing Li, Lei Chen, Fan Yang, Mingxuan Yuan, Hongli Yan, Yupeng Wan
2021	A	`conf`	Block Access Pattern Discovery via Compressed Full Tensor Transformer. CIKM Xing Li, Qiquan Shi, Gang Hu, Lei Chen, Hui Mao, Yiyuan Yang, Mingxuan Yuan, Jia Zeng, Zhuo Cheng