Xin Wang - RankMe

11 papers Journal 3Unranked 8

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	A Duty-Cycle Switching 30-Gb/s Burst-Mode CDR With 1.6-ns Locking Time in 28-nm CMOS. IEEE J. Solid State Circuits Xin Wang, Achim Vandierendonck, Bruno Govaerts, Tinus Pannier, Warre Geeroms, Caro Meysmans, Johan Bauwelinck, Guy Torfs
2025	—	`conf`	60 Gbaud NRZ Transmission with 0.94 PJ/b Direct-Drive Optical Transmitter Using SM 1060 NM VCSEL Over 5 KM SMF. ECOC Arijit Karmakar, Torben Onselaere, Achim Vandierendonck, Xin Wang, Nishant Singh, Joris Van Kerrebrouck, Guy Torfs, Johan Bauwelinck
2025	—	`conf`	A Co-Designed DC-Coupled 30-Gbps Burst-Mode Receiver and CDR with 3.2-ns Locking Time for Fast Optical Switching. ECOC Xin Wang, Gertjan Coudyzer, Achim Vandierendonck, Simone Cammarata, Nishant Singh, Tinus Pannier, Bruno Govaerts, Warre Geeroms, Caro Meysmans, Xin Yin, Johan Bauwelinck, Guy Torfs
2025	—	`conf`	An All-Silicon 4x56 Gbit/s NRZ, 1 pJ/bit Optical Receiver with Ge-on-Si PDs and 28nm CMOS TIA Array. ECOC Bruno Govaerts, Xin Wang, Axl Bomhals, Jakob Declercq, Arijit Karmakar, Geert Van Steenberge, Jeroen Missinne, Cedric Bruynsteen, Nishant Singh, Guy Torfs, Johan Bauwelinck, Xin Yin, Peter Ossieur
2023	J	`jnl`	Photonic Network-on-Wafer for Multichiplet GPUs. IEEE Micro Shiqing Zhang, Ziyue Zhang, Mahmood Naderan-Tahan, Hossein SeyyedAghaei, Xin Wang, He Li, Senbiao Qin, Didier Colle, Guy Torfs, Mario Pickavet, Johan Bauwelinck, Günther Roelkens, Lieven Eeckhout
2022	—	`conf`	Co-designed electro-optical integrated frontend circuits for high speed transceivers. OECC/PSC Johan Bauwelinck, Marijn Verbeke, Joris Lambrecht, Michael Vanhoecke, Laurens Breyne, Gertjan Coudyzer, Jakob Declercq, Bart Moeneclaey, R. Ahmed, Nishant Singh, Cedric Bruynsteen, Cheng Wang, Shengpu Niu, Xin Wang, Tinus Pannier, Ye Gu, Achim Vandierendonck, Borre Van Lombergen, Kieran De Bruyn, Joris Van Kerrebrouck, Michiel Verplaetse, Guy Torfs, Xin Yin, Peter Ossieur
2020	—	`conf`	PAM-X™: A 25Gb/s-PAM4 Optical Transceiver Chipset for 5G Optical Front-Haul. OFC Xin Wang, Yi Peng, Yuanxi Zhang, Tao Xia, Yifan Wu, Juncheng Wang, Lei Wang, Liujia Song, Lei Zhao, Shenglong Zhuo, Quan Pan, Xuefeng Chen, Patrick Yin Chiang, Rui Bai
2019	—	`conf`	A 50Gb/s PAM-4 Retimer-CDR + VCSEL Driver with Asymmetric Pulsed Pre-Emphasis Integrated into a Single CMOS Die. OFC Shang Hu, Tingyu Yao, Bozhi Yin, Chunyu Song, Lei Zhao, Juncheng Wang, Lei Wang, Rui Bai, Xin Wang, Tao Xia, Yi Peng, Binbin Yao, Yuan Li, Xuefeng Chen, Quan Pan, Nan Qi, Patrick Yin Chiang
2019	J	`jnl`	A Fully Integrated 25 Gb/s Low-Noise TIA+CDR Optical Receiver Designed in 40-nm-CMOS. IEEE Trans. Circuits Syst. II Express Briefs Juncheng Wang, Quan Pan, Yajie Qin, Xuefeng Chen, Shang Hu, Rui Bai, Xin Wang, Yaxin Cai, Tao Xia, Yuanxi Zhang, Jianxu Ma, Nan Qi, Patrick Yin Chiang
2018	—	`conf`	A Fully-Integrated 25Gb/s Low-Noise TIA+CDR Optical Receiver designed in 40nm-CMOS. A-SSCC Juncheng Wang, Xuefeng Chen, Shang Hu, Yaxin Cai, Rui Bai, Xin Wang, Yuanxi Zhang, Shenglong Zhuo, Chang Liu, Bozhi Yin, Jianxu Ma, Hao Yan, Jiangao Xuan, Milton Lu, Tao Xia, Nan Qi, Patrick Yin Chiang
2013	—	`conf`	A wideband CMOS variable-gain low noise amplifier with novel attenuator. ASICON Tao Cheng, Tao Yang, Xin Wang, Zhangwen Tang