Xin-Yu Shih

33 papers C 2Misc 1Journal 15Unranked 15
YearRankTypeTitle / Venue / Authors
2025 J jnl
Design and Hardware Implementation of Low-Latency 4-Splitting Tree-Structure-Based K-Means Clustering Trainer and Classifier Chip for Detecting Cybersecurity Attacks.
IEEE Trans. Circuits Syst. II Express Briefs
Xin-Yu Shih, Hsi-Cheng Chen, Xin-Liang Hung
2024 J jnl
High-Area-Efficiency Polar Decoder Chip Architecture Reconfiguring SCL-Decoding With Reconfigurable Pipelined Sorter and SCF-Decoding With Non-Uniform 4-Segment CRC.
IEEE Trans. Circuits Syst. II Express Briefs
Xin-Yu Shih, Yu-Chen Lee, Geng-Hong Li, Jia-Han Xie
2023 J jnl
Design and Implementation of Decision-Tree (DT) Online Training Hardware Using Divider-Free GI Calculation and Speeding-Up Double-Root Classifier.
IEEE Trans. Circuits Syst. I Regul. Pap.
Xin-Yu Shih, Yao Chiu, Hsiang-En Wu
2023 J jnl
Design and Implementation of Dual-Mode Support Vector Machine (SVM) Trainer and Classifier Chip Architecture for Human Disease Detection Applications.
IEEE Trans. Circuits Syst. I Regul. Pap.
Xin-Yu Shih, Hsiang-En Wu, Ming-Xian Cai
2023 — conf
Low-Cost Hardware Design of Fast 3D-Sorter Engine for Successive Cancellation List Polar-Decoders in 5G Applications.
ICCE-Taiwan
Xin-Yu Shih, Lok Hin Samuel Leung, Geng-Hong Li
2023 J jnl
Unified chip hardware architecture of KD-tree mean-based trainer and speeding-up classifier with repeat-point searching for various applications.
Integr.
Xin-Yu Shih, Chen-Yen Song, Yao-Yu Lu
2022 — conf
A Systematic and Generic Correlation-Based Design Approach for Data Sample Reduction in ML-Training.
ICCE-TW
Xin-Yu Shih, Ming-Jyun Wu, Hsiang-En Wu
2022 — conf
Design Methodology of Queue-Based Fast Classification for Sequential Minimal Optimization in SVM ML-Training.
ICCE-TW
Xin-Yu Shih, Hsiang-En Wu
2022 — conf
Design and Analysis of 7x7 Median Filter with 8-Step Low-Complexity Fast Searching Approach for Undersea Image Processing Applications.
ICCE-TW
Xin-Yu Shih, Hsiang-En Wu
2022 J jnl
Reconfigurable Hardware Architecture of Area-Efficient Multimode Successive Cancellation (SC) Decoder.
IEEE Trans. Circuits Syst. II Express Briefs
Xin-Yu Shih, Jui-Hung Tsai, Bing-Xuan Li, Chi-Ping Huang
2022 — conf
Scalable and Reconfigurable Architecture of Modified KD-Tree ML-Classifier with 5-Point Searching.
ICCE-TW
Xin-Yu Shih, Chen-Yen Song
2019 — conf
Design and Analysis of Cost-Efficient Ultra-High-Order Matched Filter Architecture Using 4-Phase Calculating Paths for Underwater Applications.
ICCE-TW
Xin-Yu Shih
2019 J jnl
Flexible design and implementation of QC-Based LDPC decoder architecture for on-line user-defined matrix downloading and efficient decoding.
Integr.
Xin-Yu Shih, Hong-Ru Chou
2019 — conf
VLSI Architecture of 36-Mode Reconfigurable FFT Hardware Chip with Newly-Developed 2D-FIFO Arrangement Structure.
ICSAI
Xin-Yu Shih
2018 J jnl
Design and Implementation of Flexible and Reconfigurable SDF-Based FFT Chip Architecture With Changeable-Radix Processing Elements.
IEEE Trans. Circuits Syst. I Regul. Pap.
Xin-Yu Shih, Hong-Ru Chou, Yue-Qu Liu
2018 J jnl
Reconfigurable VLSI design of a changeable hybrid-radix FFT hardware architecture with 2D-FIFO storing structure for 3GPP LTE systems.
ICT Express
Xin-Yu Shih, Hong-Ru Chou
2018 J jnl
VLSI Design and Implementation of Reconfigurable 46-Mode Combined-Radix-Based FFT Hardware Architecture for 3GPP-LTE Applications.
IEEE Trans. Circuits Syst. I Regul. Pap.
Xin-Yu Shih, Hong-Ru Chou, Yue-Qu Liu
2018 J jnl
VLSI design and implementation of a reconfigurable hardware-friendly Polar encoder architecture for emerging high-speed 5G system.
Integr.
Xin-Yu Shih, Po-Chun Huang, Hong-Ru Chou
2017 J jnl
48-Mode Reconfigurable Design of SDF FFT Hardware Architecture Using Radix-3
IEEE Trans. Circuits Syst. I Regul. Pap.
Xin-Yu Shih, Yue-Qu Liu, Hong-Ru Chou
2017 — conf
A 2-D grouping FIFO based hardware architecture for supporting 36-mode hybrid-radix FFT design in 3GPP-LTE systems.
GCCE
Xin-Yu Shih, Hong-Ru Chou
2017 — conf
Cost-efficient hardware design of coarse and fine rotation based FFT twiddle factor generator for 3GPP LTE applications.
GCCE
Xin-Yu Shih, Yue-Qu Liu
2017 C conf
Reconfigurable hardware design of low-area-cost computing kernel engine for different radixes of single-path delay feedback FFT systems.
ICCE
Xin-Yu Shih, Hong-Ru Chou
2016 — conf
High-speed low-area-cost VLSI design of polar codes encoder architecture using radix-k processing engines.
GCCE
Xin-Yu Shih, Po-Chun Huang, Yu-Chun Chen
2016 — conf
LEGO-based VLSI design and implementation of polar codes encoder architecture with radix-2 processing engines.
APCCAS
Xin-Yu Shih, Po-Chun Huang, Yu-Chun Chen
2016 — conf
Reconfigurable VLSI design of processing kernel for multiple-radix single-path delay feedback FFT systems.
GCCE
Xin-Yu Shih, Hong-Ru Chou, Yue-Qu Liu
2014 J jnl
A Highly-Efficient Multi-Band Multi-Mode All-Digital Quadrature Transmitter.
IEEE Trans. Circuits Syst. I Regul. Pap.
Hua Wang, Chun-Hsien Peng, Yaopei Chang, Richard Z. Huang, Chih-Wei Chang, Xin-Yu Shih, Chia-Jui Hsu, Paul C. P. Liang, Ali M. Niknejad, George Chien, Chao Long Tsai, H. C. Hwang
2013 — conf
A 0.27mm
ISSCC
Jie-Wei Lai, Chi-Hsueh Wang, Kaipon Kao, Anson Lin, Yi-Hsien Cho, Lan-Chou Cho, Meng-Hsiung Hung, Xin-Yu Shih, Che-Min Lin, Sheng-Hong Yan, Yuan-Hung Chung, Paul C. P. Liang, Guang-Kaai Dehng, Hung-Sung Li, George Chien, Robert Bogdan Staszewski
2012 J jnl
Matrix Merging Scheme and Efficient Decoding Techniques for Reconfigurable QC-LDPC Decoders.
J. Signal Process. Syst.
Min-An Chao, Xin-Yu Shih, An-Yeu Wu
2009 — conf
A 52-mW 8.29mm
ASP-DAC
Xin-Yu Shih, Cheng-Zhou Zhan, Cheng-Hung Lin, An-Yeu Wu
2009 — conf
A Channel-Adaptive Early Termination strategy for LDPC decoders.
SiPS
Yu-Hsin Chen, Yi-Ju Chen, Xin-Yu Shih, An-Yeu Wu
2009 C conf
A Triple-mode LDPC Decoder Design for IEEE 802.11n SYSTEM.
ISCAS
Min-An Chao, Jen-Yang Wen, Xin-Yu Shih, An-Yeu Wu
2008 J jnl
An 8.29 mm
IEEE J. Solid State Circuits
Xin-Yu Shih, Cheng-Zhou Zhan, Cheng-Hung Lin, An-Yeu Wu
2008 Misc conf
High-performance scheduling algorithm for partially parallel LDPC decoder.
ICASSP
Cheng-Zhou Zhan, Xin-Yu Shih, An-Yeu Wu