Xijiang Lin - RankMe

61 papers A* 1A 14B 3C 1Misc 12Journal 9Unranked 20

Year	Rank	Type	Title / Venue / Authors
2024	—	`conf`	AI Driven Testing. ITC-Asia Yu Huang, Alex Yu, Louis Liu, Xijiang Lin
2024	—	`conf`	DFT for Complex Designs and Test Data Management. ITC-Asia Wu Yang, Jinshan Yu, Pearl He, Xijiang Lin
2021	—	`conf`	On Modeling CMOS Library Cells for Cell Internal Fault Test Pattern Generation. ATS Xijiang Lin, Wu-Tung Cheng, Takeo Kobayashi, Andreas Glowatz
2021	J	`jnl`	Single Test Type to Replace Broadside and Skewed-Load Tests for Transition Faults. IEEE Trans. Very Large Scale Integr. Syst. Irith Pomeranz, Xijiang Lin
2021	Misc	`conf`	Timing Critical Path Validation for Intel ATOM Cores Using Structural Test. VTS Wei Li, Shih-Yu Yang, Khen Wee, Ricardo Sanchez, Jay Desai, Kun-Han Tsai, Xijiang Lin
2020	A	`conf`	Test Challenges of Intel IA Cores. ITC Uri Shpiro, Khen Wee, Kun-Han Tsai, Justyna Zawada, Xijiang Lin
2019	B	`conf`	On Generating Fault Diagnosis Patterns for Designs with X Sources. ETS Xijiang Lin, Sudhakar M. Reddy
2019	—	`conf`	TEA: A Test Generation Algorithm for Designs with Timing Exceptions. ATS Naixing Wang, Chen Wang, Kun-Han Tsai, Wu-Tung Cheng, Xijiang Lin, Mark Kassab, Irith Pomeranz
2017	—	`conf`	Functional Broadside Test Generation Using a Commercial ATPG Tool. ISVLSI Naixing Wang, Bo Yao, Xijiang Lin, Irith Pomeranz
2017	A	`conf`	On applying scan based structural test for designs with dual-edge triggered flip-flops. ITC Xijiang Lin
2016	—	`conf`	On Achieving Maximal Chain Diagnosis Resolution through Test Pattern Selection. ATS Xijiang Lin, Sudhakar M. Reddy, Wu-Tung Cheng
2016	J	`jnl`	Thermal-Aware Small-Delay Defect Testing in Integrated Circuits for Mitigating Overkill. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Dong Xiang, Kele Shen, Bhargab B. Bhattacharya, Xiaoqing Wen, Xijiang Lin
2016	B	`conf`	Transistor stuck-on fault detection tests for digital CMOS circuits. ETS Xijiang Lin, Sudhakar M. Reddy, Janusz Rajski
2015	—	`conf`	On Improving Transition Test Set Quality to Detect CMOS Transistor Stuck-Open Faults. ATS Xijiang Lin, Wu-Tung Cheng, Janusz Rajski
2015	A	`conf`	On generating high quality tests based on cell functions. ITC Xijiang Lin, Sudhakar M. Reddy
2015	Misc	`conf`	Using Boolean Tests to Improve Detection of Transistor Stuck-Open Faults in CMOS Digital Logic Circuits. VLSID Xijiang Lin, Sudhakar M. Reddy, Janusz Rajski
2014	—	`ch.`	Timing-Aware ATPG. Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits Mark Kassab, Benoit Nadeau-Dostie, Xijiang Lin
2014	B	`conf`	Using dynamic shift to reduce test data volume in high-compression designs. ETS Xijiang Lin, Mark Kassab, Janusz Rajski
2013	—	`conf`	Multicycle-aware At-speed Test Methodology. Asian Test Symposium Kun-Han Tsai, Xijiang Lin
2013	J	`jnl`	Test compaction for small-delay defects using an effective path selection scheme. ACM Trans. Design Autom. Electr. Syst. Dong Xiang, Jianbo Li, Krishnendu Chakrabarty, Xijiang Lin
2012	—	`conf`	On Utilizing Test Cube Properties to Reduce Test Data Volume Further. Asian Test Symposium Xijiang Lin, Janusz Rajski
2012	—	`conf`	Power Supply Droop and Its Impacts on Structural At-Speed Testing. Asian Test Symposium Xijiang Lin
2011	—	`conf`	Low power testing - What can commercial DFT tools provide? IGCC Xijiang Lin
2011	—	`conf`	Power Aware Embedded Test. Asian Test Symposium Xijiang Lin, Elham K. Moghaddam, Nilanjan Mukherjee, Benoit Nadeau-Dostie, Janusz Rajski, Jerzy Tyszer
2010	—	`conf`	Adaptive Low Shift Power Test Pattern Generator for Logic BIST. Asian Test Symposium Xijiang Lin, Janusz Rajski
2010	A	`conf`	Clock control architecture and ATPG for reducing pattern count in SoC designs with multiple clock domains. ITC Tom Waayers, Richard Morren, Xijiang Lin, Mark Kassab
2010	A	`conf`	Detecting and diagnosing open defects. ITC Dat Tran, LeRoy Winemberg, Darrell Carder, Xijiang Lin, Joe LeBritton, Bruce Swanson
2010	A	`conf`	Low capture power at-speed test in EDT environment. ITC Elham K. Moghaddam, Janusz Rajski, Sudhakar M. Reddy, Xijiang Lin, Nilanjan Mukherjee, Mark Kassab
2010	J	`jnl`	On Reducing Scan Shift Activity at RTL. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Elif Alpaslan, Yu Huang, Xijiang Lin, Wu-Tung Cheng, Jennifer Dworak
2009	J	`jnl`	Low-Power Scan Operation in Test Compression Environment. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Dariusz Czysz, Mark Kassab, Xijiang Lin, Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer
2009	—	`conf`	Test Generation for Designs with On-Chip Clock Generators. Asian Test Symposium Xijiang Lin, Mark Kassab
2008	A	`conf`	Low Power Scan Shift and Capture in the EDT Environment. ITC Dariusz Czysz, Mark Kassab, Xijiang Lin, Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer
2008	Misc	`conf`	Reducing Scan Shift Power at RTL. VTS Elif Alpaslan, Yu Huang, Xijiang Lin, Wu-Tung Cheng, Jennifer Dworak
2008	J	`jnl`	Scan Shift Power Reduction by Freezing Power Sensitive Scan Cells. J. Electron. Test. Xijiang Lin, Yu Huang
2008	A	`conf`	Test Generation for Interconnect Opens. ITC Xijiang Lin, Janusz Rajski
2008	—	`conf`	Test Power Reduction by Blocking Scan Cell Outputs. ATS Xijiang Lin, Janusz Rajski
2007	J	`jnl`	Logic Design for On-Chip Test Clock Generation - Implementation Details and Impact on Delay Test Quality CoRR Matthias Beck, Olivier Barondeau, Martin Kaibel, Frank Poehl, Xijiang Lin, Ron Press
2007	Misc	`conf`	Low Shift and Capture Power Scan Tests. VLSI Design Santiago Remersaro, Xijiang Lin, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski
2007	—	`conf`	Programmable Logic BIST for At-speed Test. ATS Yu Huang, Xijiang Lin
2007	J	`jnl`	Scan-Based Tests with Low Switching Activity. IEEE Des. Test Comput. Santiago Remersaro, Xijiang Lin, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski
2007	—	`conf`	Test Generation for Timing-Critical Transition Faults. ATS Xijiang Lin, Mark Kassab, Janusz Rajski
2006	A	`conf`	Preferred Fill: A Scalable Method to Reduce Capture Power for Scan Based Designs. ITC Santiago Remersaro, Xijiang Lin, Zhuo Zhang, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski
2006	Misc	`conf`	Scan Tests with Multiple Fault Activation Cycles for Delay Faults. VTS Zhuo Zhang, Sudhakar M. Reddy, Irith Pomeranz, Xijiang Lin, Janusz Rajski
2006	Misc	`conf`	The Impacts of Untestable Defects on Transition Fault Testing. VTS Xijiang Lin, Janusz Rajski
2006	—	`conf`	Timing-Aware ATPG for High Quality At-speed Testing of Small Delay Defects. ATS Xijiang Lin, Kun-Han Tsai, Chen Wang, Mark Kassab, Janusz Rajski, Takeo Kobayashi, Randy Klingenberg, Yasuo Sato, Shuji Hamada, Takashi Aikyo
2005	A	`conf`	Logic Design for On-Chip Test Clock Generation - Implementation Details and Impact on Delay Test Quality. DATE Matthias Beck, Olivier Barondeau, Martin Kaibel, Frank Poehl, Xijiang Lin, Ron Press
2005	Misc	`conf`	Measures to Improve Delay Fault Testing on Low-Cost Testers - A Case Study. VTS Matthias Beck, Olivier Barondeau, Frank Poehl, Xijiang Lin, Ron Press
2005	—	`conf`	Propagation delay fault: a new fault model to test delay faults. ASP-DAC Xijiang Lin, Janusz Rajski
2003	J	`jnl`	High-Frequency, At-Speed Scan Testing. IEEE Des. Test Comput. Xijiang Lin, Ron Press, Janusz Rajski, Paul Reuter, Thomas Rinderknecht, Bruce Swanson, Nagesh Tamarapalli
2003	A*	`conf`	Test generation for designs with multiple clocks. DAC Xijiang Lin, Rob Thompson
2002	A	`conf`	Conflict driven techniques for improving deterministic test pattern generation. ICCAD Chen Wang, Sudhakar M. Reddy, Irith Pomeranz, Xijiang Lin, Janusz Rajski
2002	Misc	`conf`	Novel Techniques for Achieving High At-Speed Transition Fault Test Coverage for Motorola's Microprocessors Based on PowerPC(tm) Instruction Set Architecture. VTS Nandu Tendolkar, Rajesh Raina, Rick Woltenberg, Xijiang Lin, Bruce Swanson, Greg Aldrich
2001	—	`conf`	Experimental Results of Forward-Looking Reverse Order Fault Simulation on Industrial Circuits with Scan. Asian Test Symposium Irith Pomeranz, Sudhakar M. Reddy, Xijiang Lin
2001	A	`conf`	On static test compaction and test pattern ordering for scan designs. ITC Xijiang Lin, Janusz Rajski, Irith Pomeranz, Sudhakar M. Reddy
2000	Misc	`conf`	SIFAR: Static Test Compaction for Synchronous Sequential Circuits Based on Single Fault Restoration. VTS Xijiang Lin, Wu-Tung Cheng, Irith Pomeranz, Sudhakar M. Reddy
1999	A	`conf`	Full Scan Fault Coverage With Partial Scan. DATE Xijiang Lin, Irith Pomeranz, Sudhakar M. Reddy
1999	Misc	`conf`	Procedures for Identifying Undetectable and Redundant Faults In Synchronous Sequential Circuits. VTS Sudhakar M. Reddy, Irith Pomeranz, Nadir Z. Basturkmen, Xijiang Lin
1999	A	`conf`	Techniques for improving the efficiency of sequential circuit test generation. ICCAD Xijiang Lin, Irith Pomeranz, Sudhakar M. Reddy
1998	Misc	`conf`	MIX: A Test Generation System for Synchronous Sequential Circuits. VLSI Design Xijiang Lin, Irith Pomeranz, Sudhakar M. Reddy
1998	Misc	`conf`	On Removing Redundant Faults in Synchronous Sequential Circuits. VTS Xijiang Lin, Irith Pomeranz, Sudhakar M. Reddy
1998	C	`conf`	On finding undetectable and redundant faults in synchronous sequential circuits. ICCD Xijiang Lin, Irith Pomeranz, Sudhakar M. Reddy