Xicheng Jiang - RankMe

30 papers Journal 13Unranked 17

Year	Rank	Type	Title / Venue / Authors
2016	J	`jnl`	A 2.7 mW/Channel 48-1000 MHz Direct Sampling Full-Band Cable Receiver. IEEE J. Solid State Circuits Jiangfeng Wu, Giuseppe Cusmai, Acer Wei-Te Chou, Tao Wang, Bo Shen, Vijayaramalingam Periasamy, Ming-Hung Hsieh, Chun-Ying Chen, Lin He, Loke Kun Tan, Aravind Padyana, Vincent Cheng-Hsun Yang, Gregory Unruh, Jackie Koon Lun Wong, Bryan Juo-Jung Hung, Massimo Brandolini, Maco Sha-Ting Lin, Xi Chen, Yen Ding, Yen-Jen Ko, Young J. Shin, Ada Hing T. Hung, Binning Chen, Cynthia Dang, Deepak Lakshminarasimhan, Iris Hong Liu, Jerry Lin, Kowen Lai, Larry Wassermann, Ayaskant Shrivastava, Chi-Ming Hsiao, Chun-Sheng Huang, Jianlong Chen, Lakshminarasimhan Krishnan, Ning-Yi Wang, Pin-En Su, Tianwei Li, Wei-Ta Shih, Yau-Cheng Yang, Peter Cangiane, Randall Perlow, William Ngai, Hanson Hung-Sen Huang, James Y. C. Chang, Xicheng Jiang, Ardie G. Venes, Ramon Ray Gomez
2016	J	`jnl`	An 8-Bit Compressive Sensing ADC With 4-GS/s Equivalent Speed Utilizing Self-Timed Pipeline SAR-Binary-Search. IEEE Trans. Circuits Syst. II Express Briefs Boyu Hu, Fengbo Ren, Zuow-Zun Chen, Xicheng Jiang, Mau-Chung Frank Chang
2016	—	`conf`	EE1: Class of 2025 - Where will be the best jobs? ISSCC Xicheng Jiang, Axel Thomsen, Piero Malcovati, M.-C. Frank Chang
2016	—	`conf`	F2: Data-converter calibration and dynamic-matching techniques. ISSCC Kostas Doris, Alyosha C. Molnar, Xicheng Jiang, Seung-Tak Ryu
2015	—	`conf`	A 2.7mW/Channel 48-to-1000MHz Direct Sampling Full-Band Cable Receiver. VLSIC Jiangfeng Wu, Giuseppe Cusmai, Acer Wei-Te Chou, Tao Wang, Bo Shen, Vijayaramalingam Periasamy, Ming-Hung Hsieh, Chun-Ying Chen, Lin He, Loke Tan, Aravind Padyana, Cheng-Hsun Yang, Gregory Unruh, Jackie Koon Lun Wong, Juo-Jung Hung, Massimo Brandolini, Sha-Ting Lin, Xi Chen, Yen Ding, Yen-Jen Ko, Young Shin, Ada Hing T. Hung, Binning Chen, Cynthia Dang, Deepak Lakshminarasimhan, Iris Hong Liu, Jerry Lin, Kowen Lai, Larry Wassermann, Ayaskant Shrivastava, Chi-Ming Hsiao, Chun-Sheng Huang, Jianlong Chen, Lakshminarasimhan Krishnan, Ning-Yi Wang, Pin-En Su, Tianwei Li, Wei-Ta Shih, Yau-Cheng Yang, Peter Cangiane, Randall Perlow, William Ngai, Hung Sen Huang, James Y. C. Chang, Xicheng Jiang, Ardie G. Venes, Ramon Gomez
2015	J	`jnl`	A Multibit Delta-Sigma Modulator With Double Noise-Shaped Segmentation. IEEE Trans. Circuits Syst. II Express Briefs Lin He, Guanglong Zhu, Fang Long, Yuncheng Zhang, Li Wang, Fujiang Lin, Libin Yao, Xicheng Jiang
2015	J	`jnl`	A Speed-Enhancing Dual-Trial Instantaneous Switching Architecture for SAR ADCs. IEEE Trans. Circuits Syst. II Express Briefs Lin He, Jiaqi Yang, Duona Luo, Lele Jin, Shuangshuang Zhang, Fujiang Lin, Libin Yao, Xicheng Jiang
2015	J	`jnl`	Analysis of Current Efficiency for CMOS Class-B LC Oscillators. IEEE Trans. Circuits Syst. I Regul. Pap. Zisong Wang, Shengxi Diao, Lin He, Xicheng Jiang, Fujiang Lin
2015	J	`jnl`	Self-Dithering Technique for High-Resolution SAR ADC Design. IEEE Trans. Circuits Syst. II Express Briefs Lin He, Lele Jin, Jiaqi Yang, Fujiang Lin, Libin Yao, Xicheng Jiang
2015	—	`conf`	Session 5 overview: Analog techniques: Analog subcommittee. ISSCC Xicheng Jiang, Ed van Tuijl
2014	—	`conf`	A 28 nm analog and audio mixed-signal front end for 4G/LTE Cellular System-on-Chip. ESSCIRC Xicheng Jiang, Xinyu Yu, Fang Lin, Felix Cheung, Mike Inerfield, Kevin Li, Abhishek Kamath, Harsh Mehta, Jingbo Duan, Jing Yang, Gautham Krishnamurthy, Sumant Ranganathan, Darwin Cheung, Naga Radha Krishna Damaraju, Jianlong Chen, Dongtian Lu, Vinod Jayakumar, Leon Wang, Dario Soltesz, Hongwei Kong, Min Zhang, David Chang
2014	J	`jnl`	A 40 nm Fully Integrated 82 mW Stereo Headphone Module for Mobile Applications. IEEE J. Solid State Circuits Khaled Abdelfattah, Sherif Galal, Iuri Mehr, Alex Jianzhong Chen, Chengyue Yu, Maurice Tjie, Ahmet Tekin, Xicheng Jiang, Todd Brooks
2014	—	`conf`	Configurable incremental sigma-delta ADC for DC measure and audio conversion. CICC Zhengyu Wang, Tay Hui Zheng, Dongtian Lu, Sasi Kumar Arunachalam, Xicheng Jiang
2014	J	`jnl`	Digital Noise-Coupling Technique for Delta-Sigma Modulators With Segmented Quantization. IEEE Trans. Circuits Syst. II Express Briefs Lin He, Yuncheng Zhang, Fang Long, Fengcheng Mei, Mingyuan Yu, Fujiang Lin, Libin Yao, Xicheng Jiang
2014	—	`conf`	Digitally-assisted analog and analog-assisted digital design techniques for a 28 nm mobile System-on-Chip. ESSCIRC Xicheng Jiang, Narayan Prasad Ramachandran, Dae Woon Kang, Chee Kiong Chen, Mark Rutherford, Yonghua Cong, David Chang
2014	—	`conf`	F1: Digitally assisted analog and analog-assisted digital in high-performance scaled CMOS process. ISSCC Xicheng Jiang, Piero Malcovati, Vladimir Stojanovic, Tetsuya Lizuka
2014	J	`jnl`	Integrated Class-D Audio Amplifier With 95% Efficiency and 105 dB SNR. IEEE J. Solid State Circuits Xicheng Jiang, Jungwoo Song, Darwin Cheung, Minsheng Wang, Sasi Kumar Arunachalam
2014	—	`conf`	Sub-session: Data converter techniques. CICC Jorge A. Grilo, Xicheng Jiang
2013	—	`conf`	A direct-battery hookup, fully integrated stereo headphone module with 82 mW output power and 110 dB PSRR. CICC Khaled Abdelfattah, Sherif Galal, Iuri Mehr, Alex Jianzhong Chen, Ahmet Tekin, Xicheng Jiang, Todd Brooks
2013	—	`conf`	Analog techniques I. CICC Don Thelen, Xicheng Jiang
2013	J	`jnl`	Integrated Pop-Click Noise Suppression, EMI Reduction, and Short-Circuit Detection for Class-D Audio Amplifiers. IEEE J. Solid State Circuits Xicheng Jiang, Jungwoo Song, Minsheng Wang, Jianlong Chen, Sasi Kumar Arunachalam
2012	—	`conf`	A 40 nm CMOS analog front end with enhanced audio for HSPA/EDGE multimedia applications. ESSCIRC Xicheng Jiang, Min-Gyu Kim, Felix Cheung, Fang Lin, Hui Zheng, Jianlong Chen, Alex Jianzhong Chen, Darwin Cheung, Khaled Abdelfattah, Seong-Ho Lee, Hanson Hung-Sen Huang, Kishore Kasichainula, Yonghua Cong, Jiangfeng Wu, Chang-Hyeon Lee, George Chih, Yun Tu, Todd Brooks, Edison Jiang, Hongwei Kong, Chaoyang Zhao, Mustafa Keskin
2012	J	`jnl`	A Low-Power, High-Fidelity Stereo Audio Codec in 0.13 µm CMOS. IEEE J. Solid State Circuits Xicheng Jiang, Jungwoo Song, Jianlong Chen, Vinay Chandrasekhar, Sherif Galal, Felix Y. L. Cheung, Darwin Cheung, Todd Brooks
2012	—	`conf`	Analog Techniques. CICC Don Thelen, Xicheng Jiang
2012	—	`conf`	Circuit techniques to overcome Class-D audio amplifier limitations in mobile devices. VLSIC Xicheng Jiang, Jungwoo Song, Minsheng Wang, Jianlong Chen, Sasi Kumar Arunachalam, Todd L. Brooks
2010	—	`conf`	A 10mW stereo audio CODEC in 0.13µm CMOS. ISSCC Xicheng Jiang, Jungwoo Song, Todd Brooks, Jianlong Chen, Vinay Chandrasekhar, Felix Cheung, Sherif Galal, Darwin Cheung, Gil-Cho Ahn, Madhulatha Bonu
2010	J	`jnl`	A 120 dB Dynamic Range 400 mW Class-D Speaker Driver With Fourth-Order PWM Modulator. IEEE J. Solid State Circuits Minsheng Wang, Xicheng Jiang, Jungwoo Song, Todd Brooks
2010	—	`conf`	A 32-channel front-end for wireless HID using inverse-STF pre-filtering technique. CICC Sherif Galal, Jurgen van Engelen, Jared Welz, Henrik Jensen, Khaled Abdelfattah, Felix Cheung, Sasi Kumar Arunachalam, Xicheng Jiang, Todd Brooks
2009	—	`conf`	A 120dB dynamic range 400mW class-D speaker driver with 4 CICC Minsheng Wang, Xicheng Jiang, Jungwoo Song, Todd Brooks
2005	J	`jnl`	A 1-GHz signal bandwidth 6-bit CMOS ADC with power-efficient averaging. IEEE J. Solid State Circuits Xicheng Jiang, Mau-Chung Frank Chang