Xiaoyong Xue - RankMe

73 papers A 1B 2C 10Misc 1Journal 32Unranked 27

Year	Rank	Type	Title / Venue / Authors
2025	—	`conf`	A PMOS-Based Deep Cryogenic CMOS Temperature Sensor Achieving a Range from 10K to 410K with a Relative Inaccuracy of 0.5% (3σ). CICC Xingyu Qi, Yingzhe Sha, Xufeng Kou, Xiaoyong Xue, Peng Wang, Zhangcheng Huang, Qi Liu, Ming Liu
2025	J	`jnl`	Booth-Assisted Mixed-Precision Reconfigurable Digital Computing-in-Memory Engine With Ternary-Input 1T2R ReRAM for Edge AI. IEEE Trans. Circuits Syst. I Regul. Pap. Ruijun Lin, Lixing Li, Shuyang Lv, Jingwen Jiang, Liang Meng, Zhiwang Guo, Jianguo Yang, Jun Han, Alex Zhou, Xiaoyong Xue, Xiaoyang Zeng
2025	J	`jnl`	EF-CIM: An Endurance Friendly CIM Accelerator Using Embedded NVM With Bit-Aware Wear Leveling for Efficient Light-Weight On-Chip Training in Edge Devices. IEEE Trans. Circuits Syst. I Regul. Pap. Zhiwang Guo, Jingwen Jiang, Deyang Chen, Jinbei Fang, Jianguo Yang, Jun Han, Xiaoyong Xue, Xiaoyang Zeng
2025	J	`jnl`	Enhancing All-to-All RRAM Ising Machines With Randomized Granular Update Strategies for Solving Combinatorial Optimization Problems. IEEE Trans. Circuits Syst. I Regul. Pap. Yixuan Liu, Qiqiao Wu, Honghu Yang, Chengshuo Yu, Keji Zhou, Yu Jiang, Haijun Jiang, Hailan Yi, Xiaoyong Xue, Jianguo Yang, Xiaoyang Zeng
2025	J	`jnl`	Garbage collection optimization with data separation for large data storage in deep learning applications. Microelectron. J. Qiang Zhou, Sirui Peng, Taoran Shen, Jie Yin, Tieli Sun, Xiaoyong Xue
2025	J	`jnl`	Light-CIM: A Lightweight ADC/DAC-Fewer RRAM CIM DNN Accelerator With Fully Analog Tiles and Nonideality-Aware Algorithm for Consumer Electronics. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chenyang Zhao, Jinbei Fang, Jingwen Jiang, Xiaoyong Xue, Xiaoyang Zeng
2025	A	`conf`	LsCMM-H: A TCO-Optimized Hybrid CXL Memory Expansion Architecture with Log Structure. ICCAD Xingyu Chen, XiangRui Zhang, Sirui Peng, Zhiwang Guo, Haidong Tian, Xiankui Xiong, Xiaoyong Xue, Xiaoyang Zeng
2025	J	`jnl`	Runtime Backdoor Detection for Federated Learning via Representational Dissimilarity Analysis. CoRR Xiyue Zhang, Xiaoyong Xue, Xiaoning Du, Xiaofei Xie, Yang Liu, Meng Sun
2025	J	`jnl`	Runtime Backdoor Detection for Federated Learning via Representational Dissimilarity Analysis. IEEE Trans. Dependable Secur. Comput. Xiyue Zhang, Xiaoyong Xue, Xiaoning Du, Xiaofei Xie, Yang Liu, Meng Sun
2024	J	`jnl`	A 1024-Spin Scalable Ising Machine With Capacitive Coupling and Progressive Annealing Method for Combination Optimization Problems. IEEE Trans. Circuits Syst. II Express Briefs Yixuan Liu, Zhongze Han, Qiqiao Wu, Honghu Yang, Yue Cao, Yongkang Han, Haijun Jiang, Xiaoyong Xue, Jianguo Yang, Xiaoyang Zeng
2024	J	`jnl`	A 28-nm 36 Kb SRAM CIM Engine With 0.173 μm IEEE J. Solid State Circuits Chenyang Zhao, Jinbei Fang, Xiaoli Huang, Deyang Chen, Zhiwang Guo, Jingwen Jiang, Jiawei Wang, Jianguo Yang, Jun Han, Peng Zhou, Xiaoyong Xue, Xiaoyang Zeng
2024	B	`conf`	A Heuristic and Greedy Weight Remapping Scheme with Hardware Optimization for Irregular Sparse Neural Networks Implemented on CIM Accelerator in Edge AI Applications. ASPDAC Lizhou Wu, Chenyang Zhao, Jingbo Wang, Xueru Yu, Shoumian Chen, Chen Li, Jun Han, Xiaoyong Xue, Xiaoyang Zeng
2024	B	`conf`	Optimal Solution Guided Branching Strategy for Neural Network Branch and Bound Verification. ICECCS Xiaoyong Xue, Meng Sun
2024	J	`jnl`	SET Tolerable SRAM Hardened by DMR Circuit With Feedback-Split-Gate Voter and High-Speed Hierarchical Structure. IEEE Trans. Circuits Syst. II Express Briefs Yuanyuan Han, Xu Cheng, Xiaoyong Xue, Jun Han, Jiawei Xu, Xiaoyang Zeng
2023	J	`jnl`	A 1T2R1C ReRAM CIM Accelerator With Energy-Efficient Voltage Division and Capacitive Coupling for CNN Acceleration in AI Edge Applications. IEEE Trans. Circuits Syst. II Express Briefs Deyang Chen, Zhiwang Guo, Jinbei Fang, Chenyang Zhao, Jingwen Jiang, Keji Zhou, Haidong Tian, Xiankui Xiong, Xiaoyong Xue, Xiaoyang Zeng
2023	—	`conf`	A 9Mb HZO-Based Embedded FeRAM with 10 ISSCC Jianguo Yang, Qing Luo, Xiaoyong Xue, Haijun Jiang, Qiqiao Wu, Zhongze Han, Yue Cao, Yongkang Han, Chunmeng Dou, Hangbing Lv, Qi Liu, Ming Liu
2023	J	`jnl`	ARBiS: A Hardware-Efficient SRAM CIM CNN Accelerator With Cyclic-Shift Weight Duplication and Parasitic-Capacitance Charge Sharing for AI Edge Application. IEEE Trans. Circuits Syst. I Regul. Pap. Chenyang Zhao, Jinbei Fang, Jingwen Jiang, Xiaoyong Xue, Xiaoyang Zeng
2023	J	`jnl`	An Emerging NVM CIM Accelerator With Shared-Path Transpose Read and Bit-Interleaving Weight Storage for Efficient On-Chip Training in Edge Devices. IEEE Trans. Circuits Syst. II Express Briefs Zhiwang Guo, Deyang Chen, Chenyang Zhao, Jinbei Fang, Jingwen Jiang, Yixuan Liu, Haidong Tian, Xiankui Xiong, Keji Zhou, Xiaoyong Xue, Qi Liu, Xiaoyang Zeng
2023	J	`jnl`	Area-Efficient 1T-2D-2MTJ SOT-MRAM Cell for High Read Performance. IEEE Trans. Circuits Syst. II Express Briefs Xunming Zhang, Long Liu, Di Wang, Ruijun Lin, Heyong Yang, Xiaoxin Xu, Jianguo Yang, Guozhong Xing, Xiaoyong Xue, Xiaoyang Zeng
2023	C	`conf`	Branch and Bound for Sigmoid-Like Neural Network Verification. ICFEM Xiaoyong Xue, Meng Sun
2023	J	`jnl`	HashC: Making deep learning coverage testing finer and faster. J. Syst. Archit. Weidi Sun, Xiaoyong Xue, Yuteng Lu, Jia Zhao, Meng Sun
2023	—	`conf`	MedTiny: Enhanced Mediator Modeling Language for Scalable Parallel Algorithms. QRS Companion Xiangyu Li, Yihao Zhang, Xiaokun Luan, Xiaoyong Xue, Meng Sun
2023	C	`conf`	NBSSN: A Neuromorphic Binary Single-Spike Neural Network for Efficient Edge Intelligence. ISCAS Ziyang Shen, Fengshi Tian, Jingwen Jiang, Chaoming Fang, Xiaoyong Xue, Jie Yang, Mohamad Sawan
2023	J	`jnl`	Tempo-CIM: A RRAM Compute-in-Memory Neuromorphic Accelerator With Area-Efficient LIF Neuron and Split-Train-Merged-Inference Algorithm for Edge AI Applications. IEEE J. Emerg. Sel. Topics Circuits Syst. Jingwen Jiang, Keji Zhou, Jinhao Liang, Fengshi Tian, Chenyang Zhao, Jianguo Yang, Xiaoyong Xue, Xiaoyang Zeng
2023	—	`conf`	kProp: Multi-neuron Relaxation Method for Neural Network Robustness Verification. FSEN Xiaoyong Xue, Xiyue Zhang, Meng Sun
2022	J	`jnl`	A 28 nm 512 Kb adjacent 2T2R RRAM PUF with interleaved cell mirroring and self-adaptive splitting for high density and low BER cryptographic key in IoT devices. Microelectron. J. Jianguo Yang, Ruijun Lin, Keji Zhou, Yuejun Zhang, Xiaoyong Xue, Hangbing Lv
2022	J	`jnl`	A 28 nm 81 Kb 59-95.3 TOPS/W 4T2R ReRAM Computing-in-Memory Accelerator With Voltage-to-Time-to-Digital Based Output. IEEE J. Emerg. Sel. Topics Circuits Syst. Keji Zhou, Xinru Jia, Chenyang Zhao, Xumeng Zhang, Guangjian Wu, Chen Mu, Haozhe Zhu, Yanting Ding, Chixiao Chen, Xiaoyong Xue, Xiaoyang Zeng, Qi Liu
2022	J	`jnl`	A 2D2R ReRAM CIM accelerator for multilayer perceptron in visual classification applications. Microelectron. J. Keji Zhou, Ruijun Lin, Zhiwang Guo, Yixuan Liu, Jingwen Jiang, Chenyang Zhao, Jinbei Fang, Xiaoxin Xu, Xiaoyong Xue, Xiaoyang Zeng
2022	Misc	`conf`	HashC: Making DNNs' Coverage Testing Finer and Faster. SETTA Weidi Sun, Xiaoyong Xue, Yuteng Lu, Meng Sun
2022	C	`conf`	NIMBLE: A Neuromorphic Learning Scheme and Memristor Based Computing-in-Memory Engine for EMG Based Hand Gesture Recognition. ISCAS Fengshi Tian, Jingwen Jiang, Jinhao Liang, Zhiyuan Zhang, Jiahe Shi, Chaoming Fang, Hui Wu, Xiaoyong Xue, Xiaoyang Zeng
2021	—	`conf`	24.2 A 14nm-FinFET 1Mb Embedded 1T1R RRAM with a 0.022µ m ISSCC Jianguo Yang, Xiaoyong Xue, Xiaoxin Xu, Qiao Wang, Haijun Jiang, Jie Yu, Danian Dong, Feng Zhang, Hangbing Lv, Ming Liu
2021	—	`conf`	Algorithm/Hardware Co-Design Configurable SAR ADC with Low Power for Computing-in-Memory in 28nm CMOS. ASICON Zhiwang Guo, Deyang Chen, Xiaoyong Xue
2021	J	`jnl`	An Energy Efficient Computing-in-Memory Accelerator With 1T2R Cell and Fully Analog Processing for Edge AI Applications. IEEE Trans. Circuits Syst. II Express Briefs Keji Zhou, Chenyang Zhao, Jinbei Fang, Jingwen Jiang, Deyang Chen, Yujie Huang, Ming-e Jing, Jun Han, Haidong Tian, Xiankui Xiong, Qi Liu, Xiaoyong Xue, Xiaoyang Zeng
2021	—	`conf`	Arbitrary Style Transfer via Learning to Paint in the Feature Domain. ASICON Yujie Huang, Yixuan Liu, Ming-e Jing, Mingyu Wang, Xiaoyong Xue, Xiaoyang Zeng, Yibo Fan
2021	—	`conf`	Combining Max Pooling and ReLU Activation Function in Stochastic Computing. ASICON Lixing Li, Deyang Chen, Xiaoyong Xue, Xiaoyang Zeng
2021	C	`conf`	Fast Style Transfer with High Shape Retention. ISCAS Yujie Huang, Yi Ling, Ming-e Jing, Xiaoyong Xue, Xiaoyang Zeng, Yibo Fan
2021	J	`jnl`	High-Density 3-D Stackable Crossbar 2D2R nvTCAM With Low-Power Intelligent Search for Fast Packet Forwarding in 5G Applications. IEEE J. Solid State Circuits Keji Zhou, Xiaoyong Xue, Jianguo Yang, Xiaoxin Xu, Hangbing Lv, Ming-e Jing, Jing Li, Xiaoyang Zeng, Ming Liu
2021	—	`conf`	Intra-array Non-Idealities Modeling and Algorithm Optimization for RRAM-based Computing-in-Memory Applications. ASICON Chenyang Zhao, Jinbei Fang, Jingwen Jiang, Zhiwang Guo, Xiaoyong Xue, Xiaoyang Zeng
2021	—	`conf`	Novel 15T SRAM Cell for Low Voltage High Reliability Application. ASICON Yongkang Han, Yulin Zhao, Qiao Hu, Xuanzhi Liu, Bo Peng, Haijun Jiang, Jianguo Yang, Xiaoyong Xue
2021	J	`jnl`	Orthogonal obfuscation based key management for multiple IP protection. Integr. Yuejun Zhang, Jiawei Wang, Pengjun Wang, Xiaoyong Xue, Xiaoyang Zeng
2020	—	`conf`	A 28nm 1.5Mb Embedded 1T2R RRAM with 14.8 Mb/mm VLSI Circuits Jianguo Yang, Xiaoyong Xue, Xiaoxin Xu, Hangbing Lv, Feng Zhang, Xiaoyang Zeng, Meng-Fan Chang, Ming Liu
2020	J	`jnl`	A Low Power 4T2C nvSRAM With Dynamic Current Compensation Operation Scheme. IEEE Trans. Very Large Scale Integr. Syst. Chao Liu, Jianguo Yang, Pengfei Jiang, Qiao Wang, Donglin Zhang, Tiancheng Gong, Qingting Ding, Yuling Zhao, Qing Luo, Xiaoyong Xue, Hangbing Lv, Ming Liu
2020	—	`conf`	A Parallel Change Detection Method for Spatiotemporally Multi-Temporal SAR Image Based On Enhance Learning and Wavelet. ISCID Jinxi Peng, Yuanqi Su, Xiaorong Xue, Yi Li, Bin Liu, Xiaoyong Xue, Aihua Wu
2020	C	`conf`	Directly Obtaining Matching Points without Keypoints for Image Stitching. ISCAS Yujie Huang, Ming-e Jing, Yibo Fan, Xiaoyong Xue, Xiaoyang Zeng
2019	J	`jnl`	A 0.75 V reference clamping sense amplifier for low-power high-density ReRAM with dynamic pre-charge technique. IEICE Electron. Express Jiahao Yin, Chunmeng Dou, Danian Dong, Jie Yu, Xiaoxin Xu, Qing Luo, Tiancheng Gong, Lu Tai, Peng Yuan, Xiaoyong Xue, Ming Liu, Hangbing Lv
2019	—	`conf`	A 28nm 512Kb adjacent 2T2R RRAM PUF with interleaved cell mirroring and self-adaptive splitting for extremely low bit error rate of cryptographic key. A-SSCC Xiaoyong Xue, Jianguo Yang, Yuejun Zhang, Mingyu Wang, Hangbing Lv, Xiaoyang Zeng, Ming Liu
2019	—	`conf`	A High Reliability 500 µW Resistance-to-Digital Interface Circuit for SnO2 Gas Sensor IoT Applications. ASICON Jianguo Yang, Xiaowen Li, Qingting Ding, Xiaoyong Xue, Xiaoxin Xu, Qing Luo, Hangbing Lv, Ming Liu
2019	—	`conf`	An Orthogonal Algorithm for Key Management in Hardware Obfuscation. AsianHOST Jiawei Wang, Yuejun Zhang, Pengjun Wang, Zhicun Luan, Xiaoyong Xue, Xiaoyang Zeng, Qiaoyan Yu
2019	—	`conf`	Nonvolatile Binary CNN Accelerator with Extremely Low Standby Power using RRAM for IoT Applications. ASICON Yujie Cai, Keji Zhou, Xiaoyong Xue, Mingyu Wang, Xiaoyang Zeng
2018	—	`conf`	A Physically Unclonable Function with BER < 0.35% for Secure Chip Authentication Using Write Speed Variation of RRAM. ESSDERC Jianguo Yang, Xing Li, Tao Wang, Xiaoyong Xue, Zhiliang Hong, Yuanyuan Wang, David Wei Zhang, Hongliang Lu
2018	C	`conf`	An Automatic Task Partition Method for Multi-core System. ISCAS Ming-e Jing, Yujie Huang, Yibo Fan, Xiaoyong Xue, Xiaoyang Zeng, Zhiyi Yu
2018	—	`conf`	Nonvolatile Crossbar 2D2R TCAM with Cell Size of 16.3 F A-SSCC Keji Zhou, Xiaoyong Xue, Jianguo Yang, Xiaoxin Xu, Hangbing Lv, Mingyu Wang, Ming-e Jing, Wenjun Liu, Xiaoyang Zeng, Steve S. Chung, Jing Li, Ming Liu
2017	—	`conf`	A 1.0-3.0GHz LTE transmitter with CIM enhancement. ASICON Yun Yin, Tong Li, Xiaoyong Xue
2017	C	`conf`	A small area and low power true random number generator using write speed variation of oxidebased RRAM for IoT security application. ISCAS Jianguo Yang, Yinyin Lin, Yarong Fu, Xiaoyong Xue, B. A. Chen
2017	—	`conf`	Distributed graph database as base of smart world things. SmartWorld/SCALCOM/UIC/ATC/CBDCom/IOP/SCI Kosei Ueta, Yukikazu Nakamoto, Xiaoyong Xue, Sena Murakami
2017	J	`jnl`	Dynamic Data-Dependent Reference to Improve Sense Margin and Speed of Magnetoresistive Random Access Memory. IEEE Trans. Circuits Syst. II Express Briefs Xiaoyong Xue, Yarong Fu, Yanqing Zhao, Juan Xu, Jianguo Yang, Yufeng Xie, Yinyin Lin, Ryan Huang, Qingtian Zou, Jingang Wu
2017	—	`conf`	ReRAM write circuit with dynamic uniform and small overshoot compliance current under PVT variations. ASICON Yun Yin, Junlin Gou, Junyi Wang, Yarong Fu, Xiaoyong Xue, Yinyin Lin
2016	—	`conf`	A Distributed Graph Database for the Data Management of IoT Systems. iThings/GreenCom/CPSCom/SmartData Kosei Ueta, Xiaoyong Xue, Yukikazu Nakamoto, Sena Murakami
2016	J	`jnl`	A Logic Resistive Memory Chip for Embedded Key Storage With Physical Security. IEEE Trans. Circuits Syst. II Express Briefs Yufeng Xie, Xiaoyong Xue, Jianguo Yang, Yinyin Lin, Qingtian Zou, Ryan Huang, Jingang Wu
2016	C	`conf`	A compact pico-second in-situ sensor using programmable ring oscillators for advanced on chip variation characterization in 28nm HKMG. ISCAS Yinyin Lin, Xinyi Hu, Jianguo Yang, Xiaoyong Xue
2016	J	`jnl`	A self-adaptive write driver with fast termination of step-up pulse for ReRAM. IEICE Electron. Express Jianguo Yang, Xiaoyong Xue, Juan Xu, Fan Ye, Yinyin Lin, Ryan Huang, Qingtian Zou, Jingang Wu
2016	J	`jnl`	Low-Power Variation-Tolerant Nonvolatile Lookup Table Design. IEEE Trans. Very Large Scale Integr. Syst. Xiaoyong Xue, Jianguo Yang, Yinyin Lin, Ryan Huang, Qingtian Zou, Jingang Wu
2016	C	`conf`	Novel 3D horizontal RRAM architecture with isolation cell structure for sneak current depression. ISCAS Yanqing Zhao, Juan Xu, Jianguo Yang, Xiaoyong Xue, Yinyin Lin, Jaehwang Sim
2015	C	`conf`	3D vertical RRAM architecture and operation algorithms with effective IR-drop suppressing and anti-disturbance. ISCAS Yinyin Lin, Rui Yuan, Xiaoyong Xue, B. A. Chen
2015	—	`conf`	A low cost and high reliability true random number generator based on resistive random access memory. ASICON Jianguo Yang, Juan Xu, Bo Wang, Xiaoyong Xue, Ryan Huang, Qingtian Zou, Jingang Wu, Yinyin Lin
2015	—	`conf`	Impacts of external magnetic field and high temperature disturbance on MRAM reliability based on FPGA test platform. ASICON Kai Yang, Yanqing Zhao, Jianguo Yang, Xiaoyong Xue, Yinyin Lin, Jun-Soo Bae
2013	J	`jnl`	A 0.13 µm 8 Mb Logic-Based Cu IEEE J. Solid State Circuits Xiaoyong Xue, Wenxiang Jian, Jianguo Yang, Fanjie Xiao, Gang Chen, Shuliu Xu, Yufeng Xie, Yinyin Lin, Ryan Huang, Qingtian Zou, Jingang Wu
2013	—	`conf`	A 2Mb ReRAM with two bits error correction codes circuit for high reliability application. ASICON Jianguo Yang, Ying Meng, Xiaoyong Xue, Ryan Huang, Q. T. Zhou, J. G. Wu, Yinyin Lin
2012	J	`jnl`	64Kb logic RRAM chip resisting physical and side-channel attacks for encryption keys storage. IEICE Electron. Express Yufeng Xie, Wenxiang Jian, Xiaoyong Xue, Gang Jin, Yinyin Lin
2012	—	`conf`	A 0.13µm 8Mb logic based CuxSiyO resistive memory with self-adaptive yield enhancement and operation power reduction. VLSIC Xiaoyong Xue, W. X. Jian, Jianguo Yang, F. J. Xiao, G. Chen, X. L. Xu, Y. F. Xie, Yinyin Lin, R. Huang, Q. T. Zhou, J. G. Wu
2011	J	`jnl`	Novel 2T programmable element to improve density and performance of FPGA. IEICE Electron. Express Xiaoyong Xue, Yufeng Xie, Yinyin Lin
2011	—	`conf`	Novel RRAM programming technology for instant-on and high-security FPGAs. ASICON Xiaoyong Xue, Wenxiang Jian, Yufeng Xie, Qing Dong, Rui Yuan, Yinyin Lin
2010	J	`jnl`	A 3D RRAM Using a Stackable Multi-Layer 1TXR Cell. IEICE Trans. Electron. Ji Zhang, Yiqing Ding, Xiaoyong Xue, Gang Jin, Yuxin Wu, Yufeng Xie, Yinyin Lin