Xiaowei Li - RankMe

541 papers A* 49A 71B 17C 26Misc 19Journal 214Unranked 144

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	Chipletizer 2.0: Toward Cost-Effective Chiplet Design via Reuse-Aware Decomposition. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Fuping Li, Ding Yuan, Yujie Wang, Juelei Zhou, Xihao Liang, Yinhe Han, Huawei Li, Xiaowei Li, Ying Wang
2026	J	`jnl`	Chiplever: A Hardware-Software Co-Design Framework Toward Extension of Chiplet System for Fully Homomorphic Encryption. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yibo Du, Ying Wang, Mengdi Wang, Xiaowei Li, Yinhe Han
2026	—	`conf`	FlexMem: High-Parallel Near-Memory Architecture for Flexible Dataflow in Fully Homomorphic Encryption. ASP-DAC Shangyi Shi, Husheng Han, Jianan Mu, Xinyao Zheng, Ling Liang, Hang Lu, Zidong Du, Xiaowei Li, Xing Hu
2026	J	`jnl`	From Buffers to Registers: Unlocking Fine-Grained FlashAttention with Hybrid-Bonded 3D NPU Co-Design. CoRR Jinxin Yu, Yudong Pan, Mengdi Wang, Huawei Li, Yinhe Han, Xiaowei Li, Ying Wang
2026	J	`jnl`	LayerTEE: Decoupled Memory Protection for Scalable Multilayer Communication on RISC-V. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Shangjie Pan, Yinghao Yang, Xuanyao Peng, Xiquan Zhao, Dong Du, Hang Lu, Yubin Xia, Xiaowei Li
2025	J	`jnl`	A data-centric chip design agent framework for Verilog code generation. ACM Trans. Design Autom. Electr. Syst. Kaiyan Chang, Wenlong Zhu, Kun Wang, Xinyang He, Nan Yang, Zhirong Chen, Dantong Jin, Cangyuan Li, Yunhao Zhou, Hao Yan, Zhuoliang Zhao, Yuan Cheng, Mengdi Wang, Shengwen Liang, Yinhe Han, Xiaowei Li, Huawei Li, Ying Wang
2025	J	`jnl`	A fast test compaction method using dedicated Pure MaxSAT solver embedded in DFT flow. Integr. Zhiteng Chao, Xindi Zhang, JunYing Huang, Zizhen Liu, Yixuan Zhao, Jing Ye, Shaowei Cai, Huawei Li, Xiaowei Li
2025	—	`conf`	APTO: Accelerating Serialization-Based Point Cloud Transformers with Position-Aware Pruning. ASP-DAC Qichu Sun, Rui Meng, Haishuang Fan, Fangqiang Ding, Linxi Lu, Jingya Wu, Xiaowei Li, Guihai Yan
2025	J	`jnl`	APoX-M: Accelerate deep point cloud analysis via adaptive graph construction. Integr. Lei Dai, Shengwen Liang, Ying Wang, Huawei Li, Xiaowei Li
2025	C	`conf`	AceHomo: Accelerating Privacy Preserving Inference Through Dynamic Level Adjustment. ICCD Hongyan Li, Jinkai Zhang, Hang Lu, Xiaowei Li
2025	A*	`conf`	Ares: High Performance Near-Storage Accelerator for FHE-based Private Set Intersection. DAC Haoxuan Wang, Yinghao Yang, Jinkai Zhang, Hang Lu, Xiaowei Li
2025	A*	`conf`	Athena: Accelerating Quantized Convolutional Neural Networks under Fully Homomorphic Encryption. MICRO Yinghao Yang, Xicheng Xu, Liang Chang, Hang Lu, Xiaowei Li
2025	A*	`conf`	BaWA: Automatic Optimizing Pruning Metric for Large Language Models with Balanced Weight and Activation. ICML Lian Liu, Xiandong Zhao, Guanchen Li, Dong Li, Mengdi Wang, Yinhe Han, Xiaowei Li, Ying Wang
2025	—	`conf`	COMET: Towards Practical W4A4KV4 LLMs Serving. ASPLOS (2) Lian Liu, Long Cheng, Haimeng Ren, Zhaohui Xu, Yudong Pan, Mengdi Wang, Xiaowei Li, Yinhe Han, Ying Wang
2025	J	`jnl`	Co-ViSu: Accelerating Video Super-Resolution With Codec Information Reuse. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Haishuang Fan, Qichu Sun, Jingya Wu, Wenyan Lu, Xiaowei Li, Guihai Yan
2025	J	`jnl`	DNA: A General Dynamic Neural Network Accelerator. IEEE Trans. Computers Lian Liu, Jinxin Yu, Mengdi Wang, Xiaowei Li, Yinhe Han, Ying Wang
2025	A	`conf`	DRIM-ANN: An Approximate Nearest Neighbor Search Engine based on Commercial DRAM-PIMs. SC Mingkai Chen, Tianhua Han, Cheng Liu, Shengwen Liang, Kuai Yu, Lei Dai, Ziming Yuan, Ying Wang, Lei Zhang, Huawei Li, Xiaowei Li
2025	—	`conf`	Dep-TEE: Decoupled Memory Protection for Secure and Scalable Inter-enclave Communication on RISC-V. ASP-DAC Shangjie Pan, Xuanyao Peng, Zeyuan Man, Xiquan Zhao, Dongrong Zhang, Bicheng Yang, Dong Du, Hang Lu, Yubin Xia, Xiaowei Li
2025	A*	`conf`	EPICS: Efficient Parallel Pattern Fault Simulation for Sequential Circuits via Strongly Connected Components. DAC Mingjun Wang, Hui Wang, Jianan Mu, Xinyu Zhang, Bin Sun, Yihan Wen, Zizhen Liu, Feng Gu, Jun Gao, Shengwen Liang, Jing Ye, Xiaowei Li, Huawei Li
2025	A	`conf`	ERASER: Efficient RTL FAult Simulation Framework with Trimmed Execution Redundancy. DATE Jiaping Tang, Jianan Mu, Silin Liu, Zizhen Liu, Feng Gu, Xinyu Zhang, Leyan Wang, Shengwen Liang, Jing Ye, Huawei Li, Xiaowei Li
2025	J	`jnl`	ERASER: Efficient RTL FAult Simulation Framework with Trimmed Execution Redundancy. CoRR Jiaping Tang, Jianan Mu, Silin Liu, Zizhen Liu, Feng Gu, Xinyu Zhang, Leyan Wang, Shenwen Liang, Jing Ye, Huawei Li, Xiaowei Li
2025	—	`conf`	ETPG: Efficient Transition Fault Simulation via Dual-Strategy Pattern Parallelism and Gate Restructuring. ASP-DAC Mingjun Wang, Hui Wang, Zizhen Liu, Feng Gu, Jianan Mu, Jiaping Tang, Jun Gao, Huawei Li, Jing Ye, Xiaowei Li
2025	J	`jnl`	FUS: FPGA-based Universal Sketch with homogeneous and heterogeneous memory architectures. CCF Trans. High Perform. Comput. Yunkun Liao, Jingya Wu, Wenyan Lu, Huawei Li, Xiaowei Li, Guihai Yan
2025	A*	`conf`	FicGCN: Unveiling the Homomorphic Encryption Efficiency from Irregular Graph Convolutional Networks. ICML Zhaoxuan Kan, Husheng Han, Shangyi Shi, Tenghui Hua, Hang Lu, Xiaowei Li, Jianan Mu, Xing Hu
2025	J	`jnl`	FicGCN: Unveiling the Homomorphic Encryption Efficiency from Irregular Graph Convolutional Networks. CoRR Zhaoxuan Kan, Husheng Han, Shangyi Shi, Tenghui Hua, Hang Lu, Xiaowei Li, Jianan Mu, Xing Hu
2025	J	`jnl`	FlexMem: High-Parallel Near-Memory Architecture for Flexible Dataflow in Fully Homomorphic Encryption. CoRR Shangyi Shi, Husheng Han, Jianan Mu, Xinyao Zheng, Ling Liang, Hang Lu, Zidong Du, Xiaowei Li, Xing Hu, Qi Guo
2025	A*	`conf`	FrontOrder: Frontier-Guided Graph Reordering. ICDE Xinmiao Zhang, Cheng Liu, Shengwen Liang, Chenwei Xiong, Yu Zhang, Lei Zhang, Huawei Li, Xiaowei Li
2025	B	`conf`	Frontier-guided Graph Reordering. PPoPP Xinmiao Zhang, Cheng Liu, Shengwen Liang, Chenwei Xiong, Yu Zhang, Lei Zhang, Huawei Li, Xiaowei Li
2025	J	`jnl`	Functional Testing and Repair for ReRAM-Based Deep-Learning Accelerators. IEEE Des. Test Wen Li, Ying Wang, Huawei Li, Xiaowei Li, Kaiwei Zou
2025	J	`jnl`	GRACE: An End-to-End Graph Processing Accelerator on FPGA With Graph Reordering Engine. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Haishuang Fan, Rui Meng, Qichu Sun, Jingya Wu, Wenyan Lu, Xiaowei Li, Guihai Yan
2025	C	`conf`	Hermes: Accelerating Packet Processing in DPU with Neural Network. ICCD Rui Meng, Xinyu Chen, Hanyue Lin, Jingya Wu, Wenyan Lu, Xiaowei Li, Guihai Yan
2025	Misc	`conf`	HighTPI: A Hierarchical Graph Based Intelligent Method for Test Point Insertion. VTS Zhiteng Chao, Bin Sun, Hongqin Lyu, Ge Yu, Minjun Wang, Wenxing Li, Zizhen Liu, Jianan Mu, Shengwen Liang, Jing Ye, Xiaowei Li, Huawei Li
2025	A*	`conf`	Hydra: Scale-out FHE Accelerator Architecture for Secure Deep Learning on FPGA. HPCA Yinghao Yang, Xicheng Xu, Haibin Zhang, Jie Song, Xin Tang, Hang Lu, Xiaowei Li
2025	A*	`conf`	Hypnos: Memory Efficient Homomorphic Processing Unit. DAC Haoxuan Wang, Yinghao Yang, Hang Lu, Xiaowei Li
2025	J	`jnl`	KPU: Kernel Processing Unit for in-Memory Analytical Query Processing. IEEE Trans. Computers Jingya Wu, Wenyan Lu, Haishuang Fan, Hao Kong, Xiaowei Li, Guihai Yan
2025	A*	`conf`	MOSS: Multi-Modal Representation Learning on Sequential Circuits. DAC Mingjun Wang, Bin Sun, Jianan Mu, Feng Gu, Boyu Han, Tianmeng Yang, Xinyu Zhang, Silin Liu, Yihan Wen, Hui Wang, Jun Gao, Zhiteng Chao, Husheng Han, Zizhen Liu, Shengwen Liang, Jing Ye, Bei Yu, Xiaowei Li, Huawei Li
2025	A*	`conf`	Make LLM Inference Affordable to Everyone: Augmenting GPU Memory with NDP-DIMM. HPCA Lian Liu, Shixin Zhao, Bing Li, Haimeng Ren, Zhaohui Xu, Mengdi Wang, Xiaowei Li, Yinhe Han, Ying Wang
2025	J	`jnl`	Make LLM Inference Affordable to Everyone: Augmenting GPU Memory with NDP-DIMM. CoRR Lian Liu, Shixin Zhao, Bing Li, Haimeng Ren, Zhaohui Xu, Mengdi Wang, Xiaowei Li, Yinhe Han, Ying Wang
2025	J	`jnl`	Memory-Efficient and Adaptive Heterogeneous Framework for Gate-Level Fault Simulation. ACM Trans. Design Autom. Electr. Syst. Zhiteng Chao, Feng Gu, JunYing Huang, Wenjie Li, Jing Ye, Huawei Li, Xiaowei Li
2025	A*	`conf`	NeuVSA: A Unified and Efficient Accelerator for Neural Vector Search. HPCA Ziming Yuan, Lei Dai, Wen Li, Jie Zhang, Shengwen Liang, Ying Wang, Cheng Liu, Huawei Li, Xiaowei Li, Jiafeng Guo, Peng Wang, Renhai Chen, Gong Zhang
2025	—	`conf`	PAPI: Exploiting Dynamic Parallelism in Large Language Model Decoding with a Processing-In-Memory-Enabled Computing System. ASPLOS (2) Yintao He, Haiyu Mao, Christina Giannoula, Mohammad Sadrosadati, Juan Gómez-Luna, Huawei Li, Xiaowei Li, Ying Wang, Onur Mutlu
2025	J	`jnl`	PAPI: Exploiting Dynamic Parallelism in Large Language Model Decoding with a Processing-In-Memory-Enabled Computing System. CoRR Yintao He, Haiyu Mao, Christina Giannoula, Mohammad Sadrosadati, Juan Gómez-Luna, Huawei Li, Xiaowei Li, Ying Wang, Onur Mutlu
2025	A*	`conf`	PastATPG: A Hybrid ATPG Framework for Better Test Compaction with Partial Assignment SAT. DAC Zhiteng Chao, Xindi Zhang, Xinyu Zhang, Jianan Mu, Zizhen Liu, Shengwen Liang, Shaowei Cai, Jing Ye, Xiaowei Li, Huawei Li
2025	A	`conf`	RTPU: Unifying Non-Private and Private Inference with Reconfigurable Architecture. ICCAD Fuping Li, Ying Wang, Yinghao Yang, Jingxuan Li, Yibo Du, Huawei Li, Yinhe Han, Hang Lu, Xiaowei Li
2025	A	`conf`	SNO: Securing Network Function Offloading on FPGA-based SmartNICs in Untrusted Clouds. ICCAD Yunkun Liao, Jingya Wu, Wenyan Lu, Hang Lu, Xiaowei Li, Guihai Yan
2025	C	`conf`	SecNPU: Securing LLM Inference on NPU. ICCD Xuanyao Peng, Yinghao Yang, Shangjie Pan, Junjie Huang, Yujun Liang, Hang Lu, Fengwei Zhang, Xiaowei Li
2025	J	`jnl`	Sharing Can be Threatening: Uncovering Security Flaws of RBAC Model on Smart Home Platforms. IEEE Trans. Dependable Secur. Comput. Yiyu Yang, Jiayu Zhao, Yilian Li, Xiaowei Li, Peng Liu, Yuqing Zhang
2025	A	`conf`	TESLA: Testability Enhancement for Shift-Left Automation via Multi-LLM Collaboration. ITC Zhiteng Chao, Rengang Zhang, Feng Gu, Hongqin Lyu, Bin Sun, Wenxing Li, Zizhen Liu, Jianan Mu, Jing Ye, Xiaowei Li, Huawei Li
2025	J	`jnl`	TL-PBFT: An Improved PBFT Consensus Algorithm Based on Tree-layered Communication Structure. KSII Trans. Internet Inf. Syst. Liliang Lei, Guifeng Wu, Dengqi Yang, Benhui Chen, Xiaowei Li
2025	A	`conf`	Taijigraph: an Out-Of-Core Graph Processing System Enhanced with Computational Storage. IPDPS Xinmiao Zhang, Cheng Liu, Shengwen Liang, Hayden Kwok-Hay So, Ying Wang, Lei Zhang, Huawei Li, Xiaowei Li
2025	J	`jnl`	Trident: The Acceleration Architecture for High-Performance Private Set Intersection. IEEE Trans. Computers Jinkai Zhang, Yinghao Yang, Zhe Zhou, Zhicheng Hu, Xin Zhao, Liang Chang, Hang Lu, Xiaowei Li
2025	A	`conf`	Uranus: Ultra-efficient Acceleration Architecture for the Privacy Inference of Graph Neural Networks. ICCAD Xicheng Xu, Yinghao Yang, Fuyao Liu, Xiaowei Li, Hang Lu
2024	B	`conf`	A Fast Test Compaction Method for Commercial DFT Flow Using Dedicated Pure-MaxSAT Solver. ASPDAC Zhiteng Chao, Xindi Zhang, JunYing Huang, Jing Ye, Shaowei Cai, Huawei Li, Xiaowei Li
2024	B	`conf`	A Fully Pipelined High-Performance Elliptic Curve Cryptography Processor for NIST P-256. ETS Han Yan, Shuai Chen, JunYing Huang, Jing Ye, Huawei Li, Xiaowei Li
2024	—	`conf`	A Static Test Compaction Method Based on GCN Assisted Fault Gate Classification. ITC-Asia Zhiteng Chao, Qinluan Dai, Jiale Li, Zizhen Liu, Wenxing Li, Hongqin Lyu, Jing Ye, Huawei Li, Xiaowei Li
2024	J	`jnl`	A Task-Adaptive In-Situ ReRAM Computing for Graph Convolutional Networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yintao He, Bing Li, Ying Wang, Cheng Liu, Huawei Li, Xiaowei Li
2024	A	`conf`	AGC: A Unified Architecture for Accelerating K-Nearest Neighbor Graph Construction in Vector Search. ICCAD Lei Dai, Ziming Yuan, Wen Li, Shengwen Liang, Kaiwei Zou, Ying Wang, Cheng Liu, Huawei Li, Xiaowei Li
2024	A	`conf`	AMST: Accelerating Large-Scale Graph Minimum Spanning Tree Computation on FPGA. IPDPS Haishuang Fan, Rui Meng, Qichu Sun, Jingya Wu, Wenyan Lu, Xiaowei Li, Guihai Yan
2024	B	`conf`	APoX: Accelerate Graph-Based Deep Point Cloud Analysis via Adaptive Graph Construction. ASPDAC Lei Dai, Shengwen Liang, Ying Wang, Huawei Li, Xiaowei Li
2024	—	`conf`	Accelerating Sequential Circuit Simulation with Spatial Locality Enhancement and Redundant Event Reduction. ATS Jiaping Tang, Zizhen Liu, Jianan Mu, Feng Gu, Mingjun Wang, Wenxing Li, Jing Ye, Xiaowei Li, Huawei Li
2024	A*	`conf`	Alchemist: A Unified Accelerator Architecture for Cross-Scheme Fully Homomorphic Encryption. DAC Jianan Mu, Husheng Han, Shangyi Shi, Jing Ye, Zizhen Liu, Shengwen Liang, Meng Li, Mingzhe Zhang, Song Bian, Xing Hu, Huawei Li, Xiaowei Li
2024	J	`jnl`	An Automatic Neural Network Architecture-and-Quantization Joint Optimization Framework for Efficient Model Inference. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Lian Liu, Ying Wang, Xiandong Zhao, Weiwei Chen, Huawei Li, Xiaowei Li, Yinhe Han
2024	J	`jnl`	An Energy-Efficient In-Memory Accelerator for Graph Construction and Updating. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Mingkai Chen, Cheng Liu, Shengwen Liang, Lei He, Ying Wang, Lei Zhang, Huawei Li, Xiaowei Li
2024	J	`jnl`	ApproxPilot: A GNN-based Accelerator Approximation Framework. CoRR Qing Zhang, Cheng Liu, Siting Liu, Yajuan Hui, Huawei Li, Xiaowei Li
2024	—	`conf`	Athena: Add More Intelligence to RMT-Based Network Data Plane with Low-Bit Quantization. Euro-Par (2) Yunkun Liao, Hanyue Lin, Jingya Wu, Wenyan Lu, Huawei Li, Xiaowei Li, Guihai Yan
2024	A	`conf`	Bit-Trimmer: Ineffectual Bit-Operation Removal for CLM Architecture. DATE Yintao He, Shixin Zhao, Songyun Qu, Huawei Li, Xiaowei Li, Ying Wang
2024	J	`jnl`	COMET: Towards Partical W4A4KV4 LLMs Serving. CoRR Lian Liu, Haimeng Ren, Long Cheng, Zhaohui Xu, Yudong Pan, Mengdi Wang, Xiaowei Li, Yinhe Han, Ying Wang
2024	B	`conf`	Chipletizer: Repartitioning SoCs for Cost-Effective Chiplet Integration. ASPDAC Fuping Li, Ying Wang, Yujie Wang, Mengdi Wang, Yinhe Han, Huawei Li, Xiaowei Li
2024	A*	`conf`	Chiplever: Towards Effortless Extension of Chiplet-based System for FHE. DAC Yibo Du, Ying Wang, Bing Li, Fuping Li, Shengwen Liang, Huawei Li, Xiaowei Li, Yinhe Han
2024	A*	`conf`	Co-Via: A Video Frame Interpolation Accelerator Exploiting Codec Information Reuse. DAC Haishuang Fan, Qichu Sun, Jingya Wu, Wenyan Lu, Xiaowei Li, Guihai Yan
2024	A	`conf`	DDP-Fsim: Efficient and Scalable Fault Simulation for Deterministic Patterns with Two-Dimensional Parallelism. ICCAD Feng Gu, Mingjun Wang, Jianan Mu, Zizhen Liu, Jiaping Tang, Hui Wang, Yonghao Wang, Jing Ye, Huawei Li, Xiaowei Li
2024	J	`jnl`	DPU-Direct: Unleashing Remote Accelerators via Enhanced RDMA for Disaggregated Datacenters. IEEE Trans. Computers Yunkun Liao, Jingya Wu, Wenyan Lu, Xiaowei Li, Guihai Yan
2024	J	`jnl`	DRIM-ANN: An Approximate Nearest Neighbor Search Engine based on Commercial DRAM-PIMs. CoRR Mingkai Chen, Tianhua Han, Cheng Liu, Shengwen Liang, Kuai Yu, Lei Dai, Ziming Yuan, Ying Wang, Lei Zhang, Huawei Li, Xiaowei Li
2024	A*	`conf`	Data is all you need: Finetuning LLMs for Chip Design via an Automated design-data augmentation framework. DAC Kaiyan Chang, Kun Wang, Nan Yang, Ying Wang, Dantong Jin, Wenlong Zhu, Zhirong Chen, Cangyuan Li, Hao Yan, Yunhao Zhou, Zhuoliang Zhao, Yuan Cheng, Yudong Pan, Yiqi Liu, Mengdi Wang, Shengwen Liang, Yinhe Han, Huawei Li, Xiaowei Li
2024	J	`jnl`	Data is all you need: Finetuning LLMs for Chip Design via an Automated design-data augmentation framework. CoRR Kaiyan Chang, Kun Wang, Nan Yang, Ying Wang, Dantong Jin, Wenlong Zhu, Zhirong Chen, Cangyuan Li, Hao Yan, Yunhao Zhou, Zhuoliang Zhao, Yuan Cheng, Yudong Pan, Yiqi Liu, Mengdi Wang, Shengwen Liang, Yinhe Han, Huawei Li, Xiaowei Li
2024	A*	`conf`	Drift: Leveraging Distribution-based Dynamic Precision Quantization for Efficient Deep Neural Network Acceleration. DAC Lian Liu, Zhaohui Xu, Yintao He, Ying Wang, Huawei Li, Xiaowei Li, Yinhe Han
2024	—	`conf`	Efficient Functional Safety Method for Gate-Level Fine-Grained Digital Circuits with ISO-26262. ITC-Asia Mingjun Wang, Hui Wang, Jianan Mu, Zizhen Liu, Jun Gao, Jing Ye, Huawei Li, Xiaowei Li
2024	—	`conf`	Efficient RNIC Cache Side-Channel Attack Detection Through DPU-Driven Architecture. Euro-Par (2) Yunkun Liao, Jingya Wu, Wenyan Lu, Xiaowei Li, Guihai Yan
2024	A	`conf`	GPACE: An Energy-Efficient PQ-Based GCN Accelerator with Redundancy Reduction. DATE Yibo Du, Shengwen Liang, Ying Wang, Huawei Li, Xiaowei Li, Yinhe Han
2024	J	`jnl`	General Purpose Deep Learning Accelerator Based on Bit Interleaving. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Liang Chang, Hang Lu, Chenglong Li, Xin Zhao, Zhicheng Hu, Jun Zhou, Xiaowei Li
2024	J	`jnl`	Graphitron: A Domain Specific Language for FPGA-based Graph Processing Accelerator Generation. CoRR Xinmiao Zhang, Zheng Feng, Shengwen Liang, Xinyu Chen, Cheng Liu, Huawei Li, Xiaowei Li
2024	A	`conf`	HLSPilot: LLM-based High-Level Synthesis. ICCAD Chenwei Xiong, Cheng Liu, Huawei Li, Xiaowei Li
2024	J	`jnl`	HLSPilot: LLM-based High-Level Synthesis. CoRR Chenwei Xiong, Cheng Liu, Huawei Li, Xiaowei Li
2024	A	`conf`	HyQA: Hybrid Near-Data Processing Platform for Embedding Based Question Answering System. DATE Shengwen Liang, Ziming Yuan, Ying Wang, Dawen Xu, Huawei Li, Xiaowei Li
2024	J	`jnl`	IICPilot: An Intelligent Integrated Circuit Backend Design Framework Using Open EDA. CoRR Zesong Jiang, Qing Zhang, Cheng Liu, Huawei Li, Xiaowei Li
2024	J	`jnl`	MCU-MixQ: A HW/SW Co-optimized Mixed-precision Neural Network Design Framework for MCUs. CoRR Junfeng Gong, Cheng Liu, Long Cheng, Huawei Li, Xiaowei Li
2024	J	`jnl`	MRFI: An Open-Source Multiresolution Fault Injection Framework for Neural Network Processing. IEEE Trans. Very Large Scale Integr. Syst. Haitong Huang, Cheng Liu, Xinghua Xue, Bo Liu, Huawei Li, Xiaowei Li
2024	J	`jnl`	Mortar-FP8: Morphing the Existing FP32 Infrastructure for High-Performance Deep Learning Acceleration. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Hongyan Li, Hang Lu, Xiaowei Li
2024	J	`jnl`	PDG: A Prefetcher for Dynamic Graph Updating. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Xinmiao Zhang, Cheng Liu, Jiacheng Ni, Yuanqing Cheng, Lei Zhang, Huawei Li, Xiaowei Li
2024	A*	`conf`	PHD: Parallel Huffman Decoder on FPGA for Extreme Performance and Energy Efficiency. DAC Yunkun Liao, Jingya Wu, Wenyan Lu, Xiaowei Li, Guihai Yan
2024	J	`jnl`	SPFL: A Self-Purified Federated Learning Method Against Poisoning Attacks. IEEE Trans. Inf. Forensics Secur. Zizhen Liu, Weiyang He, Chip-Hong Chang, Jing Ye, Huawei Li, Xiaowei Li
2024	J	`jnl`	SigDLA: A Deep Learning Accelerator Extension for Signal Processing. CoRR Fangfa Fu, Wenyu Zhang, Zesong Jiang, Zhiyu Zhu, Guoyu Li, Bing Yang, Cheng Liu, Liyi Xiao, Jinxiang Wang, Huawei Li, Xiaowei Li
2024	—	`conf`	TianMen: a DPU-based storage network offloading structure for disaggregated datacenters. SoCC Weiyue Zhao, Jingya Wu, Wenyan Lu, Xiaowei Li, Guihai Yan
2023	—	`conf`	A Distributed ATPG System Combining Test Compaction Based on Pure MaxSAT. ATS Zhiteng Chao, Senlin Wang, Pengyu Tian, Shuwen Yuan, Huawei Li, Jing Ye, Xiaowei Li
2023	—	`conf`	A Template Attack on Reduction Without Reference Device on Kyber. ATS Yipei Yang, JunYing Huang, Zongyue Wang, Jing Ye, Zihao Sun, Junfeng Fan, Shuai Chen, Huawei Li, Xiaowei Li, Yuan Cao
2023	J	`jnl`	Accelerating Deformable Convolution Networks with Dynamic and Irregular Memory Accesses. ACM Trans. Design Autom. Electr. Syst. Cheng Chu, Cheng Liu, Dawen Xu, Ying Wang, Tao Luo, Huawei Li, Xiaowei Li
2023	—	`conf`	Adversarial Testing: A Novel On-Line Testing Method for Deep Learning Processors. ATS Wen Li, Ying Wang, Kaiwei Zou, Huawei Li, Xiaowei Li
2023	J	`jnl`	ApproxABFT: Approximate Algorithm-Based Fault Tolerance for Vision Transformers. CoRR Xinghua Xue, Cheng Liu, Haitong Huang, Ying Wang, Bing Yang, Tao Luo, Lei Zhang, Huawei Li, Xiaowei Li
2023	B	`conf`	BitColor: Accelerating Large-Scale Graph Coloring on FPGA with Parallel Bit-Wise Engines. ICPP Haishuang Fan, Ming Li, Jingya Wu, Wenyan Lu, Xiaowei Li, Guihai Yan
2023	J	`jnl`	BitXpro: Regularity-Aware Hardware Runtime Pruning for Deep Neural Networks. IEEE Trans. Very Large Scale Integr. Syst. Hongyan Li, Hang Lu, Haoxuan Wang, Shengji Deng, Xiaowei Li
2023	—	`book`	Built-in Fault-Tolerant Computing Paradigm for Resilient Large-Scale Chip Design - A Self-Test, Self-Diagnosis, and Self-Repair-Based Approach Xiaowei Li, Guihai Yan, Cheng Liu
2023	J	`jnl`	ChipGPT: How far are we from natural language hardware design. CoRR Kaiyan Chang, Ying Wang, Haimeng Ren, Mengdi Wang, Shengwen Liang, Yinhe Han, Huawei Li, Xiaowei Li
2023	J	`jnl`	Chosen ciphertext correlation power analysis on Kyber. Integr. Yipei Yang, Zongyue Wang, Jing Ye, Junfeng Fan, Shuai Chen, Huawei Li, Xiaowei Li, Yuan Cao
2023	B	`conf`	Co-ViSu: a Video Super-Resolution Accelerator Exploiting Codec Information Reuse. FPL Haishuang Fan, Jingya Wu, Wenyan Lu, Xiaowei Li, Guihai Yan
2023	—	`conf`	Configurable and High-Level Pipelined Lattice-Based Post Quantum Cryptography Hardware Accelerator Design. ATS Jianan Mu, Huajie Tan, Shuai Chen, Min Cai, Jing Ye, Huawei Li, Xiaowei Li
2023	J	`jnl`	Cross-Layer Optimization for Fault-Tolerant Deep Learning. CoRR Qing Zhang, Cheng Liu, Bo Liu, Haitong Huang, Ying Wang, Huawei Li, Xiaowei Li
2023	J	`jnl`	DHSA: efficient doubly homomorphic secure aggregation for cross-silo federated learning. J. Supercomput. Zizhen Liu, Si Chen, Jing Ye, Junfeng Fan, Huawei Li, Xiaowei Li
2023	J	`jnl`	DOE: database offloading engine for accelerating SQL processing. Distributed Parallel Databases Hao Kong, Wenyan Lu, Yan Chen, Jingya Wu, Yu Zhang, Guihai Yan, Xiaowei Li
2023	A	`conf`	DeepBurning-MixQ: An Open Source Mixed-Precision Neural Network Accelerator Design Framework for FPGAs. ICCAD Erjing Luo, Haitong Huang, Cheng Liu, Guoyu Li, Bing Yang, Ying Wang, Huawei Li, Xiaowei Li
2023	J	`jnl`	DeepBurning-MixQ: An Open Source Mixed-Precision Neural Network Accelerator Design Framework for FPGAs. CoRR Erjing Luo, Haitong Huang, Cheng Liu, Guoyu Li, Bing Yang, Ying Wang, Huawei Li, Xiaowei Li
2023	A	`conf`	Energy-efficient NTT Design with One-bank SRAM and 2-D PE Array. DATE Jianan Mu, Huajie Tan, Jiawen Wu, Haotian Lu, Chip-Hong Chang, Shuai Chen, Shengwen Liang, Jing Ye, Huawei Li, Xiaowei Li
2023	J	`jnl`	Exploring Winograd Convolution for Cost-Effective Neural Network Fault Tolerance. IEEE Trans. Very Large Scale Integr. Syst. Xinghua Xue, Cheng Liu, Bo Liu, Haitong Huang, Ying Wang, Tao Luo, Lei Zhang, Huawei Li, Xiaowei Li
2023	J	`jnl`	Exploring Winograd Convolution for Cost-effective Neural Network Fault Tolerance. CoRR Xinghua Xue, Cheng Liu, Bo Liu, Haitong Huang, Ying Wang, Tao Luo, Lei Zhang, Huawei Li, Xiaowei Li
2023	—	`conf`	KPU-SQL: Kernel Processing Unit for High-Performance SQL Acceleration. ACM Great Lakes Symposium on VLSI Hao Kong, Haishuang Fan, Jingya Wu, Liyun Cheng, Yan Chen, Wenyan Lu, Guihai Yan, Xiaowei Li
2023	—	`conf`	M2VT: A Multi-Output Encoder Accelerator for Multiple-Way Video Transcoding. ACM Great Lakes Symposium on VLSI Haishuang Fan, Jingya Wu, Wenyan Lu, Xiaowei Li, Guihai Yan
2023	J	`jnl`	MRFI: An Open Source Multi-Resolution Fault Injection Framework for Neural Network Processing. CoRR Haitong Huang, Cheng Liu, Xinghua Xue, Ying Wang, Huawei Li, Xiaowei Li
2023	J	`jnl`	On-Line Fault Protection for ReRAM-Based Neural Networks. IEEE Trans. Computers Wen Li, Ying Wang, Cheng Liu, Yintao He, Lian Liu, Huawei Li, Xiaowei Li
2023	B	`conf`	Online Reliability Evaluation Design: Select Reliable CRPs for Arbiter PUF and Its Variants. ETS Chaofang Ma, Jianan Mu, Jing Ye, Shuai Chen, Yuan Cao, Huawei Li, Xiaowei Li
2023	—	`conf`	Optimize the TX Architecture of RDMA NIC for Performance Isolation in the Cloud Environment. ACM Great Lakes Symposium on VLSI Yunkun Liao, Jingya Wu, Wenyan Lu, Xiaowei Li, Guihai Yan
2023	C	`conf`	PANG: A Pattern-Aware GCN Accelerator for Universal Graphs. ICCD Yibo Du, Ying Wang, Shengwen Liang, Huawei Li, Xiaowei Li, Yinhe Han
2023	J	`jnl`	Poseidon-NDP: Practical Fully Homomorphic Encryption Accelerator Based on Near Data Processing Architecture. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yinghao Yang, Hang Lu, Xiaowei Li
2023	A*	`conf`	Poseidon: Practical Homomorphic Encryption Accelerator. HPCA Yinghao Yang, Huaizhi Zhang, Shengyu Fan, Hang Lu, Mingzhe Zhang, Xiaowei Li
2023	J	`jnl`	Reliability Analysis of Vision Transformers. CoRR Xinghua Xue, Cheng Liu, Ying Wang, Bing Yang, Tao Luo, Lei Zhang, Huawei Li, Xiaowei Li
2023	J	`jnl`	SPFL: A Self-purified Federated Learning Method Against Poisoning Attacks. CoRR Zizhen Liu, Weiyang He, Chip-Hong Chang, Jing Ye, Huawei Li, Xiaowei Li
2023	J	`jnl`	Scalable and Conflict-Free NTT Hardware Accelerator Design: Methodology, Proof, and Implementation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jianan Mu, Yi Ren, Wen Wang, Yizhong Hu, Shuai Chen, Chip-Hong Chang, Junfeng Fan, Jing Ye, Yuan Cao, Huawei Li, Xiaowei Li
2023	J	`jnl`	Soft Error Reliability Analysis of Vision Transformers. IEEE Trans. Very Large Scale Integr. Syst. Xinghua Xue, Cheng Liu, Ying Wang, Bing Yang, Tao Luo, Lei Zhang, Huawei Li, Xiaowei Li
2023	J	`jnl`	Statistical Modeling of Soft Error Influence on Neural Networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Haitong Huang, Xinghua Xue, Cheng Liu, Ying Wang, Tao Luo, Long Cheng, Huawei Li, Xiaowei Li
2022	J	`jnl`	A Fast Precision Tuning Solution for Always-On DNN Accelerators. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ying Wang, Yintao He, Long Cheng, Huawei Li, Xiaowei Li
2022	—	`conf`	A Voltage Template Attack on the Modular Polynomial Subtraction in Kyber. ASP-DAC Jianan Mu, Yixuan Zhao, Zongyue Wang, Jing Ye, Junfeng Fan, Shuai Chen, Huawei Li, Xiaowei Li, Yuan Cao
2022	J	`jnl`	A robust authentication scheme for remote diagnosis and maintenance in 5G V2N. J. Netw. Comput. Appl. Ruhui Ma, Jin Cao, Dengguo Feng, Hui Li, Xiaowei Li, Yang Xu
2022	A*	`conf`	AGNAS: Attention-Guided Micro and Macro-Architecture Search. ICML Zihao Sun, Yu Hu, Shun Lu, Longxing Yang, Jilin Mei, Yinhe Han, Xiaowei Li
2022	J	`jnl`	An Efficient Deep Learning Accelerator Architecture for Compressed Video Analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yongchen Wang, Ying Wang, Huawei Li, Xiaowei Li
2022	J	`jnl`	CAP: Communication-Aware Automated Parallelization for Deep Learning Inference on CMP Architectures. IEEE Trans. Computers Kaiwei Zou, Ying Wang, Long Cheng, Songyun Qu, Huawei Li, Xiaowei Li
2022	B	`conf`	Closing the Dynamics Gap via Adversarial and Reinforcement Learning for High-Speed Racing. IJCNN Jingyu Niu, Yu Hu, Wei Li, Guangyan Huang, Yinhe Han, Xiaowei Li
2022	J	`jnl`	Cognitive SSD+: a deep learning engine for energy-efficient unstructured data retrieval. CCF Trans. High Perform. Comput. Shengwen Liang, Ying Wang, Huawei Li, Xiaowei Li
2022	J	`jnl`	DHSA: Efficient Doubly Homomorphic Secure Aggregation for Cross-silo Federated Learning. CoRR Zizhen Liu, Si Chen, Jing Ye, Junfeng Fan, Huawei Li, Xiaowei Li
2022	—	`conf`	DOE: Database Offloading Engine for Accelerating SQL Processing. ICDE Workshops Wenyan Lu, Yan Chen, Jingya Wu, Yu Zhang, Xiaowei Li, Guihai Yan
2022	—	`conf`	Exploring the high-throughput and low-delay hardware design of SM4 on FPGA. ISOCC Yixiao Chen, Jinfeng Song, Shuai Chen, Yuan Cao, Jing Ye, Huawei Li, Xiaowei Li, Xin Lou, Enyi Yao
2022	J	`jnl`	Fault-Tolerant Deep Learning: A Hierarchical Perspective. CoRR Cheng Liu, Zhen Gao, Siting Liu, Xuefei Ning, Huawei Li, Xiaowei Li
2022	A	`conf`	GIA: A Reusable General Interposer Architecture for Agile Chiplet Integration. ICCAD Fuping Li, Ying Wang, Yuanqing Cheng, Yujie Wang, Yinhe Han, Huawei Li, Xiaowei Li
2022	J	`jnl`	HyCA: A Hybrid Computing Architecture for Fault-Tolerant Deep Learning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Cheng Liu, Cheng Chu, Dawen Xu, Ying Wang, Qianlong Wang, Huawei Li, Xiaowei Li, Kwang-Ting Cheng
2022	A*	`conf`	InfoX: an energy-efficient ReRAM accelerator design with information-lossless low-bit ADCs. DAC Yintao He, Songyun Qu, Ying Wang, Bing Li, Huawei Li, Xiaowei Li
2022	A	`conf`	NoCeption: A Fast PPA Prediction Framework for Network-on-Chips Using Graph Neural Network. DATE Fuping Li, Ying Wang, Cheng Liu, Huawei Li, Xiaowei Li
2022	J	`jnl`	Portrait: A holistic computation and bandwidth balanced performance evaluation model for heterogeneous systems. Sustain. Comput. Informatics Syst. Jingya Wu, Wenyan Lu, Guihai Yan, Xiaowei Li
2022	C	`conf`	Reexamining CGRA Memory Sub-system for Higher Memory Utilization and Performance. ICCD Lei Dai, Ying Wang, Cheng Liu, Fuping Li, Huawei Li, Xiaowei Li
2022	A	`conf`	SASH: Efficient secure aggregation based on SHPRG for federated learning. UAI Zizhen Liu, Si Chen, Jing Ye, Junfeng Fan, Huawei Li, Xiaowei Li
2022	J	`jnl`	STC-NAS: Fast neural architecture search with source-target consistency. Neurocomputing Zihao Sun, Yu Hu, Longxing Yang, Shun Lu, Jilin Mei, Yinhe Han, Xiaowei Li
2022	J	`jnl`	Saving Energy of RRAM-Based Neural Accelerator Through State-Aware Computing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yintao He, Ying Wang, Huawei Li, Xiaowei Li
2022	A*	`conf`	Searching for BurgerFormer with Micro-Meso-Macro Space Design. ICML Longxing Yang, Yu Hu, Shun Lu, Zihao Sun, Jilin Mei, Yinhe Han, Xiaowei Li
2022	Misc	`conf`	Special Session: Fault-Tolerant Deep Learning: A Hierarchical Perspective. VTS Cheng Liu, Zhen Gao, Siting Liu, Xuefei Ning, Huawei Li, Xiaowei Li
2022	J	`jnl`	Statistical Modeling of Soft Error Influence on Neural Networks. CoRR Haitong Huang, Xinghua Xue, Cheng Liu, Ying Wang, Tao Luo, Long Cheng, Huawei Li, Xiaowei Li
2022	J	`jnl`	Taming Process Variations in CNFET for Efficient Last-Level Cache Design. IEEE Trans. Very Large Scale Integr. Syst. Dawen Xu, Zhuangyu Feng, Cheng Liu, Li Li, Ying Wang, Huawei Li, Xiaowei Li
2022	J	`jnl`	VNet: a versatile network to train real-time semantic segmentation models on a single GPU. Sci. China Inf. Sci. Wenxing Li, Ning Lin, Mingzhe Zhang, Hang Lu, Xiaoming Chen, Xiaowei Li
2022	A*	`conf`	VStore: in-storage graph based vector search accelerator. DAC Shengwen Liang, Ying Wang, Ziming Yuan, Cheng Liu, Huawei Li, Xiaowei Li
2021	J	`jnl`	An Edge 3D CNN Accelerator for Low-Power Activity Recognition. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ying Wang, Yongchen Wang, Cong Shi, Long Cheng, Huawei Li, Xiaowei Li
2021	B	`conf`	BitX: Empower Versatile Inference with Hardware Runtime Pruning. ICPP Hongyan Li, Hang Lu, Jiawen Huang, Wenxu Wang, Mingzhe Zhang, Wei Chen, Liang Chang, Xiaowei Li
2021	—	`conf`	ChaoPIM: A PIM-based Protection Framework for DNN Accelerators Using Chaotic Encryption. ATS Ning Lin, Xiaoming Chen, Chunwei Xia, Jing Ye, Xiaowei Li
2021	J	`jnl`	Chaotic Weights: A Novel Approach to Protect Intellectual Property of Deep Neural Networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ning Lin, Xiaoming Chen, Hang Lu, Xiaowei Li
2021	C	`conf`	DDSAS: Dynamic and Differentiable Space-Architecture Search. ACML Longxing Yang, Yu Hu, Shun Lu, Zihao Sun, Jilin Mei, Yiming Zeng, Zhiping Shi, Yinhe Han, Xiaowei Li
2021	A	`conf`	DU-DARTS: Decreasing the Uncertainty of Differentiable Architecture Search. BMVC Shun Lu, Yu Hu, Longxing Yang, Zihao Sun, Jilin Mei, Yiming Zeng, Xiaowei Li
2021	J	`jnl`	Efficient Secure Aggregation Based on SHPRG For Federated Learning. CoRR Zizhen Liu, Si Chen, Jing Ye, Junfeng Fan, Huawei Li, Xiaowei Li
2021	J	`jnl`	EnGN: A High-Throughput and Energy-Efficient Accelerator for Large Graph Neural Networks. IEEE Trans. Computers Shengwen Liang, Ying Wang, Cheng Liu, Lei He, Huawei Li, Dawen Xu, Xiaowei Li
2021	J	`jnl`	Energy-Efficient Accelerator Design for Deformable Convolution Networks. CoRR Dawen Xu, Cheng Chu, Cheng Liu, Ying Wang, Huawei Li, Xiaowei Li, Kwang-Ting Cheng
2021	A*	`conf`	GCiM: A Near-Data Processing Accelerator for Graph Construction. DAC Lei He, Cheng Liu, Ying Wang, Shengwen Liang, Huawei Li, Xiaowei Li
2021	—	`conf`	GLIST: Towards In-Storage Graph Learning. USENIX ATC Cangyuan Li, Ying Wang, Cheng Liu, Shengwen Liang, Huawei Li, Xiaowei Li
2021	J	`jnl`	Happy Emotion Recognition From Unconstrained Videos Using 3D Hybrid Deep Features. IEEE Access Najmeh Samadiani, Guangyan Huang, Yu Hu, Xiaowei Li
2021	J	`jnl`	HyCA: A Hybrid Computing Architecture for Fault Tolerant Deep Learning. CoRR Dawen Xu, Qianlong Wang, Cheng Liu, Cheng Chu, Ying Wang, Huawei Li, Xiaowei Li, Kwang-Ting Cheng
2021	J	`jnl`	Internet connected vehicle platoon system modeling and linear stability analysis. Comput. Commun. Lidong Zhang, Mengmeng Zhang, Jian Wang, Xiaowei Li, Wenxing Zhu
2021	A*	`conf`	KFS-LIO: Key-Feature Selection for Lightweight Lidar Inertial Odometry. ICRA Wei Li, Yu Hu, Yinhe Han, Xiaowei Li
2021	A*	`conf`	PixelSieve: Towards Efficient Activity Analysis From Compressed Video Streams. DAC Yongchen Wang, Ying Wang, Huawei Li, Xiaowei Li
2021	J	`jnl`	R2F: A Remote Retraining Framework for AIoT Processors With Computing Errors. IEEE Trans. Very Large Scale Integr. Syst. Dawen Xu, Meng He, Cheng Liu, Ying Wang, Long Cheng, Huawei Li, Xiaowei Li, Kwang-Ting Cheng
2021	J	`jnl`	R2F: A Remote Retraining Framework for AIoT Processors with Computing Errors. CoRR Dawen Xu, Meng He, Cheng Liu, Ying Wang, Long Cheng, Huawei Li, Xiaowei Li, Kwang-Ting Cheng
2021	—	`conf`	SeGa: A Trojan Detection Method Combined With Gate Semantics. ATS Yunying Ye, Shan Li, Haihua Shen, Huawei Li, Xiaowei Li
2021	J	`jnl`	ShuntFlowPlus: An Efficient and Scalable Dataflow Accelerator Architecture for Stream Applications. ACM J. Emerg. Technol. Comput. Syst. Shijun Gong, Jiajun Li, Wenyan Lu, Guihai Yan, Xiaowei Li
2021	Misc	`conf`	Special Session - Test for AI Chips: from DFT to On-line Testing. VTS Huawei Li, Xiaowei Li, Yu Huang, Ying Wang, Gary Guo
2021	A*	`conf`	TARe: Task-Adaptive in-situ ReRAM Computing for Graph Learning. DAC Yintao He, Ying Wang, Cheng Liu, Huawei Li, Xiaowei Li
2021	J	`jnl`	Taming Process Variations in CNFET for Efficient Last Level Cache Design. CoRR Dawen Xu, Zhuangyu Feng, Cheng Liu, Li Li, Ying Wang, Yuanqing Cheng, Huawei Li, Xiaowei Li
2021	J	`jnl`	To cloud or not to cloud: an on-line scheduler for dynamic privacy-protection of deep learning workload on edge devices. CCF Trans. High Perform. Comput. Yibin Tang, Ying Wang, Huawei Li, Xiaowei Li
2020	A	`conf`	A Many-Core Accelerator Design for On-Chip Deep Reinforcement Learning. ICCAD Ying Wang, Mengdi Wang, Bing Li, Huawei Li, Xiaowei Li
2020	A*	`conf`	An Efficient Deep Learning Accelerator for Compressed Video Analysis. DAC Yongchen Wang, Ying Wang, Huawei Li, Yinhe Han, Xiaowei Li
2020	J	`jnl`	Architecting Effectual Computation for Machine Learning Accelerators. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Hang Lu, Mingzhe Zhang, Yinhe Han, Qi Wang, Huawei Li, Xiaowei Li
2020	J	`jnl`	BZIP: A compact data memory system for UTXO-based blockchains. J. Syst. Archit. Shuhao Jiang, Jiajun Li, Shijun Gong, Junchao Yan, Guihai Yan, Yi Sun, Xiaowei Li
2020	A	`conf`	DeepBurning-GL: an Automated Framework for Generating Graph Neural Network Accelerators. ICCAD Shengwen Liang, Cheng Liu, Ying Wang, Huawei Li, Xiaowei Li
2020	J	`jnl`	Evaluating and Constraining Hardware Assertions with Absent Scenarios. J. Comput. Sci. Technol. Huina Chao, Huawei Li, Xiaoyu Song, Tiancheng Wang, Xiaowei Li
2020	A*	`conf`	Exploring Spatial-Temporal Multi-Frequency Analysis for High-Fidelity and Temporal-Consistency Video Prediction. CVPR Beibei Jin, Yu Hu, Qiankun Tang, Jingyu Niu, Zhiping Shi, Yinhe Han, Xiaowei Li
2020	J	`jnl`	Exploring Spatial-Temporal Multi-Frequency Analysis for High-Fidelity and Temporal-Consistency Video Prediction. CoRR Beibei Jin, Yu Hu, Qiankun Tang, Jingyu Niu, Zhiping Shi, Yinhe Han, Xiaowei Li
2020	J	`jnl`	INOR - An Intelligent noise reduction method to defend against adversarial audio examples. Neurocomputing Qingli Guo, Jing Ye, Yiran Chen, Yu Hu, Yazhu Lan, Guohe Zhang, Xiaowei Li
2020	J	`jnl`	MultiPAD: A Multivariant Partition-Based Method for Audio Adversarial Examples Detection. IEEE Access Qingli Guo, Jing Ye, Yu Hu, Guohe Zhang, Xiaowei Li, Huawei Li
2020	—	`conf`	Optimization Space Exploration of Hardware Design for CRYSTALS-KYBER. ATS Yixuan Zhao, Zhiteng Chao, Jing Ye, Wen Wang, Yuan Cao, Shuai Chen, Xiaowei Li, Huawei Li
2020	—	`conf`	Prediction Stability: A New Metric for Quantitatively Evaluating DNN Outputs. ACM Great Lakes Symposium on VLSI Qingli Guo, Jing Ye, Jiliang Zhang, Yu Hu, Xiaowei Li, Huawei Li
2020	—	`conf`	Search-free Accelerator for Sparse Convolutional Neural Networks. ASP-DAC Bosheng Liu, Xiaoming Chen, Yinhe Han, Ying Wang, Jiajun Li, Haobo Xu, Xiaowei Li
2020	Misc	`conf`	Sequence Triggered Hardware Trojan in Neural Network Accelerator. VTS Zizhen Liu, Jing Ye, Xing Hu, Huawei Li, Xiaowei Li, Yu Hu
2020	—	`conf`	Survey: Hardware Trojan Detection for Netlist. ATS Yipei Yang, Jing Ye, Yuan Cao, Jiliang Zhang, Xiaowei Li, Huawei Li, Yu Hu
2020	A*	`conf`	Towards State-Aware Computation in ReRAM Neural Networks. DAC Yintao He, Ying Wang, Xiandong Zhao, Huawei Li, Xiaowei Li
2020	J	`jnl`	Trajectory Tracking Based on Adaptive Sliding Mode Control for Agricultural Tractor. IEEE Access Chengqiang Yin, Shourui Wang, Xiaowei Li, Guanhao Yuan, Chao Jiang
2020	B	`conf`	Two-Stage Safe Reinforcement Learning for High-Speed Autonomous Racing. SMC Jingyu Niu, Yu Hu, Beibei Jin, Yinhe Han, Xiaowei Li
2019	A*	`conf`	A None-Sparse Inference Accelerator that Distills and Reuses the Computation Redundancy in CNNs. DAC Ying Wang, Shengwen Liang, Huawei Li, Xiaowei Li
2019	J	`jnl`	A QoS-QoR Aware CNN Accelerator Design Approach. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ying Wang, Huawei Li, Long Cheng, Xiaowei Li
2019	J	`jnl`	Accelerating DNN-based 3D point cloud processing for mobile computing. Sci. China Inf. Sci. Bosheng Liu, Xiaoming Chen, Yinhe Han, Jiajun Li, Haobo Xu, Xiaowei Li
2019	—	`conf`	Addressing the issue of processing element under-utilization in general-purpose systolic deep learning accelerators. ASP-DAC Bosheng Liu, Xiaoming Chen, Ying Wang, Yinhe Han, Jiajun Li, Haobo Xu, Xiaowei Li
2019	A	`conf`	An Agile Precision-Tunable CNN Accelerator based on ReRAM. ICCAD Yintao He, Ying Wang, Yongchen Wang, Huawei Li, Xiaowei Li
2019	A	`conf`	Asian Test Symposium - Past, Present and Future -. ITC Michiko Inoue, Xiaowei Li, Cheng-Wen Wu
2019	—	`conf`	BZIP: A Compact Data Memory System for UTXO-based Blockchains. ICESS Shuhao Jiang, Jiajun Li, Shijun Gong, Junchao Yan, Guihai Yan, Yi Sun, Xiaowei Li
2019	A	`conf`	China Test Conference (CTC) - Extending the Global Test Forum to China. ITC Huawei Li, Xiaowei Li, Yinhe Han
2019	J	`jnl`	Cluster Restoration-Based Trace Signal Selection for Post-Silicon Debug. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yun Cheng, Huawei Li, Ying Wang, Xiaowei Li
2019	—	`conf`	Cognitive SSD: A Deep Learning Engine for In-Storage Data Retrieval. USENIX ATC Shengwen Liang, Ying Wang, Youyou Lu, Zhe Yang, Huawei Li, Xiaowei Li
2019	J	`jnl`	Comments on "Provably Secure Dynamic Id-Based Anonymous Two-Factor Authenticated Key Exchange Protocol With Extended Security Model". IEEE Trans. Inf. Forensics Secur. Xiaowei Li, Dengqi Yang, Xing Zeng, Benhui Chen, Yuqing Zhang
2019	—	`conf`	CuckooPIM: an efficient and less-blocking coherence mechanism for processing-in-memory systems. ASP-DAC Sheng Xu, Xiaoming Chen, Ying Wang, Yinhe Han, Xiaowei Li
2019	—	`conf`	GramsDet: Hardware Trojan Detection Based on Recurrent Neural Network. ATS Renjie Lu, Haihua Shen, Yu Su, Huawei Li, Xiaowei Li
2019	J	`jnl`	HTDet: A Clustering Method using Information Entropy for Hardware Trojan Detection. CoRR Renjie Lu, Haihua Shen, Feng Zhang, Huawei Li, Wei Zhao, Xiaowei Li
2019	A*	`conf`	HeadStart: Enforcing Optimal Inceptions in Pruning Deep Neural Networks for Efficient Inference on GPGPUs. DAC Ning Lin, Hang Lu, Xin Wei, Xiaowei Li
2019	—	`conf`	Implementation of Parametric Hardware Trojan in FPGA. ITC-Asia Yipei Yang, Jing Ye, Xiaowei Li, Yinhe Han, Huawei Li, Yu Hu
2019	B	`conf`	InS-DLA: An In-SSD Deep Learning Accelerator for Near-Data Processing. FPL Shengwen Liang, Ying Wang, Cheng Liu, Huawei Li, Xiaowei Li
2019	—	`conf`	Instruction Vulnerability Test and Code Optimization Against DVFS Attack. ITC-Asia JunYing Huang, Jing Ye, Xiaochun Ye, Da Wang, Dongrui Fan, Huawei Li, Xiaowei Li, Zhimin Zhang
2019	A	`conf`	Learn-to-Scale: Parallelizing Deep Learning Inference on Chip Multiprocessor Architecture. DATE Kaiwei Zou, Ying Wang, Huawei Li, Xiaowei Li
2019	Misc	`conf`	Leveraging Memory PUFs and PIM-based encryption to secure edge deep learning systems. VTS Wen Li, Ying Wang, Huawei Li, Xiaowei Li
2019	—	`conf`	MLA: Machine Learning Adaptation for Realtime Streaming Financial Applications. IGSC Jingya Wu, Wenyan Lu, Guihai Yan, Xiaowei Li
2019	J	`jnl`	MV-Net: Toward Real-Time Deep Learning on Mobile GPGPU Systems. ACM J. Emerg. Technol. Comput. Syst. Yibin Tang, Ying Wang, Huawei Li, Xiaowei Li
2019	—	`conf`	P ASP-DAC Wen Li, Ying Wang, Huawei Li, Xiaowei Li
2019	J	`jnl`	PIMSim: A Flexible and Detailed Processing-in-Memory Simulator. IEEE Comput. Archit. Lett. Sheng Xu, Xiaoming Chen, Ying Wang, Yinhe Han, Xuehai Qian, Xiaowei Li
2019	J	`jnl`	PUFPass: A password management mechanism based on software/hardware codesign. Integr. Qingli Guo, Jing Ye, Bing Li, Yu Hu, Xiaowei Li, Yazhu Lan, Guohe Zhang
2019	J	`jnl`	Promoting the Harmony between Sparsity and Regularity: A Relaxed Synchronous Architecture for Convolutional Neural Networks. IEEE Trans. Computers Wenyan Lu, Guihai Yan, Jiajun Li, Shijun Gong, Shuhao Jiang, Jingya Wu, Xiaowei Li
2019	C	`conf`	RRAMedy: Protecting ReRAM-Based Neural Network from Permanent and Soft Faults During Its Lifetime. ICCD Wen Li, Ying Wang, Huawei Li, Xiaowei Li
2019	—	`conf`	Redeeming chip-level power efficiency by collaborative management of the computation and communication. ASP-DAC Ning Lin, Hang Lu, Xin Wei, Xiaowei Li
2019	J	`jnl`	Scan Chain Based Attacks and Countermeasures: A Survey. IEEE Access Xiaowei Li, Wenjie Li, Jing Ye, Huawei Li, Yu Hu
2019	A*	`conf`	ShuntFlow: An Efficient and Scalable Dataflow Accelerator Architecture for Streaming Applications. DAC Shijun Gong, Jiajun Li, Wenyan Lu, Guihai Yan, Xiaowei Li
2019	J	`jnl`	ShuttleNoC: Power-Adaptable Communication Infrastructure for Many-Core Processors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Hang Lu, Yisong Chang, Guihai Yan, Ning Lin, Xin Wei, Xiaowei Li
2019	—	`conf`	Simulate-the-hardware: training accurate binarized neural networks for low-precision neural accelerators. ASP-DAC Jiajun Li, Ying Wang, Bosheng Liu, Yinhe Han, Xiaowei Li
2019	J	`jnl`	SqueezeFlow: A Sparse CNN Accelerator Exploiting Concise Convolution Rules. IEEE Trans. Computers Jiajun Li, Shuhao Jiang, Shijun Gong, Jingya Wu, Junchao Yan, Guihai Yan, Xiaowei Li
2019	—	`conf`	Squeezing the Last MHz for CNN Acceleration on FPGAs. ITC-Asia Li Li, Dawen Xu, KouZi Xing, Cheng Liu, Ying Wang, Huawei Li, Xiaowei Li
2019	J	`jnl`	SynergyFlow: An Elastic Accelerator Architecture Supporting Batch Processing of Large-Scale Deep Neural Networks. ACM Trans. Design Autom. Electr. Syst. Jiajun Li, Guihai Yan, Wenyan Lu, Shijun Gong, Shuhao Jiang, Jingya Wu, Xiaowei Li
2019	A*	`conf`	Systolic Cube: A Spatial 3D CNN Accelerator Architecture for Low Power Video Analysis. DAC Yongchen Wang, Ying Wang, Huawei Li, Cong Shi, Xiaowei Li
2019	—	`conf`	TNPU: an efficient accelerator architecture for training convolutional neural networks. ASP-DAC Jiajun Li, Guihai Yan, Wenyan Lu, Shuhao Jiang, Shijun Gong, Jingya Wu, Junchao Yan, Xiaowei Li
2019	J	`jnl`	Thread: Towards fine-grained precision reconfiguration in variable-precision neural network accelerator. IEICE Electron. Express Shichang Zhang, Ying Wang, Xiaoming Chen, Yinhe Han, Yujie Wang, Xiaowei Li
2019	C	`conf`	VNet: A Versatile Network for Efficient Real-Time Semantic Segmentation. ICCD Ning Lin, Hang Lu, Jingliang Gao, Shunjie Qiao, Xiaowei Li
2019	C	`conf`	When Deep Learning Meets the Edge: Auto-Masking Deep Neural Networks for Efficient Machine Learning on Edge Devices. ICCD Ning Lin, Hang Lu, Xing Hu, Jingliang Gao, Mingzhe Zhang, Xiaowei Li
2019	C	`conf`	iATPG: Instruction-level Automatic Test Program Generation for Vulnerabilities under DVFS attack. IOLTS Kuozhong Zhang, JunYing Huang, Jing Ye, Xiaochun Ye, Da Wang, Dongrui Fan, Huawei Li, Xiaowei Li, Zhimin Zhang
2018	J	`jnl`	A Case of On-Chip Memory Subsystem Design for Low-Power CNN Accelerators. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ying Wang, Huawei Li, Xiaowei Li
2018	J	`jnl`	A Low Overhead In-Network Data Compressor for the Memory Hierarchy of Chip Multiprocessors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ying Wang, Huawei Li, Yinhe Han, Xiaowei Li
2018	A	`conf`	A retrospective evaluation of energy-efficient object detection solutions on embedded devices. DATE Ying Wang, Zhenyu Quan, Jiajun Li, Yinhe Han, Huawei Li, Xiaowei Li
2018	J	`jnl`	AdaFlow: Aggressive Convolutional Neural Networks Approximation by Leveraging the Input Variability. J. Low Power Electron. Wenyan Lu, Guihai Yan, Xiaowei Li
2018	—	`conf`	Bias PUF based Secure Scan Chain Design. AsianHOST Wenjie Li, Jing Ye, Xiaowei Li, Huawei Li, Yu Hu
2018	A	`conf`	CCR: A concise convolution rule for sparse neural network accelerators. DATE Jiajun Li, Guihai Yan, Wenyan Lu, Shuhao Jiang, Shijun Gong, Jingya Wu, Xiaowei Li
2018	J	`jnl`	Deterministic and Probabilistic Diagnostic Challenge Generation for Arbiter Physical Unclonable Function. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jing Ye, Qingli Guo, Yu Hu, Xiaowei Li
2018	J	`jnl`	Fault tolerance on-chip: a reliable computing paradigm using self-test, self-diagnosis, and self-repair (3S) approach. Sci. China Inf. Sci. Xiaowei Li, Guihai Yan, Jing Ye, Ying Wang
2018	—	`conf`	Grey Zone in Pre-Silicon Hardware Trojan Detection. ITC-Asia Jing Ye, Yipei Yang, Yue Gong, Yu Hu, Xiaowei Li
2018	—	`conf`	Hardware Trojan Detection Based on Signal Correlation. ATS Wei Zhao, Haihua Shen, Huawei Li, Xiaowei Li
2018	—	`conf`	Hardware Trojan in FPGA CNN Accelerator. ATS Jing Ye, Yu Hu, Xiaowei Li
2018	J	`jnl`	LMDet: A "Naturalness" Statistical Method for Hardware Trojan Detection. IEEE Trans. Very Large Scale Integr. Syst. Haihua Shen, Huazhe Tan, Huawei Li, Feng Zhang, Xiaowei Li
2018	—	`conf`	Leveraging DRAM Refresh to Protect the Memory Timing Channel of Cloud Chip Multi-processors. ITC-Asia Ying Wang, Wen Li, Huawei Li, Xiaowei Li
2018	A	`conf`	Lightweight Timing Channel Protection for Shared DRAM Controller. ITC Ying Wang, Wen Li, Huawei Li, Xiaowei Li
2018	Misc	`conf`	Modeling attacks on strong physical unclonable functions strengthened by random number and weak PUF. VTS Jing Ye, Qingli Guo, Yu Hu, Huawei Li, Xiaowei Li
2018	J	`jnl`	On Trace Buffer Reuse-Based Trigger Generation in Post-Silicon Debug. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yun Cheng, Huawei Li, Ying Wang, Haihua Shen, Bo Liu, Xiaowei Li
2018	J	`jnl`	Optimizing Memory Efficiency for Deep Convolutional Neural Network Accelerators. J. Low Power Electron. Xiaowei Li, Jiajun Li, Guihai Yan
2018	—	`conf`	PIMCH: Cooperative memory prefetching in processing-in-memory architecture. ASP-DAC Sheng Xu, Ying Wang, Yinhe Han, Xiaowei Li
2018	—	`conf`	PUF Based Pay-Per-Device Scheme for IP Protection of CNN Model. ATS Qingli Guo, Jing Ye, Yue Gong, Yu Hu, Xiaowei Li
2018	J	`jnl`	RT3D: Real-Time 3-D Vehicle Detection in LiDAR Point Cloud for Autonomous Driving. IEEE Robotics Autom. Lett. Yiming Zeng, Yu Hu, Shice Liu, Jing Ye, Yinhe Han, Xiaowei Li, Ninghui Sun
2018	—	`conf`	RiskCap: Minimizing Effort of Error Regulation for Approximate Computing. ATS Shuhao Jiang, Jiajun Li, Xin He, Guihai Yan, Xuan Zhang, Xiaowei Li
2018	A*	`conf`	See and Think: Disentangling Semantic Scene Completion. NeurIPS Shice Liu, Yu Hu, Yiming Zeng, Qiankun Tang, Beibei Jin, Yinhe Han, Xiaowei Li
2018	A	`conf`	SmartShuttle: Optimizing off-chip memory accesses for deep learning accelerators. DATE Jiajun Li, Guihai Yan, Wenyan Lu, Shuhao Jiang, Shijun Gong, Jingya Wu, Xiaowei Li
2018	J	`jnl`	Tetris: Re-architecting Convolutional Neural Network Computation for Machine Learning Accelerators. CoRR Hang Lu, Xin Wei, Ning Lin, Guihai Yan, Xiaowei Li
2018	A	`conf`	Tetris: re-architecting convolutional neural network computation for machine learning accelerators. ICCAD Hang Lu, Xin Wei, Ning Lin, Guihai Yan, Xiaowei Li
2018	—	`conf`	XORiM: A case of in-memory bit-comparator implementation and its performance implications. ASP-DAC Kaiwei Zou, Ying Wang, Huawei Li, Xiaowei Li
2017	—	`conf`	ApproxEye: Enabling approximate computation reuse for microrobotic computer vision. ASP-DAC Xin He, Guihai Yan, Faqiang Sun, Yinhe Han, Xiaowei Li
2017	—	`conf`	ApproxPIM: Exploiting realistic 3D-stacked DRAM for energy-efficient processing in-memory. ASP-DAC Yibin Tang, Ying Wang, Huawei Li, Xiaowei Li
2017	—	`conf`	BoDNoC: Providing bandwidth-on-demand interconnection for multi-granularity memory systems. ASP-DAC Shiqi Lian, Ying Wang, Yinhe Han, Xiaowei Li
2017	—	`conf`	CNN-based object detection solutions for embedded heterogeneous multicore SoCs. ASP-DAC Cheng Wang, Ying Wang, Yinhe Han, Lili Song, Zhenyu Quan, Jiajun Li, Xiaowei Li
2017	A*	`conf`	Dadu: Accelerating Inverse Kinematics for High-DOF Robots. DAC Shiqi Lian, Yinhe Han, Ying Wang, Yungang Bao, Hang Xiao, Xiaowei Li, Ninghui Sun
2017	J	`jnl`	Exploiting the Potential of Computation Reuse Through Approximate Computing. IEEE Trans. Multi Scale Comput. Syst. Xin He, Shuhao Jiang, Wenyan Lu, Guihai Yan, Yinhe Han, Xiaowei Li
2017	A	`conf`	Fault diagnosis of arbiter physical unclonable function. DATE Jing Ye, Qingli Quo, Yu Hu, Xiaowei Li
2017	A*	`conf`	FlexFlow: A Flexible Dataflow Accelerator Architecture for Convolutional Neural Networks. HPCA Wenyan Lu, Guihai Yan, Jiajun Li, Shijun Gong, Yinhe Han, Xiaowei Li
2017	Misc	`conf`	Flip-flop clustering based trace signal selection for post-silicon debug. VTS Yun Cheng, Huawei Li, Ying Wang, Yingke Gao, Bo Liu, Xiaowei Li
2017	A	`conf`	GeoCueDepth: Exploiting geometric structure cues to estimate depth from a single image. IROS Yiming Zeng, Yu Hu, Shice Liu, Qiankun Tang, Jing Ye, Xiaowei Li
2017	J	`jnl`	Going Cooler With Timing-Constrained TeSHoP: A Temperature Sensing-Based Hotspot-Driven Placement Technique for FPGAs. IEEE Trans. Very Large Scale Integr. Syst. Weina Lu, Yu Hu, Jing Ye, Xiaowei Li
2017	Misc	`conf`	Innovative practices session 10C formal verification practices in industry. VTS Huawei Li, Xiaowei Li
2017	J	`jnl`	LAPS: Layout-Aware Path Selection for Post-Silicon Timing Characterization. IEICE Trans. Inf. Syst. Yu Hu, Jing Ye, Zhiping Shi, Xiaowei Li
2017	B	`conf`	Leveraging FVT-margins in design space exploration for FFGA-based CNN accelerators. FPL Weina Lu, Wenyan Lu, Jing Ye, Yu Hu, Xiaowei Li
2017	—	`conf`	On Evaluating and Constraining Assertions Using Conflicts in Absent Scenarios. ATS Huina Chao, Huawei Li, Xiaoyu Song, Tiancheng Wang, Xiaowei Li
2017	—	`conf`	Polymorphic PUF: Exploiting reconfigurability of CPU+FPGA SoC to resist modeling attack. AsianHOST Jing Ye, Yue Gong, Yu Hu, Xiaowei Li
2017	C	`conf`	Polymorphic PUF: Exploiting reconfigurability of CPU+FPGA SoC to resist modeling attack. IOLTS Jing Ye, Yue Gong, Yu Hu, Xiaowei Li
2017	J	`jnl`	Power-Utility-Driven Write Management for MLC PCM. ACM J. Emerg. Technol. Comput. Syst. Bing Li, Yu Hu, Ying Wang, Jing Ye, Xiaowei Li
2017	J	`jnl`	PowerTrader: Enforcing Autonomous Power Management for Future Large-Scale Many-Core Processors. IEEE Trans. Multi Scale Comput. Syst. Hang Lu, Guihai Yan, Yinhe Han, Xiaowei Li
2017	A*	`conf`	Real-Time Meets Approximate Computing: An Elastic CNN Inference Accelerator with Adaptive Trade-off between QoS and QoR. DAC Ying Wang, Huawei Li, Xiaowei Li
2017	J	`jnl`	Resilience-Aware Frequency Tuning for Neural-Network-Based Approximate Computing Chips. IEEE Trans. Very Large Scale Integr. Syst. Ying Wang, Jiachao Deng, Yuntan Fang, Huawei Li, Xiaowei Li
2017	J	`jnl`	Retention-Aware DRAM Assembly and Repair for Future FGR Memories. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ying Wang, Yinhe Han, Cheng Wang, Huawei Li, Xiaowei Li
2017	J	`jnl`	STT-RAM Buffer Design for Precision-Tunable General-Purpose Neural Network Accelerator. IEEE Trans. Very Large Scale Integr. Syst. Lili Song, Ying Wang, Yinhe Han, Huawei Li, Yuanqing Cheng, Xiaowei Li
2017	—	`conf`	Selective off-loading to Memory: Task Partitioning and Mapping for PIM-enabled Heterogeneous Systems. Conf. Computing Frontiers Dawen Xu, Yi Liao, Ying Wang, Huawei Li, Xiaowei Li
2017	C	`conf`	VPUF: Voter based physical unclonable function with high reliability and modeling attack resistance. IOLTS Jing Ye, Yu Hu, Xiaowei Li
2016	—	`conf`	ACR: Enabling computation reuse for approximate computing. ASP-DAC Xin He, Guihai Yan, Yinhe Han, Xiaowei Li
2016	J	`jnl`	Abstraction-Guided Simulation Using Markov Analysis for Functional Verification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jian Wang, Huawei Li, Tao Lv, Tiancheng Wang, Xiaowei Li, Sandip Kundu
2016	J	`jnl`	An Analytical Framework for Estimating Scale-Out and Scale-Up Power Efficiency of Heterogeneous Manycores. IEEE Trans. Computers Jun Ma, Guihai Yan, Yinhe Han, Xiaowei Li
2016	A	`conf`	An accurate algorithm for computing mutation coverage in model checking. ITC Huina Chao, Huawei Li, Tiancheng Wang, Xiaowei Li, Bo Liu
2016	A*	`conf`	C-brain: a deep learning accelerator that tames the diversity of CNNs through adaptive data-level parallelization. DAC Lili Song, Ying Wang, Yinhe Han, Xin Zhao, Bosheng Liu, Xiaowei Li
2016	J	`jnl`	CoreRank: Redeeming "Sick Silicon" by Dynamically Quantifying Core-Level Healthy Condition. IEEE Trans. Computers Guihai Yan, Faqiang Sun, Huawei Li, Xiaowei Li
2016	A	`conf`	DCPUF: Placement and Routing Constraint based Dynamically Configured Physical Unclonable Function on FPGA (Abstact Only). FPGA Jing Ye, Yu Hu, Xiaowei Li
2016	A*	`conf`	DISCO: a low overhead in-network data compressor for energy-efficient chip multi-processors. DAC Ying Wang, Yinhe Han, Jun Zhou, Huawei Li, Xiaowei Li
2016	A*	`conf`	DeepBurning: automatic generation of FPGA-based learning accelerators for the neural network family. DAC Ying Wang, Jie Xu, Yinhe Han, Huawei Li, Xiaowei Li
2016	J	`jnl`	EcoUp: Towards Economical Datacenter Upgrading. IEEE Trans. Parallel Distributed Syst. Guihai Yan, Jun Ma, Yinhe Han, Xiaowei Li
2016	—	`conf`	Efficient Attack on Non-linear Current Mirror PUF with Genetic Algorithm. ATS Qingli Guo, Jing Ye, Yue Gong, Yu Hu, Xiaowei Li
2016	J	`jnl`	Enhanced Wear-Rate Leveling for PRAM Lifetime Improvement Considering Process Variation. IEEE Trans. Very Large Scale Integr. Syst. Yinhe Han, Jianbo Dong, Kaiheng Weng, Ying Wang, Xiaowei Li
2016	A	`conf`	Frequency scheduling for resilient chip multi-processors operating at Near Threshold Voltage. DATE Ying Wang, Huawei Li, Xiaowei Li
2016	J	`jnl`	Functional Test Generation for Hard-to-Reach States Using Path Constraint Solving. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yanhong Zhou, Tiancheng Wang, Huawei Li, Tao Lv, Xiaowei Li
2016	J	`jnl`	LOFT: A low-overhead fault-tolerant routing scheme for 3D NoCs. Integr. Jun Zhou, Huawei Li, Tiancheng Wang, Xiaowei Li
2016	J	`jnl`	One-round Secure Key Exchange Protocol With Strong Forward Secrecy. KSII Trans. Internet Inf. Syst. Xiaowei Li, Dengqi Yang, Benhui Chen, Yuqing Zhang
2016	A*	`conf`	POSTER: Attack on Non-Linear Physical Unclonable Function. CCS Jing Ye, Yu Hu, Xiaowei Li
2016	J	`jnl`	PSI Conscious Write Scheduling: Architectural Support for Reliable Power Delivery in 3-D Die-Stacked PCM. IEEE Trans. Very Large Scale Integr. Syst. Ying Wang, Yinhe Han, Huawei Li, Lei Zhang, Yuanqing Cheng, Xiaowei Li
2016	Misc	`conf`	Path constraint solving based test generation for observability-enhanced branch coverage. VTS Yanhong Zhou, Huawei Li, Tiancheng Wang, Bo Liu, Yingke Gao, Xiaowei Li
2016	—	`conf`	Property Coverage Analysis Based Trustworthiness Verification for Potential Threats from EDA Tools. ATS Yingxin Qiu, Huawei Li, Tiancheng Wang, Bo Liu, Yingke Gao, Xiaowei Li
2016	—	`conf`	RPUF: Physical Unclonable Function with Randomized Challenge to resist modeling attack. AsianHOST Jing Ye, Yu Hu, Xiaowei Li
2016	A	`conf`	Re-architecting the on-chip memory sub-system of machine-learning accelerator for embedded devices. ICCAD Ying Wang, Huawei Li, Xiaowei Li
2016	B	`conf`	TeSHoP: A Temperature Sensing based Hotspot-Driven Placement technique for FPGAs. FPL Weina Lu, Yu Hu, Jing Ye, Xiaowei Li
2016	J	`jnl`	VANUCA: Enabling Near-Threshold Voltage Operation in Large-Capacity Cache. IEEE Trans. Very Large Scale Integr. Syst. Ying Wang, Yinhe Han, Huawei Li, Xiaowei Li
2016	J	`jnl`	Wide Operational Range Processor Power Delivery Design for Both Super-Threshold Voltage and Near-Threshold Voltage Computing. J. Comput. Sci. Technol. Xin He, Guihai Yan, Yinhe Han, Xiaowei Li
2015	—	`conf`	A Lightweight Timing Channel Protection for Shared Memory Controllers. ATS Guopei Liu, Ying Wang, Sen Li, Huawei Li, Xiaowei Li
2015	—	`conf`	A Similarity Based Circuit Partitioning and Trimming Method to Defend against Hardware Trojans. ISVLSI Yun Cheng, Ying Wang, Huawei Li, Xiaowei Li
2015	C	`conf`	A case of precision-tunable STT-RAM memory design for approximate neural network. ISCAS Ying Wang, Lili Song, Yinhe Han, Yuanqing Cheng, Huawei Li, Xiaowei Li
2015	J	`jnl`	A privacy preserving authentication scheme for roaming services in global mobility networks. Secur. Commun. Networks Gefei Zhang, Dan Fan, Yuqing Zhang, Xiaowei Li, Xuefeng Liu
2015	J	`jnl`	A signal degradation reduction method for memristor ratioed logic (MRL) gates. IEICE Electron. Express Bosheng Liu, Ying Wang, Zhiqiang You, Yinhe Han, Xiaowei Li
2015	J	`jnl`	An on-chip frequency programmable test clock generation and application method for small delay defect detection. Integr. Songwei Pei, Huawei Li, Song Jin, Jun Liu, Xiaowei Li
2015	J	`jnl`	Data Remapping for Static NUCA in Degradable Chip Multiprocessors. IEEE Trans. Very Large Scale Integr. Syst. Ying Wang, Lei Zhang, Yinhe Han, Huawei Li, Xiaowei Li
2015	J	`jnl`	Diagnosis and Layout Aware (DLA) Scan Chain Stitching. IEEE Trans. Very Large Scale Integr. Syst. Jing Ye, Yu Huang, Yu Hu, Wu-Tung Cheng, Ruifeng Guo, Liyang Lai, Ting-Pu Tai, Xiaowei Li, Wei-pin Changchien, Daw-Ming Lee, Ji-Jan Chen, Sandeep C. Eruvathi, Kartik K. Kumara, Charles C. C. Liu, Sam Pan
2015	J	`jnl`	Economizing TSV Resources in 3-D Network-on-Chip Design. IEEE Trans. Very Large Scale Integr. Syst. Ying Wang, Yinhe Han, Lei Zhang, Binzhang Fu, Cheng Liu, Huawei Li, Xiaowei Li
2015	A*	`conf`	Impact assessment of net metering on smart home cyberattack detection. DAC Yang Liu, Shiyan Hu, Jie Wu, Yiyu Shi, Yier Jin, Yu Hu, Xiaowei Li
2015	C	`conf`	OPUF: Obfuscation logic based physical unclonable function. IOLTS Jing Ye, Yu Hu, Xiaowei Li
2015	A*	`conf`	ProPRAM: exploiting the transparent logic resources in non-volatile memory for near data computing. DAC Ying Wang, Yinhe Han, Lei Zhang, Huawei Li, Xiaowei Li
2015	J	`jnl`	RISO: Enforce Noninterfered Performance With Relaxed Network-on-Chip Isolation in Many-Core Cloud Processors. IEEE Trans. Very Large Scale Integr. Syst. Hang Lu, Binzhang Fu, Ying Wang, Yinhe Han, Guihai Yan, Xiaowei Li
2015	A	`conf`	Retraining-based timing error mitigation for hardware neural networks. DATE Jiachao Deng, Yuntan Fang, Zidong Du, Ying Wang, Huawei Li, Olivier Temam, Paolo Ienne, David Novo, Xiaowei Li, Yunji Chen, Chengyong Wu
2015	—	`conf`	ShuttleNoC: Boosting on-chip communication efficiency by enabling localized power adaptation. ASP-DAC Hang Lu, Guihai Yan, Yinhe Han, Ying Wang, Xiaowei Li
2015	—	`conf`	TURO: A lightweight turn-guided routing scheme for 3D NoCs. COOL Chips Jun Zhou, Huawei Li, Tiancheng Wang, Ying Wang, Xiaowei Li
2015	—	`conf`	TWiN: A Turn-Guided Reliable Routing Scheme for Wireless 3D NoCs. ATS Jun Zhou, Huawei Li, Tiancheng Wang, Sen Li, Ying Wang, Xiaowei Li
2014	—	`conf`	A novel abstraction-guided simulation approach using posterior probabilities for verification. VLSI-DAT Jian Wang, Huawei Li, Xiaowei Li
2014	—	`conf`	Amphisbaena: Modeling two orthogonal ways to hunt on heterogeneous many-cores. ASP-DAC Jun Ma, Guihai Yan, Yinhe Han, Xiaowei Li
2014	—	`conf`	An On-Line Timing Error Detection Method for Silicon Debug. ATS Yun Cheng, Huawei Li, Xiaowei Li
2014	A	`conf`	Data-aware DRAM refresh to squeeze the margin of retention time in hybrid memory cube. ICCAD Yinhe Han, Ying Wang, Huawei Li, Xiaowei Li
2014	J	`jnl`	Diagnose Failures Caused by Multiple Locations at a Time. IEEE Trans. Very Large Scale Integr. Syst. Jing Ye, Yu Hu, Xiaowei Li, Wu-Tung Cheng, Yu Huang, Huaxing Tang
2014	A	`conf`	Functional test generation guided by steady-state probabilities of abstract design. DATE Jian Wang, Huawei Li, Tao Lv, Tiancheng Wang, Xiaowei Li
2014	—	`conf`	HARS: A High-Performance Reliable Routing Scheme for 3D NoCs. ISVLSI Jun Zhou, Huawei Li, Yuntan Fang, Tiancheng Wang, Yuanqing Cheng, Xiaowei Li
2014	J	`jnl`	Lifetime Enhancement Techniques for PCM-Based Image Buffer in Multimedia Applications. IEEE Trans. Very Large Scale Integr. Syst. Yuntan Fang, Huawei Li, Xiaowei Li
2014	—	`conf`	On-Chip Delay Sensor for Environments with Large Temperature Fluctuations. ATS Jibing Qiu, Guihai Yan, Xiaowei Li
2014	J	`jnl`	Orchestrator: Guarding Against Voltage Emergencies in Multithreaded Applications. IEEE Trans. Very Large Scale Integr. Syst. Xing Hu, Guihai Yan, Yu Hu, Xiaowei Li
2014	A	`conf`	Partial-SET: Write speedup of PCM main memory. DATE Bing Li, Shuchang Shan, Yu Hu, Xiaowei Li
2014	J	`jnl`	Reliability-Oriented Placement and Routing Algorithm for SRAM-Based FPGAs. IEEE Trans. Very Large Scale Integr. Syst. Keheng Huang, Yu Hu, Xiaowei Li
2014	—	`conf`	Short-SET: An energy-efficient write scheme for MLC PCM. NVMSA Bing Li, Yu Hu, Xiaowei Li
2014	J	`jnl`	SmartCap: Using Machine Learning for Power Adaptation of Smartphone's Application Processor. ACM Trans. Design Autom. Electr. Syst. Xueliang Li, Guihai Yan, Yinhe Han, Xiaowei Li
2014	A	`conf`	SuperRange: Wide operational range power delivery design for both STV and NTV computing. DATE Xin He, Guihai Yan, Yinhe Han, Xiaowei Li
2014	J	`jnl`	Test-Quality Optimization for Variable $n$ -Detections of Transition Faults. IEEE Trans. Very Large Scale Integr. Syst. Dawen Xu, Huawei Li, Amirali Ghofrani, Kwang-Ting Cheng, Yinhe Han, Xiaowei Li
2014	J	`jnl`	ZoneDefense: A Fault-Tolerant Routing for 2-D Meshes Without Virtual Channels. IEEE Trans. Very Large Scale Integr. Syst. Binzhang Fu, Yinhe Han, Huawei Li, Xiaowei Li
2013	J	`jnl`	A Lightweight Three-Party Privacy-preserving Authentication Key Exchange Protocol Using Smart Card. KSII Trans. Internet Inf. Syst. Xiaowei Li, Yuqing Zhang, Xuefeng Liu, Jin Cao
2013	J	`jnl`	A New Roaming Authentication Framework For Wireless Communication. KSII Trans. Internet Inf. Syst. Xiaowei Li, Yuqing Zhang, Xuefeng Liu, Jin Cao, Qianqian Zhao
2013	J	`jnl`	A new certificateless authenticated key agreement protocol for SIP with different KGCs. Secur. Commun. Networks Xiaowei Li, Yuqing Zhang, Geifei Zhang
2013	J	`jnl`	A simple and robust anonymous two-factor authenticated key exchange protocol. Secur. Commun. Networks Xiaowei Li, Yuqing Zhang
2013	J	`jnl`	Automatic Test Program Generation Using Executing-Trace-Based Constraint Extraction for Embedded Processors. IEEE Trans. Very Large Scale Integr. Syst. Ying Zhang, Huawei Li, Xiaowei Li
2013	A	`conf`	Capturing post-silicon variation by layout-aware path-delay testing. DATE Xiaolin Zhang, Jing Ye, Yu Hu, Xiaowei Li
2013	A	`conf`	Diagnosis and Layout Aware (DLA) scan chain stitching. ITC Jing Ye, Yu Huang, Yu Hu, Wu-Tung Cheng, Ruifeng Guo, Liyang Lai, Ting-Pu Tai, Xiaowei Li, Wei-pin Changchien, Daw-Ming Lee, Ji-Jan Chen, Sandeep C. Eruvathi, Kartik K. Kumara, Charles C. C. Liu, Sam Pan
2013	C	`conf`	Enabling Near-Threshold Voltage(NTV) operation in Multi-VDD cache for power reduction. ISCAS Yinhe Han, Ying Wang, Huawei Li, Xiaowei Li
2013	C	`conf`	HHC: Hierarchical hardware checkpointing to accelerate fault recovery for SRAM-based FPGAs. IOLTS Enshan Yang, Keheng Huang, Yu Hu, Xiaowei Li, Jian Gong, Hongjin Liu, Bo Liu
2013	—	`conf`	On predicting NBTI-induced circuit aging by isolating leakage change. ISQED Yinhe Han, Song Jin, Jibing Qiu, Qiang Xu, Xiaowei Li
2013	A	`conf`	Orchestrator: a low-cost solution to reduce voltage emergencies for multi-threaded applications. DATE Xing Hu, Guihai Yan, Yu Hu, Xiaowei Li
2013	—	`conf`	Path Constraint Solving Based Test Generation for Hard-to-Reach States. Asian Test Symposium Yanhong Zhou, Tiancheng Wang, Tao Lv, Huawei Li, Xiaowei Li
2013	A*	`conf`	RISO: relaxed network-on-chip isolation for cloud processors. DAC Hang Lu, Guihai Yan, Yinhe Han, Binzhang Fu, Xiaowei Li
2013	Misc	`conf`	RSAK: Random stream attack for phase change memory in video applications. VTS Yuntan Fang, Huawei Li, Xiaowei Li
2013	J	`jnl`	RevivePath: Resilient Network-on-Chip Design Through Data Path Salvaging of Router. J. Comput. Sci. Technol. Yinhe Han, Cheng Liu, Hang Lu, Wen-Bo Li, Lei Zhang, Xiaowei Li
2013	A	`conf`	SmartCap: user experience-oriented power adaptation for smartphone's application processor. DATE Xueliang Li, Guihai Yan, Yinhe Han, Xiaowei Li
2013	J	`jnl`	TSV Minimization for Circuit - Partitioned 3D SoC Test Wrapper Design. J. Comput. Sci. Technol. Yuanqing Cheng, Lei Zhang, Yinhe Han, Xiaowei Li
2013	J	`jnl`	Test Path Selection for Capturing Delay Failures Under Statistical Timing Model. IEEE Trans. Very Large Scale Integr. Syst. Zijian He, Tao Lv, Huawei Li, Xiaowei Li
2013	J	`jnl`	Thermal-Constrained Task Allocation for Interconnect Energy Reduction in 3-D Homogeneous MPSoCs. IEEE Trans. Very Large Scale Integr. Syst. Yuanqing Cheng, Lei Zhang, Yinhe Han, Xiaowei Li
2013	C	`conf`	Tolerating Noise in MLC PCM with Multi-Bit Error Correction Code. PRDC Bing Li, Shuchang Shan, Yu Hu, Xiaowei Li
2013	J	`jnl`	Unified Capture Scheme for Small Delay Defect Detection and Aging Prediction. IEEE Trans. Very Large Scale Integr. Syst. Song Jin, Yinhe Han, Huawei Li, Xiaowei Li
2012	J	`jnl`	A High-Precision On-Chip Path Delay Measurement Architecture. IEEE Trans. Very Large Scale Integr. Syst. Songwei Pei, Huawei Li, Xiaowei Li
2012	A	`conf`	A clustering-based scheme for concurrent trace in debugging NoC-based multicore systems. DATE Jianliang Gao, Jianxin Wang, Yinhe Han, Lei Zhang, Xiaowei Li
2012	B	`conf`	A lightweight roaming authentication protocol for anonymous wireless communication. GLOBECOM Xiaowei Li, Yuqing Zhang, Xuefeng Liu, Jin Cao, Qianqian Zhao
2012	A*	`conf`	AgileRegulator: A hybrid voltage regulator scheme redeeming dark silicon for power efficiency in a multicore architecture. HPCA Guihai Yan, Yingmin Li, Yinhe Han, Xiaowei Li, Minyi Guo, Xiaoyao Liang
2012	J	`jnl`	An energy-efficient link quality monitoring scheme for wireless networks. Wirel. Commun. Mob. Comput. Hongsong Zhu, Xinrong Li, Yongjun Xu, Xiaowei Li, Yan Liu
2012	J	`jnl`	Flip-Flop Selection for Partial Enhanced Scan to Reduce Transition Test Data Volume. IEEE Trans. Very Large Scale Integr. Syst. Songwei Pei, Huawei Li, Xiaowei Li
2012	—	`conf`	Hungarian algorithm based virtualization to maintain application timing similarity for defect-tolerant NoC. ASP-DAC Ke Yue, Frank Lockom, Zheng Li, Soumia Ghalim, Shangping Ren, Lei Zhang, Xiaowei Li
2012	J	`jnl`	IVF: Characterizing the Vulnerability of Microprocessor Structures to Intermittent Faults. IEEE Trans. Very Large Scale Integr. Syst. Songjun Pan, Yu Hu, Xiaowei Li
2012	—	`conf`	In-Field Testing of NAND Flash Storage: Why and How? Asian Test Symposium Yu Hu, Xinli Gu, Xiaowei Li
2012	A	`conf`	Off-path leakage power aware routing for SRAM-based FPGAs. DATE Keheng Huang, Yu Hu, Xiaowei Li, Bo Liu, Hongjin Liu, Jian Gong
2012	—	`conf`	SoftPCM: Enhancing Energy Efficiency and Lifetime of Phase Change Memory in Video Applications via Approximate Write. Asian Test Symposium Yuntan Fang, Huawei Li, Xiaowei Li
2012	—	`conf`	Statistical SDFC: A metric for evaluating test quality of small delay faults. VLSI-DAT Xuefeng Zhu, Huawei Li, Xiaowei Li
2012	J	`jnl`	Testable Path Selection and Grouping for Faster Than At-Speed Testing. IEEE Trans. Very Large Scale Integr. Syst. Xiang Fu, Huawei Li, Xiaowei Li
2011	—	`conf`	A Fault Criticality Evaluation Framework of Digital Systems for Error Tolerant Video Applications. Asian Test Symposium Yuntan Fang, Huawei Li, Xiaowei Li
2011	J	`jnl`	A Loss Inference Algorithm for Wireless Sensor Networks to Improve Data Reliability of Digital Ecosystems. IEEE Trans. Ind. Electron. Yu Yang, Yongjun Xu, Xiaowei Li, Canfeng Chen
2011	J	`jnl`	A New Multiple-Round Dimension-Order Routing for Networks-on-Chip. IEICE Trans. Inf. Syst. Binzhang Fu, Yinhe Han, Huawei Li, Xiaowei Li
2011	J	`jnl`	A Security Mechanism For RFID With Dependable Proxy. Intell. Autom. Soft Comput. Jun Zhou, Yongjun Xu, Xiaowei Li
2011	A	`conf`	A cost-effective substantial-impact-filter based method to tolerate voltage emergencies. DATE Songjun Pan, Yu Hu, Xing Hu, Xiaowei Li
2011	—	`conf`	A greedy approach to tolerate defect cores for multimedia applications. ESTIMedia Ke Yue, Soumia Ghalim, Zheng Li, Frank Lockom, Shangping Ren, Lei Zhang, Xiaowei Li
2011	—	`conf`	A resilient on-chip router design through data path salvaging. ASP-DAC Cheng Liu, Lei Zhang, Yinhe Han, Xiaowei Li
2011	Misc	`conf`	A unified test architecture for on-line and off-line delay fault detections. VTS Songwei Pei, Huawei Li, Xiaowei Li
2011	A*	`conf`	An abacus turn model for time/space-efficient reconfigurable routing. ISCA Binzhang Fu, Yinhe Han, Jun Ma, Huawei Li, Xiaowei Li
2011	J	`jnl`	Capture-power-aware test data compression using selective encoding. Integr. Jia Li, Xiao Liu, Yubin Zhang, Yu Hu, Xiaowei Li, Qiang Xu
2011	A	`conf`	Cross-layer optimized placement and routing for FPGA soft error mitigation. DATE Keheng Huang, Yu Hu, Xiaowei Li
2011	A	`conf`	Eliminating data invalidation in debugging multiple-clock chips. DATE Jianliang Gao, Yinhe Han, Xiaowei Li
2011	—	`conf`	Exploiting Free LUT Entries to Mitigate Soft Errors in SRAM-based FPGAs. Asian Test Symposium Keheng Huang, Yu Hu, Xiaowei Li, Gengxin Hua, Hongjin Liu, Bo Liu
2011	A	`conf`	Flex memory: Exploiting and managing abundant off-chip optical bandwidth. DATE Ying Wang, Lei Zhang, Yinhe Han, Huawei Li, Xiaowei Li
2011	J	`jnl`	MicroFix: Using timing interpolation and delay sensors for power reduction. ACM Trans. Design Autom. Electr. Syst. Guihai Yan, Yinhe Han, Hui Liu, Xiaoyao Liang, Xiaowei Li
2011	J	`jnl`	New Methodologies for Parallel Architecture. J. Comput. Sci. Technol. Dong-Rui Fan, Xiaowei Li, Guo-Jie Li
2011	J	`jnl`	Nonidentical Linear Pulse-Coupled Oscillators Model With Application to Time Synchronization in Wireless Sensor Networks. IEEE Trans. Ind. Electron. Zhulin An, Hongsong Zhu, Xinrong Li, Chaonong Xu, Yongjun Xu, Xiaowei Li
2011	A	`conf`	On diagnosis of multiple faults using compacted responses. DATE Jing Ye, Yu Hu, Xiaowei Li
2011	A	`conf`	Online timing variation tolerance for digital integrated circuits. ITC Guihai Yan, Xiaowei Li
2011	J	`jnl`	Oware: Operand width Aware Redundant Execution for Whole-Processor Error Detection. Intell. Autom. Soft Comput. Yu Hu, Zhongliang Chen, Xiaowei Li
2011	J	`jnl`	Path Delay Test Generation Toward Activation of Worst Case Coupling Effects. IEEE Trans. Very Large Scale Integr. Syst. Minjin Zhang, Huawei Li, Xiaowei Li
2011	J	`jnl`	ReviveNet: A Self-Adaptive Architecture for Improving Lifetime Reliability via Localized Timing Adaptation. IEEE Trans. Computers Guihai Yan, Yinhe Han, Xiaowei Li
2011	J	`jnl`	SVFD: A Versatile Online Fault Detection Scheme via Checking of Stability Violation. IEEE Trans. Very Large Scale Integr. Syst. Guihai Yan, Yinhe Han, Xiaowei Li
2011	J	`jnl`	Scan chain design for shift power reduction in scan-based testing. Sci. China Inf. Sci. Jia Li, Yu Hu, Xiaowei Li
2011	J	`jnl`	Selected Transition Time Adjustment for Tolerating Crosstalk Effects on Network-on-Chip Interconnects. IEEE Trans. Very Large Scale Integr. Syst. Ying Zhang, Huawei Li, Yinghua Min, Xiaowei Li
2011	J	`jnl`	Statistical lifetime reliability optimization considering joint effect of process variation and aging. Integr. Song Jin, Yinhe Han, Huawei Li, Xiaowei Li
2011	A	`conf`	Transparent dynamic binding with fault-tolerant cache coherence protocol for chip multiprocessors. DSN Shuchang Shan, Yu Hu, Xiaowei Li
2011	—	`conf`	Vertical interconnects squeezing in symmetric 3D mesh Network-on-Chip. ASP-DAC Cheng Liu, Lei Zhang, Yinhe Han, Xiaowei Li
2011	A*	`conf`	Wear rate leveling: lifetime enhancement of PRAM with endurance variation. DAC Jianbo Dong, Lei Zhang, Yinhe Han, Ying Wang, Xiaowei Li
2011	—	`conf`	Wrapper Chain Design for Testing TSVs Minimization in Circuit-Partitioned 3D SoC. Asian Test Symposium Yuanqing Cheng, Lei Zhang, Yinhe Han, Jun Liu, Xiaowei Li
2010	J	`jnl`	A Novel Post-Silicon Debug Mechanism Based on Suspect Window. IEICE Trans. Inf. Syst. Jianliang Gao, Yinhe Han, Xiaowei Li
2010	A	`conf`	Accelerating Lightpath setup via broadcasting in binary-tree waveguide in Optical NoCs. DATE Binzhang Fu, Yinhe Han, Huawei Li, Xiaowei Li
2010	C	`conf`	Address Remapping for Static NUCA in NoC-Based Degradable Chip-Multiprocessors. PRDC Ying Wang, Lei Zhang, Yinhe Han, Huawei Li, Xiaowei Li
2010	—	`conf`	An Efficient Algorithm for Finding a Universal Set of Testable Long Paths. Asian Test Symposium Zijian He, Tao Lv, Huawei Li, Xiaowei Li
2010	A	`conf`	An abstraction-guided simulation approach using Markov models for microprocessor verification. DATE Tao Zhang, Tao Lv, Xiaowei Li
2010	A	`conf`	An on-chip clock generation scheme for faster-than-at-speed delay testing. DATE Songwei Pei, Huawei Li, Xiaowei Li
2010	A	`conf`	Diagnosis of multiple arbitrary faults with mask and reinforcement effect. DATE Jing Ye, Yu Hu, Xiaowei Li
2010	J	`jnl`	Extended Selective Encoding of Scan Slices for Reducing Test Data and Test Power. IEICE Trans. Inf. Syst. Jun Liu, Yinhe Han, Xiaowei Li
2010	Misc	`conf`	Fast path selection for testing of small delay defects considering path correlations. VTS Zijian He, Tao Lv, Huawei Li, Xiaowei Li
2010	—	`conf`	Graph partition based path selection for testing of small delay defects. ASP-DAC Zijian He, Tao Lv, Huawei Li, Xiaowei Li
2010	A	`conf`	IVF: Characterizing the vulnerability of microprocessor structures to intermittent faults. DATE Songjun Pan, Yu Hu, Xiaowei Li
2010	Misc	`conf`	Improving complex distributed software system availability through information hiding. SAC Li Wang, Yair Leiferman, Shangping Ren, Kevin A. Kwiat, Xiaowei Li
2010	A*	`conf`	Leveraging the core-level complementary effects of PVT variations to reduce timing emergencies in multi-core processors. ISCA Guihai Yan, Xiaoyao Liang, Yinhe Han, Xiaowei Li
2010	J	`jnl`	Linear Pulse-Coupled Oscillators Model¬ - A New Approach for Time Synchronization in Wireless Sensor Networks. Wirel. Sens. Netw. Zhulin An, Hongsong Zhu, Meilin Zhang, Chaonong Xu, Yongjun Xu, Xiaowei Li
2010	—	`conf`	On Selection of Testable Paths with Specified Lengths for Faster-Than-At-Speed Testing. Asian Test Symposium Xiang Fu, Huawei Li, Xiaowei Li
2010	A	`conf`	On generation of a universal path candidate set containing testable long paths. ITC Zijian He, Tao Lv, Huawei Li, Xiaowei Li
2010	—	`conf`	P^(2)CLRAF: An Pre- and Post-Silicon Cooperated Circuit Lifetime Reliability Analysis Framework. Asian Test Symposium Song Jin, Yinhe Han, Huawei Li, Xiaowei Li
2010	J	`jnl`	Passive Loss Inference in Wireless Sensor Networks Using EM Algorithm. Wirel. Sens. Netw. Yu Yang, Zhulin An, Yongjun Xu, Xiaowei Li, Canfeng Chen
2010	J	`jnl`	Performance-asymmetry-aware scheduling for Chip Multiprocessors with static core coupling. J. Syst. Archit. Jianbo Dong, Lei Zhang, Yinhe Han, Guihai Yan, Xiaowei Li
2010	A	`conf`	Performance-asymmetry-aware topology virtualization for defect-tolerant NoC-based many-core processors. DATE Lei Zhang, Yue Yu, Jianbo Dong, Yinhe Han, Shangping Ren, Xiaowei Li
2010	—	`conf`	Software-Based Self-Testing of Processors Using Expanded Instructions. Asian Test Symposium Ying Zhang, Huawei Li, Xiaowei Li
2010	—	`conf`	Substantial Fault Pair At-a-Time (SFPAT): An Automatic Diagnostic Pattern Generation Method. Asian Test Symposium Jing Ye, Xiaolin Zhang, Yu Hu, Xiaowei Li
2010	J	`jnl`	Testable Critical Path Selection Considering Process Variation. IEICE Trans. Inf. Syst. Xiang Fu, Huawei Li, Xiaowei Li
2010	J	`jnl`	X-Filling for Simultaneous Shift- and Capture-Power Reduction in At-Speed Scan-Based Testing. IEEE Trans. Very Large Scale Integr. Syst. Jia Li, Qiang Xu, Yu Hu, Xiaowei Li
2010	A	`conf`	nGFSIM : A GPU-based fault simulator for 1-to-n detection and its applications. ITC Huawei Li, Dawen Xu, Yinhe Han, Kwang-Ting Cheng, Xiaowei Li
2009	—	`conf`	A Low Overhead On-Chip Path Delay Measurement Circuit. Asian Test Symposium Songwei Pei, Huawei Li, Xiaowei Li
2009	C	`conf`	A New Multiple-Round DOR Routing for 2D Network-on-Chip Meshes. PRDC Binzhang Fu, Yinhe Han, Huawei Li, Xiaowei Li
2009	Misc	`conf`	A New Post-Silicon Debug Approach Based on Suspect Window. VTS Jianliang Gao, Yinhe Han, Xiaowei Li
2009	B	`conf`	A sensor network performance inference algorithm based on passive measurement. WCNC Yu Yang, Yongjun Xu, Xiaowei Li
2009	A	`conf`	A unified online Fault Detection scheme via checking of Stability Violation. DATE Guihai Yan, Yinhe Han, Xiaowei Li
2009	Misc	`conf`	Automatic Selection of Internal Observation Signals for Design Verification. VTS Tao Lv, Huawei Li, Xiaowei Li
2009	—	`conf`	Extended Selective Encoding of Scan Slices for Reducing Test Data and Test Power. Asian Test Symposium Jun Liu, Yinhe Han, Xiaowei Li
2009	C	`conf`	Flip-Flop Selection for Transition Test Pattern Reduction Using Partial Enhanced Scan. PRDC Songwei Pei, Huawei Li, Xiaowei Li
2009	C	`conf`	Impact of Hazards on Pattern Selection for Small Delay Defects. PRDC Jie Wang, Huawei Li, Yinghua Min, Xiaowei Li, Huaguo Liang
2009	—	`conf`	M-IVC: Using Multiple Input Vectors to Minimize Aging-Induced Delay. Asian Test Symposium Song Jin, Yinhe Han, Lei Zhang, Huawei Li, Xiaowei Li, Guihai Yan
2009	A	`conf`	MicroFix: exploiting path-grained timing adaptability for improving power-performance efficiency. ISLPED Guihai Yan, Yinhe Han, Hui Liu, Xiaoyao Liang, Xiaowei Li
2009	J	`jnl`	On Topology Reconfiguration for Defect-Tolerant NoC-Based Homogeneous Manycore Systems. IEEE Trans. Very Large Scale Integr. Syst. Lei Zhang, Yinhe Han, Qiang Xu, Xiaowei Li, Huawei Li
2009	C	`conf`	Online Computing and Predicting Architectural Vulnerability Factor of Microprocessor Structures. PRDC Songjun Pan, Yu Hu, Xiaowei Li
2009	J	`jnl`	Preface. J. Comput. Sci. Technol. Fei-Yue Wang, Ninghui Sun, Wenji Mao, Xiaowei Li
2009	J	`jnl`	Selected Crosstalk Avoidance Code for Reliable Network-on-Chip. J. Comput. Sci. Technol. Ying Zhang, Huawei Li, Xiaowei Li
2009	C	`conf`	Variation-Aware Scheduling for Chip Multiprocessors with Thread Level Redundancy. PRDC Jianbo Dong, Lei Zhang, Yinhe Han, Guihai Yan, Xiaowei Li
2008	—	`conf`	A Case Study on At-Speed Testing for a Gigahertz Microprocessor. DELTA Da Wang, Rui Li, Yu Hu, Huawei Li, Xiaowei Li
2008	—	`conf`	A Scan-Based Delay Test Method for Reduction of Overtesting. DELTA Hui Liu, Huawei Li, Yu Hu, Xiaowei Li
2008	—	`conf`	A design- for-diagnosis technique for diagnosing both scan chain faults and combinational circuit faults. ASP-DAC Fei Wang, Yu Hu, Huawei Li, Xiaowei Li
2008	—	`conf`	Adaptive Diagnostic Pattern Generation for Scan Chains. DELTA Fei Wang, Yu Hu, Xiaowei Li
2008	J	`jnl`	Analysis of Forwarding Mechanisms on Fine-Grain Gradient Sinking Model in WSN. J. Signal Process. Syst. Limin Sun, Hongsong Zhu, Bin Duan, Xiaowei Li, Yi Sun
2008	J	`jnl`	BAT: Performance-Driven Crosstalk Mitigation Based on Bus-Grouping Asynchronous Transmission. IEICE Trans. Electron. Guihai Yan, Yinhe Han, Xiaowei Li, Hui Liu
2008	—	`conf`	Channel Width Utilization Improvement in Testing NoC-Based Systems for Test Time Reduction. DELTA Jia Li, Qiang Xu, Yu Hu, Xiaowei Li
2008	Misc	`conf`	Codeword Selection for Crosstalk Avoidance and Error Correction on Interconnects. VTS Ying Zhang, Huawei Li, Xiaowei Li, Yu Hu
2008	A	`conf`	Defect Tolerance in Homogeneous Manycore Processors Using Core-Level Redundancy with Unified Topology. DATE Lei Zhang, Yinhe Han, Qiang Xu, Xiaowei Li
2008	J	`jnl`	Design-for-Testability Features and Test Implementation of a Giga Hertz General Purpose Microprocessor. J. Comput. Sci. Technol. Da Wang, Yu Hu, Huawei Li, Xiaowei Li
2008	A	`conf`	Deterministic Diagnostic Pattern Generation (DDPG) for Compound Defects. ITC Fei Wang, Yu Hu, Huawei Li, Xiaowei Li, Jing Ye, Yu Huang
2008	A	`conf`	Diagnosis of Mask-Effect Multiple Timing Faults in Scan Chains. ITC Jing Ye, Fei Wang, Yu Hu, Xiaowei Li
2008	Misc	`conf`	Multiple Coupling Effects Oriented Path Delay Test Generation. VTS Minjin Zhang, Huawei Li, Xiaowei Li
2008	—	`conf`	Observation Point Oriented Deterministic Diagnosis Pattern Generation (DDPG) for Chain Diagnosis. ATS Fei Wang, Yu Hu, Yu Huang, Jing Ye, Xiaowei Li
2008	A	`conf`	On capture power-aware test data compression for scan-based testing. ICCAD Jia Li, Xiao Liu, Yubin Zhang, Yu Hu, Xiaowei Li, Qiang Xu
2008	—	`conf`	On reducing both shift and capture power for scan-based testing. ASP-DAC Jia Li, Qiang Xu, Yu Hu, Xiaowei Li
2008	—	`conf`	Reliable Network-on-Chip Router for Crosstalk and Soft Error Tolerance. ATS Ying Zhang, Huawei Li, Xiaowei Li
2008	—	`conf`	Robust test generation for power supply noise induced path delay faults. ASP-DAC Xiang Fu, Huawei Li, Yu Hu, Xiaowei Li
2008	—	`conf`	Static Crosstalk Noise Analysis with Transition Map. DELTA Minjin Zhang, Huawei Li, Xiaowei Li
2008	A	`conf`	iFill: An Impact-Oriented X-Filling Method for Shift- and Capture-Power Reduction in At-Speed Scan-Based Testing. DATE Jia Li, Qiang Xu, Yu Hu, Xiaowei Li
2007	—	`conf`	A Routing Algorithm for Random Error Tolerance in Network-on-Chip. HCI (4) Lei Zhang, Huawei Li, Xiaowei Li
2007	—	`conf`	Bug analysis and corresponding error models in real designs. HLDVT Tao Lv, Tong Xu, Yang Zhao, Huawei Li, Xiaowei Li
2007	J	`jnl`	Data Mining via Minimal Spanning Tree Clustering for Prolonging Lifetime of Wireless Sensor Networks. Int. J. Inf. Technol. Decis. Mak. Guangyan Huang, Xiaowei Li, Jing He, Xin Li
2007	J	`jnl`	Embedded Test Decompressor to Reduce the Required Channels and Vector Memory of Tester for Complex Processor Circuit. IEEE Trans. Very Large Scale Integr. Syst. Yinhe Han, Yu Hu, Xiaowei Li, Huawei Li, Anshuman Chandra
2007	—	`conf`	Frequency Analysis Method for Propagation of Transient Errors in Combinational Logic. ATS Shaohua Lei, Yinhe Han, Xiaowei Li
2007	J	`jnl`	Leakage Current Optimization Techniques During Test Based on Don't Care Bits Assignment. J. Comput. Sci. Technol. Wei Wang, Yu Hu, Yinhe Han, Xiaowei Li, You-Sheng Zhang
2007	—	`conf`	Test Generation for Crosstalk Glitches Considering Multiple Coupling Effects. ATS Minjin Zhang, Xiaowei Li
2007	A	`conf`	The design-for-testability features of a general purpose microprocessor. ITC Da Wang, Xiaoxin Fan, Xiang Fu, Hui Liu, Ke Wen, Rui Li, Huawei Li, Yu Hu, Xiaowei Li
2006	C	`conf`	A Lightweight Scheme for Trust Relationship Establishment in Ubiquitous Sensor Networks. CIT Lei Xie, Yongjun Xu, Xiaowei Li, Yuefei Zhu
2006	—	`conf`	A Novel Localization Scheme Based on RSS Data for Wireless Sensor Networks. APWeb Workshops Hongyang Chen, Ping Deng, Yongjun Xu, Xiaowei Li
2006	—	`conf`	A Scan Chain Adjustment Technology for Test Power Reduction. ATS Jia Li, Yu Hu, Xiaowei Li
2006	—	`conf`	An Observability Branch Coverage Metric Based on Dynamic Factored Use-Define Chains. ATS Tao Lv, Ling-Yi Liu, Yang Zhao, Huawei Li, Xiaowei Li
2006	C	`conf`	An on-chip combinational decompressor for reducing test data volume. ISCAS Jie Don, Yu Hu, Yinhe Han, Xiaowei Li
2006	Misc	`conf`	Clustering Versus Evenly Distributing Energy Dissipation in Wireless Sensor Routing for Prolonging Network Lifetime. International Conference on Computational Science (2) Guangyan Huang, Xiaowei Li, Jing He
2006	J	`jnl`	Compression/Scan Co-design for Reducing Test Data Volume, Scan-in Power Dissipation, and Test Application Time. IEICE Trans. Inf. Syst. Yu Hu, Yinhe Han, Xiaowei Li, Huawei Li, Xiaoqing Wen
2006	J	`jnl`	Embedded test resource for SoC to reduce required tester channels based on advanced convolutional codes. IEEE Trans. Instrum. Meas. Yinhe Han, Xiaowei Li, Huawei Li, Anshuman Chandra
2006	B	`conf`	Fast Packet Classification using Group Bit Vector. GLOBECOM Tong Liu, Huawei Li, Xiaowei Li, Yinhe Han
2006	J	`jnl`	Observability Statement Coverage Based on Dynamic Factored Use-Definition Chains for Functional Verification. J. Electron. Test. Tao Lv, Jianping Fan, Xiaowei Li, Ling-Yi Liu
2006	J	`jnl`	Response compaction for system-on-a-chip based on advanced convolutional codes. Sci. China Ser. F Inf. Sci. Yinhe Han, Huawei Li, Xiaowei Li, Anshuman Chandra
2006	Misc	`conf`	Robust Test Generation for Precise Crosstalk-induced Path Delay Faults. VTS Huawei Li, Pei-Fu Shen, Xiaowei Li
2006	—	`conf`	Test data compression based on clustered random access scan. ATS Yu Hu, Cheng Li, Jia Li, Yinhe Han, Xiaowei Li, Wei Wang, Huawei Li, Laung-Terng Wang, Xiaoqing Wen
2005	—	`conf`	A State Machine for Detecting C/C++ Memory Faults. Asian Test Symposium Guangyan Huang, Guangmei Zhang, Xiaowei Li, Yunzhan Gong
2005	J	`jnl`	An Efficient Evaluation and Vector Generation Method for Observability-Enhanced Statement Coverage. J. Comput. Sci. Technol. Wei Lu, Xiu-Tao Yang, Tao Lv, Xiaowei Li
2005	J	`jnl`	An innovative free memory design for network processors in home network gateway. IEEE Trans. Consumer Electron. Shuguang Gong, Huawei Li, Xiaowei Li
2005	C	`conf`	Compression/Scan Co-Design for Reducing Test Data Volume, Scan-in Power Dissipation and Test Application Time. PRDC Yu Hu, Xiaowei Li, Huawei Li, Xiaoqing Wen
2005	—	`conf`	Design of an efficient memory subsystem for network processor. ASP-DAC Shuguang Gong, Huawei Li, Yufeng Xu, Tong Liu, Xiaowei Li
2005	—	`conf`	Deterministic and low power BIST based on scan slice overlapping. ISCAS (6) Ji Li, Yinhe Han, Xiaowei Li
2005	J	`jnl`	Formal Verification Techniques Based on Boolean Satisfiability Problem. J. Comput. Sci. Technol. Xiaowei Li, Guanghui Li, Ming Shao
2005	—	`conf`	Non-robust Test Generation for Crosstalk-Induced Delay Faults. Asian Test Symposium Pei-Fu Shen, Huawei Li, Yong-Jun Xu, Xiaowei Li
2005	J	`jnl`	Perface. J. Comput. Sci. Technol. Xiaowei Li
2005	—	`conf`	Scan Data Volume Reduction Using Periodically Alterable MUXs Decompressor. Asian Test Symposium Yinhe Han, Xiaowei Li, Shivakumar Swaminathan, Yu Hu, Anshuman Chandra
2005	J	`jnl`	Selection of Crosstalk-Induced Faults in Enhanced Delay Test. J. Electron. Test. Huawei Li, Xiaowei Li
2005	J	`jnl`	Test Resource Partitioning Based on Efficient Response Compaction for Test Time and Tester Channels Reduction. J. Comput. Sci. Technol. Yinhe Han, Xiaowei Li, Huawei Li, Anshuman Chandra
2005	—	`conf`	The Automatic Generation of Basis Set of Path for Path Testing. Asian Test Symposium Guangmei Zhang, Chen Rui, Xiaowei Li, Congying Han
2005	—	`conf`	Theoretic analysis and enhanced X-tolerance of test response compact based on convolutional code. ASP-DAC Yinhe Han, Yu Hu, Huawei Li, Xiaowei Li
2005	—	`conf`	Using MUXs Network to Hide Bunches of Scan Chains. ISQED Yinhe Han, Yu Hu, Huawei Li, Xiaowei Li
2005	—	`conf`	Validation analysis and test flow optimization of VLSI chip. ISCAS (6) Yanzhuo Tan, Yinhe Han, Xiaowei Li, Feiyin Lu, Yuchuan Chen
2005	—	`conf`	Vector extraction for average total power estimation. ASP-DAC Yongjun Xu, Jinghua Chen, Zuying Luo, Xiaowei Li
2005	J	`jnl`	Wrapper Scan Chains Design for Rapid and Low Power Testing of Embedded Cores. IEICE Trans. Inf. Syst. Yinhe Han, Yu Hu, Xiaowei Li, Huawei Li, Anshuman Chandra, Xiaoqing Wen
2004	—	`conf`	A maximum total leakage current estimation method. ISCAS (2) Yongjun Xu, Zuying Luo, Xiaowei Li
2004	—	`conf`	Circuit-Width Based Heuristic for Boolean Reasoning. Asian Test Symposium Guanghui Li, Xiaowei Li
2004	J	`jnl`	Conference Reports. IEEE Des. Test Comput. Xiaowei Li
2004	J	`jnl`	Leakage Current Estimation of CMOS Circuit with Stack Effect. J. Comput. Sci. Technol. Yong-Jun Xu, Zuying Luo, Xiaowei Li, Li-Jian Li, Xianlong Hong
2004	—	`conf`	Pair Balance-Based Test Scheduling for SOCs. Asian Test Symposium Yu Hu, Yinhe Han, Huawei Li, Tao Lv, Xiaowei Li
2004	—	`conf`	Rapid and Energy-Efficient Testing for Embedded Cores. Asian Test Symposium Yinhe Han, Yu Hu, Huawei Li, Xiaowei Li, Anshuman Chandra
2004	—	`conf`	Response Compaction for Test Time and Test Pins Reduction Based on Advanced Convolutional Codes. DFT Yinhe Han, Yu Hu, Huawei Li, Xiaowei Li, Anshuman Chandra
2004	—	`conf`	Simultaneous Reduction of Test Data Volume and Testing Power for Scan-Based Test. ESA/VLSI Yinhe Han, Xiaowei Li
2003	J	`jnl`	A Novel RT-Level Behavioral Description Based ATPG Method. J. Comput. Sci. Technol. Zhigang Yin, Yinghua Min, Xiaowei Li, Huawei Li
2003	—	`conf`	An Efficient Observability Evaluation Algorithm Based on Factored Use-Def Chains. Asian Test Symposium Tao Lv, Jianping Fan, Xiaowei Li
2003	—	`conf`	An Expression's Single Fault Model and the Testing Methods. Asian Test Symposium Yunzhan Gong, Wanli Xu, Xiaowei Li
2003	—	`conf`	Average Leakage Current Macromodeling for Dual-Threshold Voltage Circuits. Asian Test Symposium Yongjun Xu, Zuying Luo, Zhiguo Chen, Xiaowei Li
2003	—	`conf`	Delay Test Pattern Generation Considering Crosstalk-Induced Effects. Asian Test Symposium Huawei Li, Yue Zhang, Xiaowei Li
2003	—	`conf`	Design Error Diagnosis Based on Verification Techniques. Asian Test Symposium Guanghui Li, Ming Shao, Xiaowei Li
2003	—	`conf`	SAT-Based Algorithm of Verification for Port Order Fault. Asian Test Symposium Ming Shao, Guanghui Li, Xiaowei Li
2003	—	`conf`	Test Resource Partitioning Based on Efficient Response Compaction for Test Time and Teste. Asian Test Symposium Yinhe Han, Yongjun Xu, Huawei Li, Xiaowei Li, Anshuman Chandra
2002	—	`conf`	Test Power Optimization Techniques for CMOS Circuits. Asian Test Symposium Zuying Luo, Xiaowei Li, Huawei Li, Shiyuan Yang, Yinghua Min
2002	J	`jnl`	The monotonic increasing relationship between average powers of CMOS VLSI circuits with and without delay and its applications. Sci. China Ser. F Inf. Sci. Zuying Luo, Yinghua Min, Shiyuan Yang, Xiaowei Li
2001	J	`jnl`	A Loop-Based Apparatus for At-Speed Self-Testing. J. Comput. Sci. Technol. Xiaowei Li, Paul Y. S. Cheung
2001	—	`conf`	An Approach to RTL Fault Extraction and Test Generation. Asian Test Symposium Zhigang Yin, Yinghua Min, Xiaowei Li
2001	—	`conf`	Reducing Power Dissipation during At-Speed Test Application. DFT Xiaowei Li, Huawei Li, Yinghua Min
2000	J	`jnl`	Exploiting Deterministic TPG for Path Delay Testing. J. Comput. Sci. Technol. Xiaowei Li, Paul Y. S. Cheung
2000	J	`jnl`	High Level Synthesis for Loop-Based BIST. J. Comput. Sci. Technol. Xiaowei Li, Paul Y. S. Cheung
2000	J	`jnl`	LFSR-Based Deterministic TPG for Two-Pattern Testing. J. Electron. Test. Xiaowei Li, Paul Y. S. Cheung, Hideo Fujiwara
2000	—	`conf`	Strong self-testability for data paths high-level synthesis. Asian Test Symposium Xiaowei Li, Toshimitsu Masuzawa, Hideo Fujiwara
1999	—	`conf`	An approach to behavioral synthesis for loop-based BIST. ISCAS (6) Xiaowei Li, Paul Y. S. Cheung
1999	—	`conf`	Data Path Synthesis for BIST with Low Area Overhead. ASP-DAC Xiaowei Li, Paul Y. S. Cheung
1999	—	`conf`	Exploiting Test Resource Optimization in Data Path Synthesis for BIST. Great Lakes Symposium on VLSI Xiaowei Li, Paul Y. S. Cheung
1998	—	`conf`	Exploiting BIST Approach for Two-Pattern Testing. Asian Test Symposium Xiaowei Li, Paul Y. S. Cheung
1998	—	`conf`	High-Level BIST Synthesis for Delay Testing. DFT Xiaowei Li, Paul Y. S. Cheung