Xiaoteng Zhao

32 papers C 1Journal 23Unranked 8
YearRankTypeTitle / Venue / Authors
2026 J jnl
A 0.0006-mm
IEEE J. Solid State Circuits
Zhicheng Dong, Xiaoteng Zhao, Zekai Yang, Xianting Su, Haolin Han, Feng Bu, Depeng Sun, Shubin Liu, Zhangming Zhu
2026 J jnl
A full-rate 8.2-to-15.1-Gb/s reference-less CDR using low-cost SAR-based frequency acquisition technique achieving 265ns acquisition time.
Microelectron. J.
Yilong Dong, Xiaoteng Zhao, Yuhao Zhang, Hao Chang, Yuxing Qi, Zekai Yang, Chenxi Han, Hongzhi Liang, Yukui Yu, Shubin Liu
2025 J jnl
A 1-V 3.9-5.2-GHz reference-sampling PLL with 168-fsrms integrated jitter and -76-dBc reference spur.
Microelectron. J.
Feng Bu, Ruixue Ding, Depeng Sun, Yuan Gao, Ruiqing Wang, Xiaoteng Zhao, Rong Zhou, Shubin Liu
2025 — conf
A 100Gb/s Transmitter with Digital Pre-Distortion and MUX-Merged Voltage-Mode Driver Achieving 3-Times INLPP Improvement in 28nm CMOS.
CICC
Chenxi Han, Xiaoteng Zhao, Qi Zhang, Yuan Liu, Yuhao Zhang, Hongzhi Liang, Yukui Yu, Shubin Liu, Zhangming Zhu
2025 J jnl
A 56 Gb/s PAM4 slope-sampling CDR with simultaneous four-output phase interpolator.
Microelectron. J.
Zekai Yang, Xiaoteng Zhao, Huajin Sun, Xianting Su, Zhicheng Dong, Yilong Dong, Yukui Yu, Hongzhi Liang, Shubin Liu
2025 J jnl
A 56 Gb/s PAM4 slope-sampling CDR with simultaneous four-output phase interpolator.
Microelectron. J.
Zekai Yang, Xiaoteng Zhao, Huajin Sun, Xianting Su, Zhicheng Dong, Yilong Dong, Yukui Yu, Hongzhi Liang, Shubin Liu
2025 J jnl
A 7-bit 8 GHz phase interpolator with eight-phase output using a linear weighting scheme using only 50 % interpolation units.
Microelectron. J.
Jie Liu, Xianting Su, Zekai Yang, Zhicheng Dong, Chenxi Han, Xiaoteng Zhao, Shubin Liu
2025 J jnl
A 7.4-9.2-GHz Fractional-N Differential Sampling PLL Based on Phase-Domain and Voltage-Domain Hybrid Calibration.
IEEE Trans. Very Large Scale Integr. Syst.
Feng Bu, Ruixue Ding, Depeng Sun, Ge Wang, Yuan Gao, Rong Zhou, Xiaoteng Zhao, Lisheng Chen, Shubin Liu, Zhangming Zhu
2025 J jnl
A Low-Noise Class-F
IEEE Trans. Circuits Syst. I Regul. Pap.
Yuan Gao, Depeng Sun, Chao Gu, Feng Bu, Bowen Wang, Rong Zhou, Zhicheng Dong, Xiaoteng Zhao, Tao Zhang, Ruixue Ding, Shubin Liu, Zhangming Zhu
2025 — conf
A Reference-Less CDR Using SAR-Based Frequency-Acquisition Technique Achieving 55ns Constant Band-Searching Time and up to 63.64Gb/s/µs Acquisition Speed.
ISSCC
Xiaoteng Zhao, Yuhao Zhang, Hao Chang, Yilong Dong, Chenxi Han, Zekai Yang, Zhicheng Dong, Rong Zhou, Shubin Liu, Zhangming Zhu
2025 J jnl
Load-driven inductive peaking design for broad band continuous-time linear equalizer.
Microelectron. J.
Miao Zhang, Ruidong Li, Xiaoteng Zhao, Xianting Su, Zhicheng Dong, Zekai Yang, Hongyu Su, Hongzhi Liang, Yukui Yu, Shubin Liu
2025 J jnl
Survey of Chiplet Technology: SoC Architecture, Interconnect, EDA, and Advanced Packaging.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Hongwei Liu, Yuan Du, Bo Pu, Guojun Yuan, Yuhang Liu, Linji Zheng, Pengchao Wang, An Yang, Yu Li, Chengming Yu, Fei Guo, Xiaoteng Zhao, Xuqiang Zheng, He Sun, Yongfu Li, Shaolin Xiang, Qinfen Hao
2025 J jnl
Withdrawal notice to "A 56 Gb/s PAM4 slope-sampling CDR with simultaneous four-output phase interpolator" [Microelectron. J. 166 (2025) 106872].
Microelectron. J.
Zekai Yang, Xiaoteng Zhao, Huajin Sun, Xianting Su, Zhicheng Dong, Yilong Dong, Yukui Yu, Hongzhi Liang, Shubin Liu
2024 — conf
A 0.0006-mm
A-SSCC
Zhicheng Dong, Xiaoteng Zhao, Zekai Yang, Xianting Su, Haolin Han, Feng Bu, Rong Zhou, Depeng Sun, Yong Chen, Shubin Liu, Ruixue Ding, Zhangming Zhu
2024 J jnl
A 0.08%/V 32.3-ppm/°C 36.6-kHz Unregulated Current-Reuse Ring Oscillator With VGS-Ratio-Based Compensation Using One-Type-Only Resistor.
IEEE J. Solid State Circuits
Zhicheng Dong, Shubin Liu, Xiaoteng Zhao, Baotian Hao, Xianting Su, Hongzhi Liang, Menghao Wang, Zhangming Zhu
2024 — conf
A 0.9-V Supply Up to 21.5-dB Boost Gain Analog Front-End with T-coilloaded CTLE and VGA in 28-nm CMOS for 112-Gb/s PAM-4 Medium-Reach Receivers.
ICTA
Miao Zhang, Xianting Su, Zekai Yang, Zhicheng Dong, Weitan Huang, Menghao Wang, Yukui Yu, Xiaoteng Zhao, Shubin Liu, Zhangming Zhu
2024 J jnl
A 3.96-4.84-GHz Dual-Path Charge Pump PLL Achieving 89.7-fs
IEEE Trans. Circuits Syst. II Express Briefs
Depeng Sun, Linguo Huang, Rong Zhou, Feng Bu, Lisheng Chen, Xiaoteng Zhao, Ruixue Ding, Shubin Liu, Zhangming Zhu
2024 C conf
A 30.5-to-31 GHz Sampling PLL With Double-Edge Sampling PD and Implict Common-Mode VCO Scoring 39.69-fs RMS Jitter and -253.6-dB FoM in a 0.047mm
ISCAS
Zhicheng Dong, Xiaoteng Zhao, Weitan Huang, Yuan Gao, Depeng Sun, Shubin Liu, Lihong Yang, Zhangming Zhu
2024 J jnl
A 56 Gb/s DAC-DSP-based transmitter with adaptive retiming clock optimization using inverse-PR-based PD achieving 8-UI converge time in 28-nm CMOS.
Sci. China Inf. Sci.
Shubin Liu, Chenxi Han, Xiaoteng Zhao, Yuhao Zhang, Shixin Li, Hongzhi Liang, Lihong Yang, Zhangming Zhu
2024 J jnl
A 8.1-nW, 4.22-kHz, -40-85 °C relaxation oscillator with subthreshold leakage current compensation and forward body bias buffer for low power IoT applications.
Microelectron. J.
Rong Zhou, Linwei Wang, Jianhang Yang, Zhen Li, Xiaoteng Zhao, Shubin Liu
2024 J jnl
A low-noise, 0.05-17.8-GHz fractional-N phase-locked loop with two parallel synchronized dual-core voltage-controlled oscillators.
Microelectron. J.
Depeng Sun, Ruiqing Wang, Feng Bu, Yuan Gao, Xiaoteng Zhao, Ruixue Ding, Shubin Liu, Rong Zhou
2024 J jnl
A wideband low power RF Receiver Front-End for Internet-of-Things applications.
Microelectron. J.
Rong Zhou, Jianhang Yang, Linwei Wang, Xiaoteng Zhao, Shubin Liu, Depeng Sun
2023 — conf
A 0.012mm
CICC
Zhicheng Dong, Shubin Liu, Xiaoteng Zhao, Baotian Hao, Hongzhi Liang, Haolin Han, Menghao Wang, Weijie Han, Zhangming Zhu
2023 J jnl
A 10.8-to-37.4 Gb/s Reference-Less FD-Less Single-Loop Quarter-Rate Bang-Bang Clock and Data Recovery Employing Deliberate-Current- Mismatch Wide-Frequency-Acquisition Technique.
IEEE Trans. Circuits Syst. I Regul. Pap.
Lin Wang, Yong Chen, Chaowei Yang, Xiaoteng Zhao, Pui-In Mak, Franco Maloberti, Rui Paulo Martins
2022 J jnl
A 0.0285-mm
IEEE J. Solid State Circuits
Xiaoteng Zhao, Yong Chen, Pui-In Mak, Rui Paulo Martins
2022 — conf
A 10.8-to-37.4Gb/s Single-Loop Quarter-Rate BBCDR Without External Reference and Separate FD Featuring a Wide-Frequency-Acquisition Scheme.
ICECS 2022
Lin Wang, Yong Chen, Chaowei Yang, Xiaoteng Zhao, Pui-In Mak, Franco Maloberti, Rui Paulo Martins
2022 J jnl
A Sub-0.25-pJ/bit 47.6-to-58.8-Gb/s Reference-Less FD-Less Single-Loop PAM-4 Bang-Bang CDR With a Deliberate-Current-Mismatch Frequency Acquisition Technique in 28-nm CMOS.
IEEE J. Solid State Circuits
Xiaoteng Zhao, Yong Chen, Lin Wang, Pui-In Mak, Franco Maloberti, Rui Paulo Martins
2021 J jnl
A 0.14-to-0.29-pJ/bit 14-GBaud/s Trimodal (NRZ/PAM-4/PAM-8) Half-Rate Bang-Bang Clock and Data Recovery (BBCDR) Circuit in 28-nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap.
Xiaoteng Zhao, Yong Chen, Pui-In Mak, Rui Paulo Martins
2020 — conf
A 0.0285mm
CICC
Xiaoteng Zhao, Yong Chen, Pui-In Mak, Rui Paulo Martins
2019 J jnl
A 0.0018-mm
IEEE Trans. Circuits Syst. I Regul. Pap.
Xiaoteng Zhao, Yong Chen, Pui-In Mak, Rui Paulo Martins
2019 — conf
A 0.14-to-0.29-pJ/bit 14-GBaud/s Trimodal (NRZ/PAM-4/PAM-8) Half-Rate Bang-Bang Clock and Data Recovery Circuit (BBCDR) in 28-nm CMOS.
APCCAS
Xiaoteng Zhao, Yong Chen, Pui-In Mak, Rui Paulo Martins
2019 J jnl
Analysis and Verification of Jitter in Bang-Bang Clock and Data Recovery Circuit With a Second-Order Loop Filter.
IEEE Trans. Very Large Scale Integr. Syst.
Xinyi Ge, Yong Chen, Xiaoteng Zhao, Pui-In Mak, Rui Paulo Martins