Xiaotao Jia

44 papers A* 5A 2C 2Journal 26Unranked 9
YearRankTypeTitle / Venue / Authors
2026 J jnl
Efficient SRAM-PIM Co-Design by Joint Exploration of Value-Level and Bit-Level Sparsity.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Cenlin Duan, Jianlei Yang, Yikun Wang, Yiou Wang, Yingjie Qi, Xiaolin He, Bonan Yan, Xueyan Wang, Xiaotao Jia, Weisheng Zhao
2025 J jnl
AM-CIM: Approximate Memory Based Near Sensor Compute-in-Memory Architecture for Keyword Spotting.
IEEE Trans. Circuits Syst. I Regul. Pap.
Yuhao Liu, Xiaotao Jia, Guangcai Yuan, Jianyi Yu, Cong Shi, Qi Wei, Youguang Zhang, Weisheng Zhao, Fei Qiao
2025 J jnl
Efficient SRAM-PIM Co-design by Joint Exploration of Value-Level and Bit-Level Sparsity.
CoRR
Cenlin Duan, Jianlei Yang, Yikun Wang, Yiou Wang, Yingjie Qi, Xiaolin He, Bonan Yan, Xueyan Wang, Xiaotao Jia, Weisheng Zhao
2025 A* conf
Finesse: An Agile Design Framework for Pairing-based Cryptography via Software/Hardware Co-Design.
ISCA
Tianwei Pan, Tianao Dai, Jianlei Yang, Hongbin Jing, Yang Su, Zeyu Hao, Xiaotao Jia, Chunming Hu, Weisheng Zhao
2025 J jnl
Finesse: An Agile Design Framework for Pairing-based Cryptography via Software/Hardware Co-Design.
CoRR
Tianwei Pan, Tianao Dai, Jianlei Yang, Hongbin Jing, Yang Su, Zeyu Hao, Xiaotao Jia, Chunming Hu, Weisheng Zhao
2025 A* conf
MBQ: Modality-Balanced Quantization for Large Vision-Language Models.
CVPR
Shiyao Li, Yingchun Hu, Xuefei Ning, Xihui Liu, Ke Hong, Xiaotao Jia, Xiuhong Li, Yaqi Yan, Pei Ran, Guohao Dai, Shengen Yan, Huazhong Yang, Yu Wang
2025 A* conf
MIRACLE: Multimodal Information Retrieval via a Combined In-Memory Processing and Content Addressable Memory Approach.
DAC
Xuehui Liu, Xueyan Wang, Tianyang Yu, Chen Cheng, Shuo Ran, Bi Wu, Xiaotao Jia, Weiqiang Liu, Gang Qu, Weisheng Zhao
2025 A conf
Ultra Energy-Efficient Butterfly Counting in Bipartite Networks via Algorithm-Architecture Co-Optimization.
ICCAD
Haiyang Liu, Xueyan Wang, Jianlei Yang, Xiaotao Jia, Gang Qu, Weisheng Zhao
2024 J jnl
An Energy-Efficient Bayesian Neural Network Implementation Using Stochastic Computing Method.
IEEE Trans. Neural Networks Learn. Syst.
Xiaotao Jia, Huiyi Gu, Yuhao Liu, Jianlei Yang, Xueyan Wang, Weitao Pan, Youguang Zhang, Sorin Cotofana, Weisheng Zhao
2024 J jnl
CiM-BNN:Computing-in-MRAM Architecture for Stochastic Computing Based Bayesian Neural Network.
IEEE Trans. Emerg. Top. Comput.
Huiyi Gu, Xiaotao Jia, Yuhao Liu, Jianlei Yang, Xueyan Wang, Youguang Zhang, Sorin Dan Cotofana, Weisheng Zhao
2024 J jnl
DDC-PIM: Efficient Algorithm/Architecture Co-Design for Doubling Data Capacity of SRAM-Based Processing-in-Memory.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Cenlin Duan, Jianlei Yang, Xiaolin He, Yingjie Qi, Yikun Wang, Yiou Wang, Ziyan He, Bonan Yan, Xueyan Wang, Xiaotao Jia, Weitao Pan, Weisheng Zhao
2024 C conf
Hierarchical Placement Algorithm for Analog Circuit With Polygonal Modules.
ISCAS
Mengzhe Han, Xiaotao Jia, Zihao Zhao, Yingchun Hu
2024 — conf
LLP-ECCA: A Low-Latency and Programmable Framework for Elliptic Curve Cryptography Accelerators.
ITC-Asia
Yicheng Huang, Xueyan Wang, Tianao Dai, Jianlei Yang, Zhaojun Lu, Xiaotao Jia, Gang Qu, Weisheng Zhao
2024 J jnl
MBQ: Modality-Balanced Quantization for Large Vision-Language Models.
CoRR
Shiyao Li, Yingchun Hu, Xuefei Ning, Xihui Liu, Ke Hong, Xiaotao Jia, Xiuhong Li, Yaqi Yan, Pei Ran, Guohao Dai, Shengen Yan, Huazhong Yang, Yu Wang
2024 C conf
Miniaturized and Integrated On-Chip Ag/AgCl Micro-electrodes for Chemical Detection.
ISCAS
Jing Liang, Xiaotao Jia, Yuanqi Hu
2024 A* conf
Towards Efficient SRAM-PIM Architecture Design by Exploiting Unstructured Bit-Level Sparsity.
DAC
Cenlin Duan, Jianlei Yang, Yiou Wang, Yikun Wang, Yingjie Qi, Xiaolin He, Bonan Yan, Xueyan Wang, Xiaotao Jia, Weisheng Zhao
2024 J jnl
Towards Efficient SRAM-PIM Architecture Design by Exploiting Unstructured Bit-Level Sparsity.
CoRR
Cenlin Duan, Jianlei Yang, Yiou Wang, Yikun Wang, Yingjie Qi, Xiaolin He, Bonan Yan, Xueyan Wang, Xiaotao Jia, Weisheng Zhao
2023 — conf
"\"Peak\" Quantization: A Training Method Suitable for Terminal Equipment to Deploy Keyword Spotting Network".
ICAICE
Xiaomeng Luo, Guangcun Wei, Yuhao Liu, Xiaotao Jia, Xinghua Yang, Junlin Li, Qi Wei, Fei Qiao
2023 J jnl
DDC-PIM: Efficient Algorithm/Architecture Co-design for Doubling Data Capacity of SRAM-based Processing-In-Memory.
CoRR
Cenlin Duan, Jianlei Yang, Xiaolin He, Yingjie Qi, Yikun Wang, Yiou Wang, Ziyan He, Bonan Yan, Xueyan Wang, Xiaotao Jia, Weitao Pan, Weisheng Zhao
2023 J jnl
IMGA: Efficient In-Memory Graph Convolution Network Aggregation With Data Flow Optimizations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yuntao Wei, Xueyan Wang, Shangtong Zhang, Jianlei Yang, Xiaotao Jia, Zhaohao Wang, Gang Qu, Weisheng Zhao
2023 J jnl
NAND-SPIN-based processing-in-MRAM architecture for convolutional neural network acceleration.
Sci. China Inf. Sci.
Yinglin Zhao, Jianlei Yang, Bing Li, Xingzhou Cheng, Xucheng Ye, Xueyan Wang, Xiaotao Jia, Zhaohao Wang, Youguang Zhang, Weisheng Zhao
2022 J jnl
Accelerating Graph-Connected Component Computation With Emerging Processing-In-Memory Architecture.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Xuhang Chen, Xueyan Wang, Xiaotao Jia, Jianlei Yang, Gang Qu, Weisheng Zhao
2022 J jnl
NAND-SPIN-Based Processing-in-MRAM Architecture for Convolutional Neural Network Acceleration.
CoRR
Yinglin Zhao, Jianlei Yang, Bing Li, Xingzhou Cheng, Xucheng Ye, Xueyan Wang, Xiaotao Jia, Zhaohao Wang, Youguang Zhang, Weisheng Zhao
2022 J jnl
Triangle Counting Accelerations: From Algorithm to In-Memory Computing Architecture.
IEEE Trans. Computers
Xueyan Wang, Jianlei Yang, Yinglin Zhao, Xiaotao Jia, Rong Yin, Xuhang Chen, Gang Qu, Weisheng Zhao
2021 J jnl
Efficient Computation Reduction in Bayesian Neural Networks Through Feature Decomposition and Memorization.
IEEE Trans. Neural Networks Learn. Syst.
Xiaotao Jia, Jianlei Yang, Runze Liu, Xueyan Wang, Sorin Dan Cotofana, Weisheng Zhao
2021 J jnl
Triangle Counting Accelerations: From Algorithm to In-Memory Computing Architecture.
CoRR
Xueyan Wang, Jianlei Yang, Yinglin Zhao, Xiaotao Jia, Rong Yin, Xuhang Chen, Gang Qu, Weisheng Zhao
2020 J jnl
An STT-MRAM based reconfigurable computing-in-memory architecture for general purpose computing.
CCF Trans. High Perform. Comput.
Yu Pan, Xiaotao Jia, Zhen Cheng, Peng Ouyang, Xueyan Wang, Jianlei Yang, Weisheng Zhao
2020 J jnl
Efficient Computation Reduction in Bayesian Neural Networks Through Feature Decomposition and Memorization.
CoRR
Xiaotao Jia, Jianlei Yang, Runze Liu, Xueyan Wang, Sorin Dan Cotofana, Weisheng Zhao
2020 J jnl
Hardware Security in Spin-Based Computing-In-Memory: Analysis, Exploits, and Mitigation Techniques.
CoRR
Xueyan Wang, Jianlei Yang, Yinglin Zhao, Xiaotao Jia, Gang Qu, Weisheng Zhao
2020 J jnl
Hardware Security in Spin-based Computing-in-memory: Analysis, Exploits, and Mitigation Techniques.
ACM J. Emerg. Technol. Comput. Syst.
Xueyan Wang, Jianlei Yang, Yinglin Zhao, Xiaotao Jia, Gang Qu, Weisheng Zhao
2020 — conf
MSFRoute: Multi-Stage FPGA Routing for Timing Division Multiplexing Technique.
ACM Great Lakes Symposium on VLSI
Zhen Zhuang, Genggeng Liu, Xing Huang, Xiaotao Jia, Wen-Hao Liu, Wenzhong Guo
2020 J jnl
SPINBIS: Spintronics-Based Bayesian Inference System With Stochastic Computing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Xiaotao Jia, Jianlei Yang, Pengcheng Dai, Runze Liu, Yiran Chen, Weisheng Zhao
2020 A* conf
TCIM: Triangle Counting Acceleration With Processing-In-MRAM Architecture.
DAC
Xueyan Wang, Jianlei Yang, Yinglin Zhao, Yingjie Qi, Meichen Liu, Xingzhou Cheng, Xiaotao Jia, Xiaoming Chen, Gang Qu, Weisheng Zhao
2020 J jnl
TCIM: Triangle Counting Acceleration With Processing-In-MRAM Architecture.
CoRR
Xueyan Wang, Jianlei Yang, Yinglin Zhao, Yingjie Qi, Meichen Liu, Xingzhou Cheng, Xiaotao Jia, Xiaoming Chen, Gang Qu, Weisheng Zhao
2019 — conf
Exploiting Near-Memory Processing Architectures for Bayesian Neural Networks Acceleration.
ISVLSI
Yinglin Zhao, Jianlei Yang, Xiaotao Jia, Xueyan Wang, Zhaohao Wang, Wang Kang, Youguang Zhang, Weisheng Zhao
2019 J jnl
SPINBIS: Spintronics based Bayesian Inference System with Stochastic Computing.
CoRR
Xiaotao Jia, Jianlei Yang, Pengcheng Dai, Runze Liu, Yiran Chen, Weisheng Zhao
2018 J jnl
A Multicommodity Flow-Based Detailed Router With Efficient Acceleration Techniques.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Xiaotao Jia, Yici Cai, Qiang Zhou, Bei Yu
2018 — conf
Electromigration Design Rule aware Global and Detailed Routing Algorithm.
ACM Great Lakes Symposium on VLSI
Xiaotao Jia, Jing Wang, Yici Cai, Qiang Zhou
2018 — conf
Spintronics based stochastic computing for efficient Bayesian inference system.
ASP-DAC
Xiaotao Jia, Jianlei Yang, Zhaohao Wang, Yiran Chen, Hai Helen Li, Weisheng Zhao
2017 J jnl
Spintronics based Stochastic Computing for Efficient Bayesian Inference System.
CoRR
Xiaotao Jia, Jianlei Yang, Zhaohao Wang, Yiran Chen, Hai Li, Weisheng Zhao
2016 — conf
MCFRoute 2.0: A Redundant Via Insertion Enhanced Concurrent Detailed Router.
ACM Great Lakes Symposium on VLSI
Xiaotao Jia, Yici Cai, Qiang Zhou, Bei Yu
2016 — conf
Secure and Low-Overhead Circuit Obfuscation Technique with Multiplexers.
ACM Great Lakes Symposium on VLSI
Xueyan Wang, Xiaotao Jia, Qiang Zhou, Yici Cai, Jianlei Yang, Mingze Gao, Gang Qu
2015 — conf
A New Random-Walk Based Label Propagation Community Detection Algorithm.
WI-IAT (1)
Chang Su, Xiaotao Jia, Xianzhong Xie, Yue Yu
2014 A conf
MCFRoute: a detailed router based on multi-commodity flow method.
ICCAD
Xiaotao Jia, Yici Cai, Qiang Zhou, Gang Chen, Zhuoyuan Li, Zuowei Li