Xiaoming Liu

45 papers C 11Journal 23Unranked 11
YearRankTypeTitle / Venue / Authors
2026 J jnl
A 37-48 GHz Frequency Doubler With >47.8 dBc FRR Utilizing a Staggered Fundamental Suppression Technique.
IEEE Trans. Circuits Syst. II Express Briefs
Yuyang Chen, Chao Yang, Xiaoming Liu, Jing Jin, Jianjun Zhou
2026 J jnl
A 40-nm CMOS Phase-Tunable Four-Phase Injection-Locked Ring VCO Utilizing Unbalanced Feedforward Topology Achieving -211.1- to -207.3-dBc/Hz FoM
IEEE J. Solid State Circuits
Huzhi Tang, Yuekang Guo, Jing Jin, Xiaoming Liu, Yi Liu, Zhongyuan Chang, Howard C. Yang, Jianjun Zhou
2025 J jnl
A 0.2-2.6 GHz Reconfigurable Receiver Using RF-Gain-Adapted Impedance Matching and Gm-Separated IQ-Leakage Suppression Structure in 40-nm CMOS.
IEEE Trans. Very Large Scale Integr. Syst.
Zhaolin Yang, Jing Jin, Xiaoming Liu, Jianjun Zhou
2025 J jnl
A 470 μW 20 kHz-BW 107.3 dB-SNDR Nested CT DSM Using Negative-R-Based Cross-RC Integrator and Weighted Multi-Threshold MSB-Pass Quantizer.
IEEE Trans. Circuits Syst. I Regul. Pap.
Jing Jin, Meng Xu, Yuekang Guo, Xiaoming Liu, Nan Sun, Jianjun Zhou
2025 J jnl
A Fully Symmetric Oscillator-Based CMOS Ising Machine Architecture With Successive Approximation Sampling and Power Efficient Solution Refinement.
IEEE Trans. Circuits Syst. I Regul. Pap.
Ke Wu, Yuekang Guo, Xiaoming Liu, Zhongyuan Chang, Howard C. Yang, Jing Jin, Jianjun Zhou
2025 J jnl
A reconfigurable passive LNA using an N-path switched-capacitor transformer with 2×/3× voltage Gain.
Microelectron. J.
Zhaolin Yang, Xiaoming Liu, Jing Jin, Jianjun Zhou
2024 J jnl
A 0.83-pJ/b 20-Gb/s/Pin Single-Ended Transceiver With AC/DC-Coupled Pre-Emphasis FFE and Edge-Dependent Phase-Modulation DFE for Low-Power Memory Controllers.
IEEE Trans. Circuits Syst. I Regul. Pap.
Xiaofei Wang, Jing Jin, Xiaoming Liu, Hui Wang, Huzhi Tang, Chao Yang, Yuekang Guo, Tingting Mo, Jianjun Zhou
2024 — conf
A 470μW 20kHz-BW 107.3dB-SNDR Nested CT DSM Employing Negative-R-Based Cross-RC Filter and Weighted Multi-Threshold MSB-Pass Quantizer.
CICC
Jing Jin, Yuekang Guo, Meng Xu, Xiaoming Liu, Nan Sun, Jianjun Zhou
2023 C conf
A 16/32-Gb/s/pin Dual-Mode Single-Ended Transmitter with Pre-Emphasis FFE and RLM-Enhanced ZQ Calibration for Memory Interfaces.
ISCAS
Xiaofei Wang, Jing Jin, Xiaoming Liu, Zhaolin Yang, Shan Wang, Jianjun Zhou
2023 — conf
A 30GHz Bidirectional PA/LNA with Transformer-Based Switchable RC Matching Network.
ASICON
Hanqi Gao, Jing Jin, Zhaolin Yang, Jianjun Zhou, Xiaoming Liu
2023 J jnl
A 372 μW 10 kHz-BW 109.2 dB-SNDR Nested Delta-Sigma Modulator Using Hysteresis-Comparison MSB-Pass Quantization.
IEEE J. Solid State Circuits
Yuekang Guo, Jing Jin, Xiaoming Liu, Jianjun Zhou
2023 J jnl
A 4 GHz FLL-less fast-locking sampling PLL with gain-boosted sampling phase-frequency detector in 28 nm CMOS.
Microelectron. J.
Chao Yang, Sheng Wang, Xiaoming Liu, Jing Jin, Jianjun Zhou
2023 J jnl
A 60-MS/s 5-MHz BW Noise-Shaping SAR ADC With Integrated Input Buffer Achieving 84.2-dB SNDR and 97.3-dB SFDR Using Dynamic Level-Shifting and ISI-Error Correction.
IEEE J. Solid State Circuits
Yuekang Guo, Jing Jin, Xiaoming Liu, Jianjun Zhou
2023 J jnl
A Compact 0.2-1.6 GHz 20 MHz-Bandwidth Passive-LNA Exploiting an N-Path 1:3 Transformer.
IEEE Trans. Circuits Syst. II Express Briefs
Minjing Lee, Xiaoming Liu, Zhaolin Yang, Jing Jin, Lin-Sheng Wu
2023 — conf
A Fully Synthesizable Dynamic Voltage Comparator with Time-Domain Offset Calibration.
MWSCAS
Shunyan Wang, Yuekang Guo, Qiang Pan, Xiaoming Liu, Shan Wang, Jing Jin
2023 — conf
A High Precision CMOS Temperature Detector with Curvature Calibration Technique.
ASICON
Weizhen Cai, Jianjun Zhou, Xiaobo Chen, Xiaoming Liu
2023 C conf
A LUT-based Background Linearization Technique for VCO-based ADC Employing $K_{\text{VCO}}-\text{Locked}-\text{Loop}$.
ISCAS
Yuekang Guo, Jing Jin, Xiaoming Liu, Zhaolin Yang, Jianjun Zhou
2023 — conf
A Non-Linearity Digital Background Calibration Algorithm with Piece-Wise Linear Functions.
MWSCAS
Ke Wu, Yuekang Guo, Xiaoming Liu, Jing Jin, Howard C. Yang, Jianjun Zhou
2023 — conf
A Wideband Inductorless LNA Employing Dual-Loop Feedback for Low-Power Applications.
ASICON
Zhaolin Yang, Jing Jin, Yuyang Chen, Jianjun Zhou, Xiaoming Liu
2023 C conf
An ADPLL with Two-Point Modulation Gain Calibration for 2.4GHz ISM-Band in 40nm CMOS.
ISCAS
Huzhi Tang, Xiaoming Liu, Chao Yang, Jing Jin
2023 — conf
Fast locking Sampling PLL Using Phase Error Eliminator.
ASICON
Shengyuan Zhou, Ziyao Xia, Chao Yang, Xiaoming Liu, Sheng Wang, Jing Jin
2023 — conf
Predictive LSB-First Successive Approximation for SAR Analog-to-Digital Converters.
MWSCAS
Jiayi Chen, Xiaoming Liu, Chao Yang, Jing Jin, Zhongyuan Chang, Jianjun Zhou
2022 J jnl
A 0.023-12 GHz ultra-wideband frequency synthesizer with FOM
Microelectron. J.
Chao Yang, Xiaoming Liu, Jing Jin, Jianjun Zhou
2022 C conf
A 3bit/cycle 1GS/s 8-bit SAR ADC Employing Asynchronous Ping-Pong Quantization Scheme.
ISCAS
Yuekang Guo, Xiaoming Liu, Jing Jin, Jianjun Zhou
2022 J jnl
A Fast-Settling Phase-Locked Loop Utilizing Cycle-Slipping-Elimination PFDCP.
IEEE Trans. Circuits Syst. II Express Briefs
Chao Yang, Xiaoming Liu, Jing Jin, Yuekang Guo, Jianjun Zhou
2022 — conf
A Power-Efficient CMOS Image Sensor with In-Sensor Processing and In-Pixel Gain Calibration.
MWSCAS
Ke Wu, Yuekang Guo, Jing Jin, Xiaoming Liu, Jianjun Zhou
2022 J jnl
An 18.1 mW 50 MHz-BW 76.4 dB-SNDR CTSDM With PVT-Robust VCO Quantizer and Latency-Free Background-Calibrated DAC.
IEEE Trans. Circuits Syst. I Regul. Pap.
Yuekang Guo, Jing Jin, Xiaoming Liu, Jianjun Zhou
2021 J jnl
A 2.4 GHz receiver with a current-reused inductor-less noise-canceling balun LNA in 40 nm CMOS.
Microelectron. J.
Xiaoming Liu, Jing Jin, Xiaofei Wang, Jianjun Zhou
2021 — conf
A Center Frequency Calibration Technique for Ring VCO Exploiting Delay
MWSCAS
Yuekang Guo, Qiang Pan, Xiaoming Liu, Jing Jin
2021 C conf
A Ka-Band Quadrature-Hybrid LNA-PS with Gm- Boosting Technique in 40-nm CMOS.
ISCAS
Zhengqi Xu, Ke Wu, Xiaoming Liu, Chengyuan Liu, Jing Jin, Jianjun Zhou
2021 C conf
A Phase Domain Excess Loop Delay Compensation Technique with Latency Optimized Phase Selector for VCO-Based Continuous-Time ΔΣ ADC.
ISCAS
Yuekang Guo, Jing Jin, Xiaoming Liu, Jianjun Zhou
2021 J jnl
A Power-Efficient SAR ADC with Optimized Timing-Redistribution Asynchronous SAR Logic in 40-nm CMOS.
Circuits Syst. Signal Process.
Mengying Hu, Jing Jin, Yuekang Guo, Xiaoming Liu, Jianjun Zhou
2021 J jnl
A fully integrated multiphase switched-capacitor DC-DC converter with PFM control and charge sharing loss reduction.
Microelectron. J.
Haopeng Kang, Jing Jin, Xiaoming Liu, Xiaofei Wang, Pengli Hong, Jianjun Zhou
2020 C conf
A Low Power Temperature-Compensated Common-Mode Voltage Detector for Dynamic Amplifiers.
ISCAS
Ran Wang, Yuekang Guo, Jing Jin, Xiaoming Liu, Naifeng Jing, Jianjun Zhou
2020 J jnl
A Multi-Modulus Fractional Divider With TDC Free Calibration Scheme for Mitigation of TX-VCO Pulling.
IEEE Trans. Circuits Syst.
LiTong Liu, Jing Jin, Xiaoming Liu, Jianjun Zhou
2020 J jnl
An ISM Band High-Linear Current-Reuse Up-Conversion Mixer With Built-in-Self-Calibration for LOFT and I/Q Imbalance.
IEEE Trans. Circuits Syst.
Xiaofei Wang, Jing Jin, Xiaoming Liu, Jianjun Zhou
2020 J jnl
An Inverter-Based Continuous Time Sigma Delta ADC With Latency-Free DAC Calibration.
IEEE Trans. Circuits Syst.
Yuekang Guo, Jing Jin, Xiaoming Liu, Jianjun Zhou
2019 J jnl
A 0.25-dB-Step, 68-dB-Dynamic Range Analog Baseband With Digitally Assisted DCOC and AGC for Multi-Standard TV Applications.
IEEE Trans. Circuits Syst. II Express Briefs
Jing Jin, Xiaoming Liu, Jianjun Zhou
2019 — conf
An Optimized Modeling Method for Transformer Design.
ASICON
Yingying Liang, Xiaoming Liu, Jing Jin
2019 J jnl
Fully Configurable Capacitor-Less Oversampling DC Offset Cancellation for Direct Conversion Receivers.
IEEE Trans. Circuits Syst. II Express Briefs
Jing Jin, Xiaoming Liu, Taotao Yan, Jianjun Zhou
2014 C conf
Digital spur calibration of multi-modulus fractional frequency LO divider utilizing most correlated comparison algorithm.
ISCAS
Jing Jin, Bukun Pan, Xiaoming Liu, Jianjun Zhou
2014 C conf
Injection-Locking Frequency Divider based dual-modulus prescalers with extended locking range.
ISCAS
Jing Jin, Bukun Pan, Xiaoming Liu, Jianjun Zhou
2012 J jnl
Quantization Noise Suppression in Fractional-N PLLs Utilizing Glitch-Free Phase Switching Multi-Modulus Frequency Divider.
IEEE Trans. Circuits Syst. I Regul. Pap.
Jing Jin, Xiaoming Liu, Tingting Mo, Jianjun Zhou
2011 C conf
Glitch-Free Multi-Modulus Frequency Divider for Quantization Noise suppression in fractional-N PLLs.
ISCAS
Xiaoming Liu, Jing Jin, Xi Li, Jianjun Zhou
2011 C conf
Linear range extensible Phase Frequency Detector and Charge Pump for fast frequency acquisition.
ISCAS
Xiaoming Liu, Jing Jin, Cui Mao, Jianjun Zhou