Xiaolong Guo - RankMe

61 papers A* 8A 4B 2C 1Misc 1Journal 21Unranked 24

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	BlindMarket: Enabling Verifiable, Confidential, and Traceable IP Core Distribution in Zero-Trust Settings. CoRR Zhaoxiang Liu, Samuel Judson, Raj Gautam Dutta, Mark Santolucito, Xiaolong Guo, Ning Luo
2025	J	`jnl`	A Generalize Hardware Debugging Approach for Large Language Models Semi-Synthetic, Datasets. IEEE Trans. Circuits Syst. I Regul. Pap. Weimin Fu, Shijie Li, Yifang Zhao, Kaichen Yang, Xuan Zhang, Yier Jin, Xiaolong Guo
2025	J	`jnl`	AnalogSAGE: Self-evolving Analog Design Multi-Agents with Stratified Memory and Grounded Experience. CoRR Zining Wang, Jian Gao, Weimin Fu, Xiaolong Guo, Xuan Zhang
2025	J	`jnl`	Boosting Cryptographic ICs' Side-Channel Resistance: A Formal Framework for Automatic Identification and Protection of Leaky Paths. ACM Trans. Embed. Comput. Syst. Qizhi Zhang, Ya Gao, Haocheng Ma, Jiaji He, Yiqiang Zhao, Xiaolong Guo
2025	A	`conf`	Building Reasoning LLMs for Hardware Design Generation via Function-Aligned Differentiated Revision. ICCAD Weimin Fu, Shijie Li, Kaichen Yang, Xuan Silvia Zhang, Yier Jin, Xiaolong Guo
2025	—	`conf`	Cross-Layer EM Fault Injection Assessment Framework. ISQED Hanqiu Wang, Ruochen Dai, Tuba Yavuz, Xiaolong Guo, Orlando Arias, Dean Sullivan, Michael Lee, Honggang Yu, Siqi Dai, Domenic Forte, Shuo Wang
2025	A*	`conf`	EVA: An Efficient and Versatile Generative Engine for Targeted Discovery of Novel Analog Circuits. DAC Jian Gao, Weimin Fu, Xiaolong Guo, Weidong Cao, Xuan Zhang
2025	C	`conf`	Enhancing LLM Performance on Hardware Design Generation Task via Reinforcement Learning. ISCAS Yifang Zhao, Weimin Fu, Shijie Li, Yixiang Hu, Xiaolong Guo, Yier Jin
2025	—	`conf`	Evaluating the Effectiveness of Hardware Trojan Detection Approaches at RTL. HOST Ruochen Dai, Zhaoxiang Liu, Orlando Arias, Xiaolong Guo, Tuba Yavuz
2025	—	`conf`	Fixbench-RTL: A Comprehensive Benchmark for Evaluating LLMs on RTL Debugging. AsianHOST Shijie Li, Weimin Fu, Yifang Zhao, Xiaolong Guo, Yier Jin
2025	J	`jnl`	FusionESP: Improved Enzyme-Substrate Pair Prediction by Fusing Protein and Chemical Knowledge. J. Chem. Inf. Model. Zhenjiao Du, Weimin Fu, Xiaolong Guo, Doina Caragea, Yonghui Li
2025	—	`conf`	HADA: Leveraging Multi-Source Data to Train Large Language Models for Hardware Security Assertion Generation. MLCAD Weimin Fu, Yiting Wang, Zelin Lu, Xiaolong Guo, Gang Qu
2025	—	`conf`	HWFixBench: Benchmarking Tools for Hardware Understanding and Fault Repair. ACM Great Lakes Symposium on VLSI Weimin Fu, Shijie Li, Yier Jin, Xiaolong Guo
2025	A*	`conf`	Hardware Generation with High Flexibility using Reinforcement Learning Enhanced LLMs. DAC Yifang Zhao, Weimin Fu, Shijie Li, Yixiang Hu, Xiaolong Guo, Yier Jin
2025	—	`conf`	Intelligence In The Fence: Construct A Privacy and Reliable Hardware Design Assistant LLM. ACM Great Lakes Symposium on VLSI Shijie Li, Weimin Fu, Yifang Zhao, Xiaolong Guo, Yier Jin
2025	—	`conf`	Leveraging Large Language Models for Secure Hardware Verification and Analysis. AsianHOST Yifang Zhao, Weimin Fu, Yixiang Hu, Shijie Li, Xiaolong Guo, Yier Jin
2025	—	`conf`	Rethinking LLM Safety on Edge Devices: Unearthing Hidden Vulnerabilities through Power Stress. AsianHOST Weimin Fu, Zelin Lu, Gang Qu, Xiaolong Guo
2024	—	`conf`	DTjRTL: A Configurable Framework for Automated Hardware Trojan Insertion at RTL. ACM Great Lakes Symposium on VLSI Ruochen Dai, Zhaoxiang Liu, Orlando Arias, Xiaolong Guo, Tuba Yavuz
2024	B	`conf`	Hardware Phi-1.5B: A Large Language Model Encodes Hardware Domain Specific Knowledge. ASPDAC Weimin Fu, Shijie Li, Yifang Zhao, Haocheng Ma, Raj Gautam Dutta, Xuan Zhang, Kaichen Yang, Yier Jin, Xiaolong Guo
2024	J	`jnl`	Hardware Phi-1.5B: A Large Language Model Encodes Hardware Domain Specific Knowledge. CoRR Weimin Fu, Shijie Li, Yifang Zhao, Haocheng Ma, Raj Gautam Dutta, Xuan Zhang, Kaichen Yang, Yier Jin, Xiaolong Guo
2024	J	`jnl`	LLM4SecHW: Leveraging Domain Specific Large Language Model for Hardware Debugging. CoRR Weimin Fu, Kaichen Yang, Raj Gautam Dutta, Xiaolong Guo, Gang Qu
2024	B	`conf`	Microscope: Causality Inference Crossing the Hardware and Software Boundary from Hardware Perspective. ASPDAC Zhaoxiang Liu, Kejun Chen, Dean Sullivan, Orlando Arias, Raj Gautam Dutta, Yier Jin, Xiaolong Guo
2024	A*	`conf`	Poster: BlindMarket: A Trustworthy Chip Designs Marketplace for IP Vendors and Users. CCS Zhaoxiang Liu, Ning Luo, Samuel Judson, Raj Gautam Dutta, Xiaolong Guo, Mark Santolucito
2024	A*	`conf`	Poster: Enhance Hardware Domain Specific Large Language Model with Reinforcement Learning for Resilience. CCS Weimin Fu, Yifang Zhao, Yier Jin, Xiaolong Guo
2024	J	`jnl`	PowerScout: Security-Oriented Power Delivery Network Modeling for Side-Channel Vulnerability Analysis. IEEE Trans. Emerg. Top. Comput. Huifeng Zhu, Xiaolong Guo, Yier Jin, Xuan Zhang
2023	J	`jnl`	IP-Tag: Tag-Based Runtime 3PIP Hardware Trojan Detection in SoC Platforms. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Kejun Chen, Orlando Arias, Xiaolong Guo, Qingxu Deng, Yier Jin
2023	—	`conf`	LLM4SecHW: Leveraging Domain-Specific Large Language Model for Hardware Debugging. AsianHOST Weimin Fu, Kaichen Yang, Raj Gautam Dutta, Xiaolong Guo, Gang Qu
2023	J	`jnl`	PDNPulse: Sensing PCB Anomaly With the Intrinsic Power Delivery Network. IEEE Trans. Inf. Forensics Secur. Huifeng Zhu, Haoqi Shan, Dean Sullivan, Xiaolong Guo, Yier Jin, Xuan Zhang
2023	J	`jnl`	VGF: Value-Guided Fuzzing - Fuzzing Hardware as Hardware. CoRR Ruochen Dai, Michael Lee, Patrick Hoey, Weimin Fu, Tuba Yavuz, Xiaolong Guo, Shuo Wang, Dean Sullivan, Orlando Arias
2022	J	`jnl`	EM Side Channels in Hardware Security: Attacks and Defenses. IEEE Des. Test Jiaji He, Xiaolong Guo, Mark Tehranipoor, Apostol Vassilev, Yier Jin
2022	J	`jnl`	FineDIFT: Fine-Grained Dynamic Information Flow Tracking for Data-Flow Integrity Using Coprocessor. IEEE Trans. Inf. Forensics Secur. Kejun Chen, Orlando Arias, Qingxu Deng, Daniela Oliveira, Xiaolong Guo, Yier Jin
2022	—	`conf`	Graph Neural Network based Hardware Trojan Detection at Intermediate Representative for SoC Platforms. ACM Great Lakes Symposium on VLSI Weimin Fu, Honggang Yu, Orlando Arias, Kaichen Yang, Yier Jin, Tuba Yavuz, Xiaolong Guo
2022	A	`conf`	Inter-IP Malicious Modification Detection through Static Information Flow Tracking. DATE Zhaoxiang Liu, Orlando Arias, Weimin Fu, Yier Jin, Xiaolong Guo
2022	J	`jnl`	PDNPulse: Sensing PCB Anomaly with the Intrinsic Power Delivery Network. CoRR Huifeng Zhu, Haoqi Shan, Dean Sullivan, Xiaolong Guo, Yier Jin, Xuan Zhang
2022	A	`conf`	RTSEC: Automated RTL Code Augmentation for Hardware Security Enhancement. DATE Orlando Arias, Zhaoxiang Liu, Xiaolong Guo, Yier Jin, Shuo Wang
2022	J	`jnl`	Security Oriented Design Framework for EM Side-Channel Protection in RTL Implementations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jiaji He, Haocheng Ma, Max Panoff, Hanning Wang, Yiqiang Zhao, Leibo Liu, Xiaolong Guo, Yier Jin
2021	—	`conf`	Fuzzing Hardware: Faith or Reality? : Invited Paper. NANOARCH Weimin Fu, Orlando Arias, Yier Jin, Xiaolong Guo
2021	—	`conf`	PCBench: Benchmarking of Board-Level Hardware Attacks and Trojans. ASP-DAC Huifeng Zhu, Xiaolong Guo, Yier Jin, Xuan Zhang
2021	A*	`conf`	Quantifying Rowhammer Vulnerability for DRAM Security. DAC Yichen Jiang, Huifeng Zhu, Dean Sullivan, Xiaolong Guo, Xuan Zhang, Yier Jin
2021	—	`conf`	TRRScope: Understanding Target Row Refresh Mechanism for Modern DDR Protection. HOST Yichen Jiang, Huifeng Zhu, Haoqi Shan, Xiaolong Guo, Xuan Zhang, Yier Jin
2021	Misc	`conf`	Towards scalable, secure, and smart mission-critical IoT systems: review and vision. EMSOFT Xiaolong Guo, Song Han, X. Sharon Hu, Xun Jiao, Yier Jin, Fanxin Kong, Michael Lemmon
2020	—	`conf`	A Formal Framework for Gate- Level Information Leakage Using Z3. AsianHOST Qizhi Zhang, Jiaji He, Yiqiang Zhao, Xiaolong Guo
2020	—	`conf`	Design for EM Side-Channel Security through Quantitative Assessment of RTL Implementations. ASP-DAC Jiaji He, Haocheng Ma, Xiaolong Guo, Yiqiang Zhao, Yier Jin
2020	—	`conf`	PowerScout: A Security-Oriented Power Delivery Network Modeling Framework for Cross-Domain Side-Channel Analysis. AsianHOST Huifeng Zhu, Xiaolong Guo, Yier Jin, Xuan Zhang
2020	A*	`conf`	Runtime Trust Evaluation and Hardware Trojan Detection Using On-Chip EM Sensors. DAC Jiaji He, Xiaolong Guo, Haocheng Ma, Yanjiang Liu, Yiqiang Zhao, Yier Jin
2019	—	`conf`	Hardware and Software Co-Verification from Security Perspective. MTV Kejun Chen, Qingxu Deng, Yumin Hou, Yier Jin, Xiaolong Guo
2019	—	`conf`	QIF-Verilog: Quantitative Information-Flow based Hardware Description Languages for Pre-Silicon Security Assessment. HOST Xiaolong Guo, Raj Gautam Dutta, Jiaji He, Mark Tehranipoor, Yier Jin
2019	J	`jnl`	SoC interconnection protection through formal verification. Integr. Jiaji He, Xiaolong Guo, Travis Meade, Raj Gautam Dutta, Yiqiang Zhao, Yier Jin
2019	A	`conf`	When Capacitors Attack: Formal Method Driven Design and Detection of Charge-Domain Trojans. DATE Xiaolong Guo, Huifeng Zhu, Yier Jin, Xuan Zhang
2017	J	`jnl`	Automatic Code Converter Enhanced PCH Framework for SoC Trust Verification. IEEE Trans. Very Large Scale Integr. Syst. Xiaolong Guo, Raj Gautam Dutta, Prabhat Mishra, Yier Jin
2017	J	`jnl`	Data Secrecy Protection Through Information Flow Tracking in Proof-Carrying Hardware IP - Part I: Framework Fundamentals. IEEE Trans. Inf. Forensics Secur. Yier Jin, Xiaolong Guo, Raj Gautam Dutta, Mohammad-Mahdi Bidmeshki, Yiorgos Makris
2017	J	`jnl`	Data Secrecy Protection Through Information Flow Tracking in Proof-Carrying Hardware IP - Part II: Framework Automation. IEEE Trans. Inf. Forensics Secur. Mohammad-Mahdi Bidmeshki, Xiaolong Guo, Raj Gautam Dutta, Yier Jin, Yiorgos Makris
2017	J	`jnl`	Eliminating the Hardware-Software Boundary: A Proof-Carrying Approach for Trust Evaluation on Computer Systems. IEEE Trans. Inf. Forensics Secur. Xiaolong Guo, Raj Gautam Dutta, Yier Jin
2017	A*	`conf`	Estimation of Safe Sensor Measurements of Autonomous System Under Attack. DAC Raj Gautam Dutta, Xiaolong Guo, Teng Zhang, Kevin A. Kwiat, Charles A. Kamhoua, Laurent Njilla, Yier Jin
2017	J	`jnl`	Hardware Trojan Detection Through Chip-Free Electromagnetic Side-Channel Statistical Analysis. IEEE Trans. Very Large Scale Integr. Syst. Jiaji He, Yiqiang Zhao, Xiaolong Guo, Yier Jin
2017	—	`conf`	PCH framework for IP runtime security verification. AsianHOST Xiaolong Guo, Raj Gautam Dutta, Jiaji He, Yier Jin
2016	—	`conf`	Automatic RTL-to-Formal Code Converter for IP Security Formal Verification. MTV Xiaolong Guo, Raj Gautam Dutta, Prabhat Mishra, Yier Jin
2016	—	`conf`	Quantifying trust in autonomous system under uncertainties. SoCC Raj Gautam Dutta, Xiaolong Guo, Yier Jin
2016	—	`conf`	Scalable SoC trust verification using integrated theorem proving and model checking. HOST Xiaolong Guo, Raj Gautam Dutta, Prabhat Mishra, Yier Jin
2015	—	`conf`	Hierarchy-Preserving Formal Verification Methods for Pre-silicon Security Assurance. MTV Xiaolong Guo, Raj Gautam Dutta, Yier Jin
2015	A*	`conf`	Pre-silicon security verification and validation: a formal perspective. DAC Xiaolong Guo, Raj Gautam Dutta, Yier Jin, Farimah Farahmandi, Prabhat Mishra