Xiaole Cui

82 papers A* 1A 4B 3C 5Journal 34Unranked 35
YearRankTypeTitle / Venue / Authors
2026 J jnl
A Joint Data Transmission Scheme With Improved CAC for 3D-SICs Based on Multiple TSV Subarrays.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Huan Yang, Xiaole Cui, Chen Wei, Juncheng Pu, Zhaohong Lin, Xing Zhang
2026 J jnl
A Reconfigurable Built-In Self-Test Scheme for the Evaluation Circuits of Digital SRAM-IMC Architectures.
IEEE Trans. Very Large Scale Integr. Syst.
Sunrui Zhang, Xiaole Cui, Feng Wei, Xing Zhang
2026 J jnl
An On-Line BISD Triggering Scheme Based on the CAC-Compatible Error Detection Code for TSV Array.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Chen Wei, Xiaole Cui, Huan Yang, Xing Zhang
2026 J jnl
MarchGen: A March Sequence Generation Method for Faults With an Arbitrary Number of Operations in RAMs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Sunrui Zhang, Xiaole Cui, Huixian Huang, Feng Wei, Yongliang Chen, Xing Zhang
2025 J jnl
A Network-Coding-Based Functional Test Method for Routers in 3-D Mesh NoCs.
IEEE Internet Things J.
Chen Wei, Xiaole Cui
2025 B conf
A UCIe Compatible Repair Scheme for the Clustered Faults in the Hexagonal Array of Interconnect Lanes.
ETS
Zhaohong Lin, Xiaole Cui, Juncheng Pu, Huan Yang
2025 J jnl
A VC Dimension-Oriented Improvement Method of PUFs for the Anti-Modeling-Attack Capability.
ACM Trans. Embed. Comput. Syst.
Yongliang Chen, Xiaole Cui, Sunrui Zhang, Xiaoxin Cui
2025 J jnl
FNS-CATF-CAC: An Efficient Crosstalk Avoidance Code to Reduce the Switching Activity in TSV Arrays.
IEEE Trans. Reliab.
Chen Wei, Xiaole Cui
2025 C conf
In-Memory Logic Synthesis Methods based on Read Decoupled 8T and Transpose 11T SRAMs.
ISCAS
Feng Wei, Xiaole Cui, Sunrui Zhang
2025 — conf
The Low-Latency UCIe-Compliant Spiral Layouts of TSV Arrays Against the Clustered Faults.
ATS
Bowen Tan, Xiaole Cui, Zhaohong Lin
2024 — conf
A Convolutional Spiking Neural Network Accelerator with the Sparsity-Aware Memory and Compressed Weights.
ASAP
Hanqing Liu, Xiaole Cui, Sunrui Zhang, Mingqi Yin, Yuanyuan Jiang, Xiaoxin Cui
2024 — conf
A High Performance PODEM Algorithm with the Improved Backtrace Process.
ITC-Asia
Yang Zeng, Xiaole Cui
2024 — conf
A Testability Improvement Method of Combinational Circuits Based on the SDC Conditions.
ATS
Yang Zeng, Xiaole Cui
2024 J jnl
A reconfigurable FPGA-based spiking neural network accelerator.
Microelectron. J.
Mingqi Yin, Xiaole Cui, Feng Wei, Hanqing Liu, Yuanyuan Jiang, Xiaoxin Cui
2024 J jnl
An 11T SRAM Cell for the Dual-Direction In-Array Logic/CAM Operations.
IEEE Trans. Circuits Syst. II Express Briefs
Feng Wei, Xiaole Cui, Sunrui Zhang, Xing Zhang
2024 J jnl
An in-Array Build-In Self-Test Scheme for Embedded SRAM Array.
IEEE Trans. Circuits Syst. II Express Briefs
Feng Wei, Xiaole Cui, Sunrui Zhang
2024 J jnl
Dy-MFNS-CAC: An Encoding Mechanism to Suppress the Crosstalk and Repair the Hard Faults in Rectangular TSV Arrays.
IEEE Trans. Reliab.
Chen Wei, Xiaole Cui, Xiaoxin Cui
2024 A conf
Modeling Attack Tests and Security Enhancement of the Sub-Threshold Voltage Divider Array PUF.
DATE
Shengjie Zhou, Yongliang Chen, Xiaole Cui, Yun Liu
2024 C conf
SPAT: FPGA-based Sparsity-Optimized Spiking Neural Network Training Accelerator with Temporal Parallel Dataflow.
ISCAS
Yuanyuan Jiang, Li Lun, Jiawei Wang, Mingqi Yin, Hanqing Liu, Zhenhui Dai, Xiaole Cui, Xiaoxin Cui
2024 J jnl
The Resistance Analysis Attack and Security Enhancement of the IMC LUT Based on the Complementary Resistive Switch Cells.
ACM Trans. Design Autom. Electr. Syst.
Xiaole Cui, Mingqi Yin, Hanqing Liu, Xiaoxin Cui
2024 J jnl
The area-efficient gate level information flow tracking schemes of digital circuit with multi-level security lattice.
Microelectron. J.
Yongliang Chen, Xiaole Cui, Xiaoxin Cui, Xing Zhang
2023 A conf
An Anti-Removal-Attack Hardware Watermarking Method Based on Polymorphic Gates.
ICCAD
Yongliang Chen, Xiaole Cui, Pengyuan Yang, Gang Qu
2023 J jnl
An Area-Efficient In-Memory Implementation Method of Arbitrary Boolean Function Based on SRAM Array.
IEEE Trans. Computers
Sunrui Zhang, Xiaole Cui, Feng Wei, Xiaoxin Cui
2023 J jnl
An Evaluation Method of the Anti-Modeling-Attack Capability of PUFs.
IEEE Trans. Inf. Forensics Secur.
Yongliang Chen, Xiaole Cui, Yun Liu, Xiaoxin Cui
2023 J jnl
Mosaic-3C1S: A Low Overhead Crosstalk Suppression Scheme for Rectangular TSV Array.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Xiaole Cui, Chen Wei, Xu Feng, Xiaoxin Cui
2022 J jnl
A Global Self-Repair Method for TSV Arrays With Adaptive FNS-CAC Codec.
IEEE Des. Test
Chen Wei, Xiaole Cui, Xiaoxin Cui
2022 — conf
A Modeling Attack on the Sub-threshold Current Array PUF.
HOST
Yun Liu, Yongliang Chen, Xiaole Cui
2022 C conf
An Area-Efficient and Robust Memristive LUT Based on the Enhanced Scouting Logic Cells.
ISCAS
Xiaole Cui, Fan Liu, Sunrui Zhang, Xiaoxin Cui
2022 — conf
An obfuscation scheme of scan chain to protect the cryptographic chips.
ATS
Huixian Huang, Xiaole Cui, Shuming Zhang, Ge Li, Xiaoxin Cui
2022 B conf
The Design Method of Logic Circuits based on the Voltage-Input Enhanced Scouting Logic Gates.
FPL
Fan Liu, Sunrui Zhang, Xiaole Cui
2021 J jnl
28nm asynchronous area-saving AES processor with high Common and Machine learning side-channel attack resistance.
IEICE Electron. Express
Qingyun Zou, Xiaoxin Cui, Zhenhui Dai, Yisong Kuang, Yi Zhong, Chenglong Zou, Xiaole Cui
2021 B conf
An SNN-Based and Neuromorphic-Hardware-Implementable Noise Filter with Self-adaptive Time Window for Event-Based Vision Sensor.
IJCNN
Kanglin Xiao, Xiaoxin Cui, Kefei Liu, Xiaole Cui, Xin'an Wang
2021 — conf
Design and Implementation of Full Adder in One-Transistor-One-Resistor RRAM Array.
ASICON
Xiangyu Zhang, Feng Wei, Xiaoyan Liu, Xiaole Cui
2021 J jnl
Machine Learning Aided Key-Guessing Attack Paradigm Against Logic Block Encryption.
J. Comput. Sci. Technol.
Yi Zhong, Jianhua Feng, Xiaoxin Cui, Xiaole Cui
2021 — conf
The ANN Based Modeling Attack and Security Enhancement of the Double-layer PUF.
ITC-Asia
Xiaole Cui, Yongliang Chen, Wenqiang Ye, Xiaoxin Cui
2021 — conf
The Modeling Attack and Security Enhancement of the XbarPUF with Both Column Swapping and XORing.
ACM Great Lakes Symposium on VLSI
Yongliang Chen, Xiaole Cui, Wenqiang Ye, Xiaoxin Cui
2021 A conf
The Security Enhancement Techniques of the Double-layer PUF Against the ANN-based Modeling Attack.
ITC
Yongliang Chen, Xiaole Cui, Wenqiang Ye, Xiaoxin Cui
2021 J jnl
The Synthesis Method of Logic Circuits Based on the NMOS-Like RRAM Gates.
IEEE Access
Xiaole Cui, Ye Ma, Feng Wei, Xiaoxin Cui
2021 — conf
The logic obfuscation of LFSR with the crosstalk based polymorphic gate.
AsianHOST
Yuqian Sun, Xiaole Cui, Yongliang Chen, Xiaoxin Cui
2020 — conf
A Testability Enhancement Method for the Memristor Ratioed Logic Circuits.
ATS
Li Qu, Xiaole Cui, Xiaoxin Cui
2020 J jnl
A synthesis method for logic circuits in RRAM arrays.
Sci. China Inf. Sci.
Xiaole Cui, Xiao Ma, Feng Wei, Xiaoxin Cui
2020 J jnl
Design of High-Speed Logic Circuits with Four-Step RRAM-Based Logic Gates.
Circuits Syst. Signal Process.
Xiaole Cui, Xiao Ma, Qiujun Lin, Xiang Li, Hang Zhou, Xiaoxin Cui
2020 A* conf
ReTriple: Reduction of Redundant Rendering on Android Devices for Performance and Energy Optimizations.
DAC
Xianfeng Li, Gengchao Li, Xiaole Cui
2020 J jnl
The synthesis method of logic circuits based on the iMemComp gates.
Integr.
Xiaole Cui, Qiujun Lin, Xiaoxin Cui, Feng Wei, Xiaoyan Liu, Jinfeng Kang
2019 J jnl
Efficient evaluation model including interconnect resistance effect for large scale RRAM crossbar array matrix computing.
Sci. China Inf. Sci.
Runze Han, Peng Huang, Yudi Zhao, Xiaole Cui, Xiaoyan Liu, Jinfeng Kang
2019 — conf
Flash-based Computing in-Memory Scheme for IOT.
ASICON
Jinfeng Kang, Peng Huang, Runze Han, Yachen Xiang, Xiaole Cui, Xiaoyan Liu
2018 — conf
A Novel Polymorphic Gate Based Circuit Fingerprinting Technique.
ACM Great Lakes Symposium on VLSI
Tian Wang, Xiaoxin Cui, Dunshan Yu, Omid Aramoon, Timothy Dunlap, Gang Qu, Xiaole Cui
2018 J jnl
Design of Low-Power High-Performance FinFET Standard Cells.
Circuits Syst. Signal Process.
Tian Wang, Xiaoxin Cui, Kai Liao, Nan Liao, Dunshan Yu, Xiaole Cui
2018 J jnl
Evaluation of Dynamic-Adjusting Threshold-Voltage Scheme for Low-Power FinFET Circuits.
IEEE Trans. Very Large Scale Integr. Syst.
Tian Wang, Xiaoxin Cui, Yewen Ni, Dunshan Yu, Xiaole Cui
2018 — conf
Polymorphic gate based IC watermarking techniques.
ASP-DAC
Tian Wang, Xiaoxin Cui, Dunshan Yu, Omid Aramoon, Timothy Dunlap, Gang Qu, Xiaole Cui
2017 — conf
A Heuristic Algorithm for Automatic Generation of March Tests.
ATS
Xiaole Cui, Yichi Luo, Qiujun Lin, Xiaoxin Cui
2017 — conf
A design of high performance full adder with memristors.
ASICON
Kuimin Zhang, Xiaole Cui, Xiaoxin Cui
2017 — conf
A new calibration method for MEMS accelerometers with genetic algorithm.
RCAR
Xiaole Cui, Chunliang Liu, Guangyi Shi, Yufeng Jin
2017 — conf
A practical cold boot attack on RSA private keys.
AsianHOST
Tian Wang, Xiaoxin Cui, Yewen Ni, Dunshan Yu, Xiaole Cui, Gang Qu
2017 — conf
A signal noise separation method for the instant mixing linear and nonlinear circuits with MISEP algorithm.
ASICON
Liwen Zhu, Xiaole Cui, Xiang Li, Xiaoxin Cui
2017 J jnl
An Enhancement of Crosstalk Avoidance Code Based on Fibonacci Numeral System for Through Silicon Vias.
IEEE Trans. Very Large Scale Integr. Syst.
Xiaole Cui, Xiaoxin Cui, Yewen Ni, Min Miao, Yufeng Jin
2017 — conf
Design of router for spiking neural networks.
ASICON
Yewen Ni, Xiaoxin Cui, Yuanning Fan, Qiankun Han, Kefei Liu, Xiaole Cui
2017 J jnl
High-Performance Noninvasive Side-Channel Attack Resistant ECC Coprocessor for GF(2m ).
IEEE Trans. Ind. Electron.
Kai Liao, Xiaoxin Cui, Nan Liao, Tian Wang, Dunshan Yu, Xiaole Cui
2017 J jnl
Improving DFA attacks on AES with unknown and random faults.
Sci. China Inf. Sci.
Nan Liao, Xiaoxin Cui, Kai Liao, Tian Wang, Dunshan Yu, Xiaole Cui
2017 — conf
Improving DFA on AES using all-fault ciphertexts.
ASICON
Yewen Ni, Xiaoxin Cui, Tian Wang, Yuanning Fan, Qiankun Han, Kefei Liu, Xiaole Cui
2017 J jnl
Testing of 1T
Sci. China Inf. Sci.
Xiaole Cui, Qiang Zhang, Xiaoxin Cui, Xin'an Wang, Jinfeng Kang, Xiaoyan Liu
2016 J jnl
A snake addressing scheme for phase change memory testing.
Sci. China Inf. Sci.
Xiaole Cui, Zuolin Cheng, Chung-Len Lee, Xinnan Lin, Yiqun Wei, Xiaogang Chen, Zhitang Song
2016 J jnl
Low Power High Performance FinFET Standard Cells Based on Mixed Back Biasing Technology.
IEICE Trans. Electron.
Tian Wang, Xiaoxin Cui, Kai Liao, Nan Liao, Xiaole Cui, Dunshan Yu
2016 J jnl
Ultralow-power high-speed flip-flop based on multimode FinFETs.
Sci. China Inf. Sci.
Kai Liao, Xiaoxin Cui, Nan Liao, Tian Wang, Dunshan Yu, Xiaole Cui
2015 — conf
A TSV repair method for clustered faults.
ASICON
Shijie Zhang, Xiaole Cui, Qiang Zhang, Yufeng Jin
2015 — conf
A countermeasure for power analysis to scalar multiplication of ECC hardware.
ASICON
Lifei Liu, Xiaole Cui, Yalin Ran, Xiaoxin Cui
2015 — conf
A high-efficient and accurate fault model aiming at FPGA-based AES cryptographic applications.
ASICON
Nan Liao, Xiaoxin Cui, Tian Wang, Kai Liao, Yewen Ni, Dunshan Yu, Xiaole Cui
2015 — conf
An enhanced decoder for multiple-bit error correcting BCH codes.
ASICON
Hupo Wei, Xiaole Cui, Qiang Zhang, Yufeng Jin
2015 C conf
Context-adaptive fast motion estimation of HEVC.
ISCAS
Xufeng Li, Ronggang Wang, Xiaole Cui, Wenmin Wang
2015 — conf
Employing the mixed FBB/RBB in the design of FinFET logic gates.
ASICON
Tian Wang, Xiaoxin Cui, Kai Liao, Nan Liao, Yewen Ni, Dunshan Yu, Xiaole Cui
2015 — conf
Post-bond test for TSVs using voltage division.
ASICON
Bingqiang Jing, Xiaole Cui, Yalin Ran, Yufeng Jin
2015 J jnl
Self-heating burn-in pattern generation based on the genetic algorithm incorporated with a BACK-like procedure.
IET Comput. Digit. Tech.
Zuolin Cheng, Xiaole Cui, Xiaoxin Cui, Chung Len Lee
2013 C conf
A UWB mixer with a balanced wide band active balun using crossing centertaped inductor.
ISCAS
Xiangrong Zhang, Xiaole Cui, Bo Wang, Chung Len Lee
2013 — conf
A folded current-reused CMOS power amplifier for low-voltage 3.0-5.0 GHz UWB applications.
ASICON
Zhengyu Qian, Xiaole Cui, Bo Wang, Xiangrong Zhang, Chung Len Lee
2013 — conf
A novel test scheme for NAND flash memory based on built-in oscillator ring.
ASICON
Si Chen, Xiaole Cui, Chung Len Lee
2013 — conf
A test pattern selection method for dynamic burn-in of logic circuits based on ATPG technique.
ASICON
Xuan Yang, Xiaole Cui, Chao Wang, Chung Len Lee
2013 — conf
AHardware implementation of DES with combined countermeasure against DPA.
ASICON
Xiaoxin Cui, Rui Li, Wei Wei, Juan Gu, Xiaole Cui
2013 — conf
Enhanced error correction against multiple-bit-upset based on BCH code for SRAM.
ASICON
Weijia Ma, Xiaole Cui, Chung Len Lee
2013 — conf
New DfT architectures for 3D-SICs with a wireless test port.
ASICON
Yibo He, Xiaole Cui, Chung Len Lee, Xiaoxin Cui, Yufeng Jin
2012 A conf
Modeling and testing of interference faults in the nano NAND Flash memory.
DATE
Jin Zha, Xiaole Cui, Chung Len Lee
2008 — conf
Towards HMM based human motion recognition using MEMS inertial sensors.
ROBIO
Guangyi Shi, Yuexian Zou, Yufeng Jin, Xiaole Cui, Wen Jung Li
2006 — conf
Design and Implementation of a 2-level FSK Digital Modems Using CORDIC Algorithm.
APCCAS
Xiaoxin Cui, Dunshan Yu, Shimin Sheng, Xiaole Cui