Xiaohua Kong - RankMe

11 papers C 1Journal 2Unranked 8

Year	Rank	Type	Title / Venue / Authors
2019	—	`conf`	Analog/Mixed-Signal Design Challenges in 7-nm CMOS and Beyond. CICC Alvin Leng Sun Loke, Da Yang, Tin Tin Wee, Jonathan L. Holland, Patrick Isakanian, Kern Rim, Sam Yang, Jacob S. Schneider, Giri Nallapati, Sreeker Dundigal, Hasnain Lakdawala, Behnam Amelifard, Chulkyu Lee, Betty McGovern, Paul S. Holdaway, Xiaohua Kong, Burton M. Leary
2018	—	`conf`	Analog/mixed-signal design challenges in 7-nm CMOS and beyond. CICC Alvin Leng Sun Loke, Da Yang, Tin Tin Wee, Jonathan L. Holland, Patrick Isakanian, Kern Rim, Sam Yang, Jacob S. Schneider, Giri Nallapati, Sreeker Dundigal, Hasnain Lakdawala, Behnam Amelifard, Chulkyu Lee, Betty McGovern, Paul S. Holdaway, Xiaohua Kong, Burton M. Leary
2009	—	`conf`	Parallel flow to analyze the impact of the voltage regulator model in nanoscale power distribution network. ISQED Amirali Shayan Arani, Xiang Hu, He Peng, Wenjian Yu, Wanping Zhang, Chung-Kuan Cheng, Mikhail Popovich, Xiaoming Chen, Lew Chua-Eoan, Xiaohua Kong
2006	J	`jnl`	Semihiding operators and active-edge specification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Xiaohua Kong, Radu Negulescu
2004	—	`conf`	Bolstering Faith in GasP Circuits through Formal Verification. ASYNC Xiaohua Kong, Radu Negulescu
2004	—	`conf`	High-Speed Reduced Stack Dual Lock Circuits. ASYNC Nisrine Saadallah, Xiaohua Kong, Radu Negulescu
2003	J	`jnl`	Refinement-based formal verification with heterogeneous timing. Int. J. Softw. Tools Technol. Transf. Xiaohua Kong, Radu Negulescu, Larry Weidong Ying
2001	C	`conf`	Formal Verification of Peephole Optimizations in Asynchronous Circuits. FORTE Xiaohua Kong, Radu Negulescu
2001	—	`conf`	Formal verification of pulse-mode asynchronous circuits. ASP-DAC Xiaohua Kong, Radu Negulescu
2001	—	`conf`	Refinement-Based Formal Verification of Asynchronous Wrappers for Independently Clocked Domains in Systems on Chip. CHARME Xiaohua Kong, Radu Negulescu, Larry Weidong Ying
2001	—	`conf`	Semi-Hiding Operators and the Analysis of Active-Edge Specifications for Digital Circuits. ACSD Radu Negulescu, Xiaohua Kong

Kai Greshake, Sahar Abdelnabi, Shailesh Mishra, Christoph Endres, Thorsten Holz, Mario Fritz