Xiaoheng Chen

11 papers A 1Misc 1Journal 8Unranked 1
YearRankTypeTitle / Venue / Authors
2013 J jnl
A Simplified Min-Sum Decoding Algorithm for Non-Binary LDPC Codes.
IEEE Trans. Commun.
Chung-Li Wang, Xiaoheng Chen, Zongwang Li, Shaohua Yang
2012 J jnl
A Simplified Min-Sum Decoding Algorithm for Non-Binary LDPC Codes
CoRR
Chung-Li Wang, Xiaoheng Chen, Zongwang Li, Shaohua Yang
2012 J jnl
Efficient Configurable Decoder Architecture for Nonbinary Quasi-Cyclic LDPC Codes.
IEEE Trans. Circuits Syst. I Regul. Pap.
Xiaoheng Chen, Shu Lin, Venkatesh Akella
2012 Misc conf
Exploiting the shift property of structured LDPC codes for reduced-complexity sliced message passing based decoder design.
ICNC
Xiaoheng Chen, Chung-Li Wang
2012 J jnl
High-Throughput Efficient Non-Binary LDPC Decoder Based on the Simplified Min-Sum Algorithm.
IEEE Trans. Circuits Syst. I Regul. Pap.
Xiaoheng Chen, Chung-Li Wang
2011 J jnl
Exploiting data-level parallelism for energy-efficient implementation of LDPC decoders and DCT on an FPGA.
ACM Trans. Reconfigurable Technol. Syst.
Xiaoheng Chen, Venkatesh Akella
2011 J jnl
Hardware Implementation of a Backtracking-Based Reconfigurable Decoder for Lowering the Error Floor of Quasi-Cyclic LDPC Codes.
IEEE Trans. Circuits Syst. I Regul. Pap.
Xiaoheng Chen, Jingyu Kang, Shu Lin, Venkatesh Akella
2011 J jnl
Memory System Optimization for FPGA-Based Implementation of Quasi-Cyclic LDPC Codes Decoders.
IEEE Trans. Circuits Syst. I Regul. Pap.
Xiaoheng Chen, Jingyu Kang, Shu Lin, Venkatesh Akella
2010 J jnl
QSN - A Simple Circular-Shift Network for Reconfigurable Quasi-Cyclic LDPC Decoders.
IEEE Trans. Circuits Syst. II Express Briefs
Xiaoheng Chen, Shu Lin, Venkatesh Akella
2009 A conf
Accelerating FPGA-based emulation of quasi-cyclic LDPC codes with vector processing.
DATE
Xiaoheng Chen, Jingyu Kang, Shu Lin, Venkatesh Akella
2009 — conf
FPGA-based low-complexity high-throughput tri-mode decoder for quasi-cyclic LDPC codes.
Allerton
Xiaoheng Chen, Qin Huang, Shu Lin, Venkatesh Akella