Xiaochen Peng

49 papers A* 4A 5C 6Journal 18Unranked 15
YearRankTypeTitle / Venue / Authors
2026 J jnl
A 3 nm FinFET 125 TOPS/W-29 TFLOPS/W, 90 TOPS/mm
IEEE J. Solid State Circuits
Haruki Mori, Je-Min Hung, Wei-Chang Zhao, Kinshuk Khare, Brian Crafton, Hiroaki Ishii, Cheng-En Lee, Xiaochen Peng, Xiaoyu Sun, Yorinobu Fujino, Chia-Jung Tsen, Vineet Joshi, Chao-Kai Chuang, Takeshi Hashizume, Chia-Fu Lee, Tan-Li Chou, Kerem Akarvardar, Saman Adham, Yih Wang, Hidehiro Fujiwara, Yu-Der Chih, Yen-Huei Chen, Hung-Jen Liao, Tsung-Yung Jonathan Chang
2026 J jnl
Exploration of Algorithm-Hardware Co-Design for Floating-Point Digital Compute-in-Memory.
IEEE Comput. Archit. Lett.
Xiaochen Peng, Haruki Mori, Abhiroop Bhattacharjee, Brian Crafton, Hidehiro Fujiwara, Kerem Akarvardar
2026 J jnl
Ultrafast Generative AI by Ultradense 3D Integration: A Case Study on LLM-based Edge Inference.
ACM Trans. Design Autom. Electr. Syst.
Kerem Akarvardar, Xiaoyu Sun, Brian Crafton, Xiaochen Peng, Haruki Mori, Abhiroop Bhattacharjee, Hidehiro Fujiwara, H.-S. Philip Wong
2025 A* conf
Finding the Pareto Frontier of Low-Precision Data Formats and MAC Architecture for LLM Inference.
DAC
Brian Crafton, Xiaochen Peng, Xiaoyu Sun, Ashwin Sanjay Lele, Bo Zhang, Win-San Khwa, Kerem Akarvardar
2024 — conf
34.4 A 3nm, 32.5TOPS/W, 55.0TOPS/mm
ISSCC
Hidehiro Fujiwara, Haruki Mori, Wei-Chang Zhao, Kinshuk Khare, Cheng-En Lee, Xiaochen Peng, Vineet Joshi, Chao-Kai Chuang, Shu-Huan Hsu, Takeshi Hashizume, Toshiaki Naganuma, Chen-Hung Tien, Yao-Yi Liu, Yen-Chien Lai, Chia-Fu Lee, Tan-Li Chou, Kerem Akarvardar, Saman Adham, Yih Wang, Yu-Der Chih, Yen-Huei Chen, Hung-Jen Liao, Tsung-Yung Jonathan Chang
2024 — conf
Co-Optimization for Robust Power Delivery Design in 3D-Heterogeneous Integration of Compute In-Memory Accelerators.
VLSI Technology and Circuits
Ankit Kaul, Madison Manley, James Read, Yandong Luo, Xiaochen Peng, Shimeng Yu, Muhannad S. Bakir
2024 J jnl
Estimating Power, Performance, and Area for On-Sensor Deployment of AR/VR Workloads Using an Analytical Framework.
ACM Trans. Design Autom. Electr. Syst.
Xiaoyu Sun, Xiaochen Peng, Sai Qian Zhang, Jorge Gomez, Win-San Khwa, Syed Shakib Sarwar, Ziyun Li, Weidong Cao, Zhao Wang, Chiao Liu, Meng-Fan Chang, Barbara De Salvo, Kerem Akarvardar, H.-S. Philip Wong
2024 A conf
Non-volatile Memory Technologies for Edge AI Applications.
ICCAD
Xiaoyu Sun, Win-San Khwa, Xiaochen Peng, Meng-Fan Chang, Kerem Akarvardar
2022 J jnl
Achieving High In Situ Training Accuracy and Energy Efficiency with Analog Non-Volatile Synaptic Devices.
ACM Trans. Design Autom. Electr. Syst.
Shanshi Huang, Xiaoyu Sun, Xiaochen Peng, Hongwu Jiang, Shimeng Yu
2022 — —
Benchmark Framework for 2-D/3-D Integrated Compute-in-Memory Based Machine Learning Accelerator.
Xiaochen Peng
2021 A conf
A Runtime Reconfigurable Design of Compute-in-Memory based Hardware Accelerator.
DATE
Anni Lu, Xiaochen Peng, Yandong Luo, Shanshi Huang, Shimeng Yu
2021 J jnl
A Runtime Reconfigurable Design of Compute-in-Memory-Based Hardware Accelerator for Deep Learning Inference.
ACM Trans. Design Autom. Electr. Syst.
Anni Lu, Xiaochen Peng, Yandong Luo, Shanshi Huang, Shimeng Yu
2021 — conf
Compute-in-Memory: From Device Innovation to 3D System Integration.
ESSDERC
Shimeng Yu, Wonbo Shim, Jae Hur, Yuan-Chun Luo, Gihun Choe, Wantong Li, Anni Lu, Xiaochen Peng
2021 — conf
Compute-in-RRAM with Limited On-chip Resources.
AICAS
Anni Lu, Xiaochen Peng, Shimeng Yu
2021 C conf
Cryogenic Performance for Compute-in-Memory Based Deep Neural Network Accelerator.
ISCAS
Panni Wang, Xiaochen Peng, Wriddhi Chakraborty, Asif Khan, Suman Datta, Shimeng Yu
2021 J jnl
DNN+NeuroSim V2.0: An End-to-End Benchmarking Framework for Compute-in-Memory Accelerators for On-Chip Training.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Xiaochen Peng, Shanshi Huang, Hongwu Jiang, Anni Lu, Shimeng Yu
2021 C conf
Exploiting Process Variations to Protect Machine Learning Inference Engine from Chip Cloning.
ISCAS
Shanshi Huang, Xiaochen Peng, Hongwu Jiang, Yandong Luo, Shimeng Yu
2021 — conf
Impact of Multilevel Retention Characteristics on RRAM based DNN Inference Engine.
IRPS
Wonbo Shim, Jian Meng, Xiaochen Peng, Jae-sun Seo, Shimeng Yu
2021 J jnl
NeuroSim Simulator for Compute-in-Memory Hardware Accelerator: Validation and Benchmark.
Frontiers Artif. Intell.
Anni Lu, Xiaochen Peng, Wantong Li, Hongwu Jiang, Shimeng Yu
2021 — conf
NeuroSim Validation with 40nm RRAM Compute-in-Memory Macro.
AICAS
Anni Lu, Xiaochen Peng, Wantong Li, Hongwu Jiang, Shimeng Yu
2021 J jnl
RRAM for Compute-in-Memory: From Inference to Training.
IEEE Trans. Circuits Syst. I Regul. Pap.
Shimeng Yu, Wonbo Shim, Xiaochen Peng, Yandong Luo
2021 J jnl
Secure XOR-CIM Engine: Compute-In-Memory SRAM Architecture With Embedded XOR Encryption.
IEEE Trans. Very Large Scale Integr. Syst.
Shanshi Huang, Hongwu Jiang, Xiaochen Peng, Wantong Li, Shimeng Yu
2021 J jnl
Structured Pruning of RRAM Crossbars for Efficient In-Memory Computing Acceleration of Deep Neural Networks.
IEEE Trans. Circuits Syst. II Express Briefs
Jian Meng, Li Yang, Xiaochen Peng, Shimeng Yu, Deliang Fan, Jae-sun Seo
2021 — conf
Thermal Reliability Considerations of Resistive Synaptic Devices for 3D CIM System Performance.
3DIC
Ankit Kaul, Yandong Luo, Xiaochen Peng, Shimeng Yu, Muhannad S. Bakir
2020 A* conf
A Two-way SRAM Array based Accelerator for Deep Neural Network On-chip Training.
DAC
Hongwu Jiang, Shanshi Huang, Xiaochen Peng, Jian-Wei Su, Yen-Chi Chou, Wei-Hsing Huang, Ta-Wei Liu, Ruhui Liu, Meng-Fan Chang, Shimeng Yu
2020 C conf
A Variation Robust Inference Engine Based on STT-MRAM with Parallel Read-Out.
ISCAS
Yandong Luo, Xiaochen Peng, Ryan Hatcher, Titash Rakshit, Jorge Kittl, Mark S. Rodder, Jae-sun Seo, Shimeng Yu
2020 — conf
Architectural Design of 3D NAND Flash based Compute-in-Memory for Inference Engine.
MEMSYS
Wonbo Shim, Hongwu Jiang, Xiaochen Peng, Shimeng Yu
2020 J jnl
Benchmark of the Compute-in-Memory-Based DNN Accelerator With Area Constraint.
IEEE Trans. Very Large Scale Integr. Syst.
Anni Lu, Xiaochen Peng, Yandong Luo, Shimeng Yu
2020 J jnl
CIMAT: A Compute-In-Memory Architecture for On-chip Training Based on Transpose SRAM Arrays.
IEEE Trans. Computers
Hongwu Jiang, Xiaochen Peng, Shanshi Huang, Shimeng Yu
2020 — conf
Compute-in-Memory with Emerging Nonvolatile-Memories: Challenges and Prospects.
CICC
Shimeng Yu, Xiaoyu Sun, Xiaochen Peng, Shanshi Huang
2020 J jnl
DNN+NeuroSim V2.0: An End-to-End Benchmarking Framework for Compute-in-Memory Accelerators for On-chip Training.
CoRR
Xiaochen Peng, Shanshi Huang, Hongwu Jiang, Anni Lu, Shimeng Yu
2020 C conf
MINT: Mixed-Precision RRAM-Based IN-Memory Training Architecture.
ISCAS
Hongwu Jiang, Shanshi Huang, Xiaochen Peng, Shimeng Yu
2020 J jnl
Optimizing Weight Mapping and Data Flow for Convolutional Neural Networks on Processing-in-Memory Architectures.
IEEE Trans. Circuits Syst. I Fundam. Theory Appl.
Xiaochen Peng, Rui Liu, Shimeng Yu
2020 A conf
Overcoming Challenges for Achieving High in-situ Training Accuracy with Emerging Memories.
DATE
Shanshi Huang, Xiaoyu Sun, Xiaochen Peng, Hongwu Jiang, Shimeng Yu
2020 A conf
XOR-CIM: Compute-In-Memory SRAM Architecture with Embedded XOR Encryption.
ICCAD
Shanshi Huang, Hongwu Jiang, Xiaochen Peng, Wantong Li, Shimeng Yu
2019 — conf
CIMAT: a transpose SRAM-based compute-in-memory architecture for deep neural network on-chip training.
MEMSYS
Hongwu Jiang, Xiaochen Peng, Shanshi Huang, Shimeng Yu
2019 A* conf
Design Guidelines of RRAM based Neural-Processing-Unit: A Joint Device-Circuit-Algorithm Analysis.
DAC
Wenqiang Zhang, Xiaochen Peng, Huaqiang Wu, Bin Gao, Hu He, Youhui Zhang, Shimeng Yu, He Qian
2019 — conf
Inference engine benchmarking across technological platforms from CMOS to RRAM.
MEMSYS
Xiaochen Peng, Minkyu Kim, Xiaoyu Sun, Shihui Yin, Titash Rakshit, Ryan M. Hatcher, Jorge A. Kittl, Jae-sun Seo, Shimeng Yu
2019 J jnl
MAX
IEEE J. Emerg. Sel. Topics Circuits Syst.
Manqing Mao, Xiaochen Peng, Rui Liu, Jingtao Li, Shimeng Yu, Chaitali Chakrabarti
2019 — conf
MLP+NeuroSimV3.0: Improving On-chip Learning Performance with Device to Algorithm Optimizations.
ICONS
Yandong Luo, Xiaochen Peng, Shimeng Yu
2019 C conf
Optimizing Weight Mapping and Data Flow for Convolutional Neural Networks on RRAM Based Processing-In-Memory Architecture.
ISCAS
Xiaochen Peng, Rui Liu, Shimeng Yu
2018 — conf
A Versatile ReRAM-based Accelerator for Convolutional Neural Networks.
SiPS
Manqing Mao, Xiaoyu Sun, Xiaochen Peng, Shimeng Yu, Chaitali Chakrabarti
2018 — conf
Benchmark of RRAM based Architectures for Dot-Product Computation.
APCCAS
Xiaochen Peng, Shimeng Yu
2018 C conf
Design Considerations of Selector Device in Cross-Point RRAM Array for Neuromorphic Computing.
ISCAS
Jiyong Woo, Xiaochen Peng, Shimeng Yu
2018 — conf
Fully parallel RRAM synaptic array for implementing binary neural network with (+1, -1) weights and (+1, 0) neurons.
ASP-DAC
Xiaoyu Sun, Xiaochen Peng, Pai-Yu Chen, Rui Liu, Jae-sun Seo, Shimeng Yu
2018 J jnl
NeuroSim: A Circuit-Level Macro Model for Benchmarking Neuro-Inspired Architectures in Online Learning.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Pai-Yu Chen, Xiaochen Peng, Shimeng Yu
2018 A* conf
Parallelizing SRAM arrays with customized bit-cell for binary neural networks.
DAC
Rui Liu, Xiaochen Peng, Xiaoyu Sun, Win-San Khwa, Xin Si, Jia-Jing Chen, Jia-Fang Li, Meng-Fan Chang, Shimeng Yu
2018 J jnl
X-Point PUF: Exploiting Sneak Paths for a Strong Physical Unclonable Function Design.
IEEE Trans. Circuits Syst. I Regul. Pap.
Rui Liu, Pai-Yu Chen, Xiaochen Peng, Shimeng Yu
2018 A conf
XNOR-RRAM: A scalable and parallel resistive synaptic architecture for binary neural networks.
DATE
Xiaoyu Sun, Shihui Yin, Xiaochen Peng, Rui Liu, Jae-sun Seo, Shimeng Yu