Xianlong Hong - RankMe

258 papers A* 8A 7B 1C 18Misc 1Journal 77Unranked 146

Year	Rank	Type	Title / Venue / Authors
2011	J	`jnl`	Leakage-Aware TSV-Planning with Power-Temperature-Delay Dependence in 3D ICs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Kan Wang, Sheqin Dong, Yuchun Ma, Yu Wang, Xianlong Hong, Jason Cong
2011	—	`conf`	Rethinking thermal via planning with timing-power-temperature dependence for 3D ICs. ASP-DAC Kan Wang, Yuchun Ma, Sheqin Dong, Yu Wang, Xianlong Hong, Jason Cong
2010	J	`jnl`	An Effective Gated Clock Tree Design Based on Activity and Register Aware Placement. IEEE Trans. Very Large Scale Integr. Syst. Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu
2010	J	`jnl`	ECP- and CMP-Aware Detailed Routing Algorithm for DFM. IEEE Trans. Very Large Scale Integr. Syst. Yin Shen, Qiang Zhou, Yici Cai, Xianlong Hong
2010	J	`jnl`	Effective congestion reduction for IC package substrate routing. ACM Trans. Design Autom. Electr. Syst. Shenghua Liu, Guoqiang Chen, Tom Tong Jing, Lei He, Robi Dutta, Xianlong Hong
2010	J	`jnl`	Efficient Power Network Analysis with Modeling of Inductive Effects. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Shan Zeng, Wenjian Yu, Xianlong Hong, Chung-Kuan Cheng
2010	—	`conf`	PS-FPG: pattern selection based co-design of floorplan and power/ground network with wiring resource optimization. ASP-DAC Li Li, Yuchun Ma, Ning Xu, Yu Wang, Xianlong Hong
2010	—	`conf`	Simultaneous slack budgeting and retiming for synchronous circuits optimization. ASP-DAC Shenghua Liu, Yuchun Ma, Xianlong Hong, Yu Wang
2010	J	`jnl`	Thermal Impacts of Leakage Power in 2D/3D floorplanning. J. Circuits Syst. Comput. Yuchun Ma, Qiang Zhou, Pingqiang Zhou, Xianlong Hong
2009	—	`conf`	A novel thermal optimization flow using incremental floorplanning for 3D ICs. ASP-DAC Xin Li, Yuchun Ma, Xianlong Hong
2009	J	`jnl`	A single layer zero skew clock routing in X architecture. Sci. China Ser. F Inf. Sci. Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu, Bing Lu
2009	J	`jnl`	An MTCMOS technology for low-power physical design. Integr. Qiang Zhou, Xin Zhao, Yici Cai, Xianlong Hong
2009	A	`conf`	An efficient decoupling capacitance optimization using piecewise polynomial models. DATE Xiaoyi Wang, Yici Cai, Sheldon X.-D. Tan, Xianlong Hong, Jacob Relles
2009	C	`conf`	Buffer Planning for 3D ICs. ISCAS Sheqin Dong, Hongjie Bai, Xianlong Hong, Satoshi Goto
2009	—	`conf`	Cell shifting aware of wirelength and overlap. ISQED Dawei Liu, Qiang Zhou, Jinian Bian, Yici Cai, Xianlong Hong
2009	—	`conf`	Diffusion-driven congestion reduction for substrate topological routing. ISPD Shenghua Liu, Guoqiang Chen, Tom Tong Jing, Lei He, Robi Dutta, Xianlong Hong
2009	J	`jnl`	Efficient Partial Reluctance Extraction for Large-Scale Regular Power Grid Structures. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Shan Zeng, Wenjian Yu, Jin Shi, Xianlong Hong, Chung-Kuan Cheng
2009	—	`conf`	Efficient power network analysis with complete inductive modeling. ISQED Shan Zeng, Wenjian Yu, Wanping Zhang, Jian Wang, Xianlong Hong, Chung-Kuan Cheng
2009	—	`conf`	Fast placement for large-scale hierarchical FPGAs. CAD/Graphics Hui Dai, Qiang Zhou, Yici Cai, Jinian Bian, Xianlong Hong
2009	—	`conf`	Incremental power optimization for multiple supply voltage design. ISQED Yuchun Ma, Xiang Qiu, Xiangqing He, Xianlong Hong
2009	—	`conf`	Integrated interlayer via planning and pin assignment for 3D ICs. SLIP Xu He, Sheqin Dong, Xianlong Hong, Satoshi Goto
2009	—	`conf`	Modern Floorplanning with Boundary Clustering Constraint. ISVLSI Li Li, Yuchun Ma, Ning Xu, Yu Wang, Xianlong Hong
2009	—	`conf`	Multi-objective Floorplanning Based on Fuzzy Logic. FSKD (4) Fubing Mao, Yuchun Ma, Ning Xu, Xianlong Hong, Yu Wang
2009	—	`conf`	Simultaneous buffer and interlayer via planning for 3D floorplanning. ISQED Xu He, Sheqin Dong, Yuchun Ma, Xianlong Hong
2009	—	`conf`	Statistical modeling and analysis of chip-level leakage power by spectral stochastic method. ASP-DAC Ruijing Shen, Ning Mi, Sheldon X.-D. Tan, Yici Cai, Xianlong Hong
2009	J	`jnl`	Substrate Topological Routing for High-Density Packages. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Shenghua Liu, Guoqiang Chen, Tom Tong Jing, Lei He, Tianpei Zhang, Robi Dutta, Xianlong Hong
2009	J	`jnl`	Thermal aware placement in 3D ICs using quadratic uniformity modeling approach. Integr. Haixia Yan, Qiang Zhou, Xianlong Hong
2009	J	`jnl`	Thermal-Aware Incremental Floorplanning for 3D ICs Based on MILP Formulation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Yuchun Ma, Xin Li, Yu Wang, Xianlong Hong
2008	—	`conf`	A Low-Power Buffered Tree Construction Algorithm Aware of Supply Voltage Variation. ISVLSI Yibo Wang, Yici Cai, Xianlong Hong
2008	J	`jnl`	A full-scale solution to the rectilinear obstacle-avoiding Steiner problem. Integr. Tom Tong Jing, Yu Hu, Zhe Feng, Xianlong Hong, Xiaodong Hu, Guiying Yan
2008	—	`conf`	A novel performance driven power gating based on distributed sleep transistor network. ACM Great Lakes Symposium on VLSI Liangpeng Guo, Yici Cai, Qiang Zhou, Le Kang, Xianlong Hong
2008	—	`conf`	Activity and register placement aware gated clock network design. ISPD Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu
2008	J	`jnl`	Application of optical proximity correction technology. Sci. China Ser. F Inf. Sci. Yici Cai, Qiang Zhou, Xianlong Hong, Rui Shi, Yang Wang
2008	—	`conf`	DFM Based Detailed Routing Algorithm for ECP and CMP. ISQED Yin Shen, Yici Cai, Qiang Zhou, Xianlong Hong
2008	J	`jnl`	Dummy Fill Aware Buffer Insertion after Layer Assignment Based on an Effective Estimation Model. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Yanming Jia, Yici Cai, Xianlong Hong
2008	J	`jnl`	Early Stage Power Supply Planning: A Heuristic Method for Codesign of Power/Ground Network and Floorplan. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Xiaoyi Wang, Jin Shi, Yici Cai, Xianlong Hong
2008	—	`conf`	Efficient Thermal Aware Placement Approach Integrated with 3D DCT Placement Algorithm. ISQED Haixia Yan, Qiang Zhou, Xianlong Hong
2008	J	`jnl`	Efficient range pattern matching algorithm for process-hotspot detection. IET Circuits Devices Syst. Hailong Yao, Subarna Sinha, Jingyu Xu, Charles C. Chiang, Yici Cai, Xianlong Hong
2008	J	`jnl`	Fashion: A Fast and Accurate Solution to Global Routing Problem. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Zhen Cao, Tong Jing, Jinjun Xiong, Yu Hu, Zhe Feng, Lei He, Xianlong Hong
2008	J	`jnl`	Fast Variational Analysis of On-Chip Power Grids by Stochastic Extended Krylov Subspace Method. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ning Mi, Sheldon X.-D. Tan, Yici Cai, Xianlong Hong
2008	—	`conf`	Full-chip routing system for reducing Cu CMP & ECP variation. SBCCI Yanming Jia, Yici Cai, Xianlong Hong
2008	C	`conf`	Gate planning during placement for gated clock network. ICCD Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu
2008	—	`conf`	Heuristic power/ground network and floorplan co-design method. ASP-DAC Xiaoyi Wang, Jin Shi, Yici Cai, Xianlong Hong
2008	—	`conf`	IPOSA: A Novel Slack Distribution Algorithm for Interconnect Power Optimization. ISQED Xiang Qiu, Yuchun Ma, Xiangqing He, Xianlong Hong
2008	—	`conf`	LP based white space redistribution for thermal via planning and performance optimization in 3D ICs. ASP-DAC Xin Li, Yuchun Ma, Xianlong Hong, Sheqin Dong, Jason Cong
2008	J	`jnl`	Large scale P/G grid transient simulation using hierarchical relaxed approach. Integr. Yici Cai, Jin Shi, Zhu Pan, Xianlong Hong, Sheldon X.-D. Tan
2008	C	`conf`	Leakage power optimization for clock network using dual-Vth technology. ISCAS Weixiang Shen, Yici Cai, Xianlong Hong
2008	J	`jnl`	Logic and Layout Aware Level Converter Optimization for Multiple Supply Voltage. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Liangpeng Guo, Yici Cai, Qiang Zhou, Xianlong Hong
2008	J	`jnl`	Low Power Gated Clock Tree Driven Placement. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu
2008	—	`conf`	Low power clock buffer planning methodology in F-D placement for large scale circuit design. ASP-DAC Yanfeng Wang, Qiang Zhou, Yici Cai, Jiang Hu, Xianlong Hong, Jinian Bian
2008	B	`conf`	MacroMap: A technology mapping algorithm for heterogeneous FPGAs with effective area estimation. FPL Xing Wei, Juanjuan Chen, Qiang Zhou, Yici Cai, Jinian Bian, Xianlong Hong
2008	J	`jnl`	Random Walk Guided Decap Embedding for Power/Ground Network Optimization. IEEE Trans. Circuits Syst. II Express Briefs Yici Cai, Le Kang, Jin Shi, Xianlong Hong, Sheldon X.-D. Tan
2008	J	`jnl`	Statistical Analysis of On-Chip Power Delivery Networks Considering Lognormal Leakage Current Variations With Spatial Correlation. IEEE Trans. Circuits Syst. I Regul. Pap. Ning Mi, Jeffrey Fan, Sheldon X.-D. Tan, Yici Cai, Xianlong Hong
2008	—	`conf`	Symmetry constraint based on mismatch analysis for analog layout in SOI technology. ASP-DAC Jiayi Liu, Sheqin Dong, Xianlong Hong, Yibo Wang, Ou He, Satoshi Goto
2008	A*	`conf`	Topological routing to maximize routability for package substrate. DAC Shenghua Liu, Guoqiang Chen, Tom Tong Jing, Lei He, Tianpei Zhang, Robi Dutta, Xianlong Hong
2008	—	`conf`	Vertical via design techniques for multi-layered P/G networks. ASP-DAC Shuai Li, Jin Shi, Yici Cai, Xianlong Hong
2008	—	`conf`	Wire density driven top-down global placement for CMP variation control. APCCAS Changdao Dong, Qiang Zhou, Yici Cai, Xianlong Hong
2008	J	`jnl`	Zero skew clock routing in X-architecture based on an improved greedy matching algorithm. Integr. Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu, Bing Lu
2007	A	`conf`	3D-STAF: scalable temperature and leakage aware floorplanning for three-dimensional integrated circuits. ICCAD Pingqiang Zhou, Yuchun Ma, Zhuoyuan Li, Robert P. Dick, Li Shang, Hai Zhou, Xianlong Hong, Qiang Zhou
2007	C	`conf`	A Fast 3D-BSG Algorithm for 3D Packing Problem. ISCAS Lingyi Zhang, Sheqin Dong, Xianlong Hong, Yuchun Ma
2007	J	`jnl`	A Yield-Driven Gridless Router. J. Comput. Sci. Technol. Qiang Zhou, Yici Cai, Duo Li, Xianlong Hong
2007	J	`jnl`	APWL-Y: An accurate and efficient wirelength estimation technique for hexagon/triangle placement. Integr. Yaoguang Wei, Sheqin Dong, Xianlong Hong
2007	—	`conf`	Activity-Aware Registers Placement for Low Power Gated Clock Tree Construction. ISVLSI Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu
2007	—	`conf`	An accurate and efficient probabilistic congestion estimation model in x architecture. SLIP Yaoguang Wei, Sheqin Dong, Xianlong Hong, Yuchun Ma
2007	—	`conf`	An effective buffer planning algorithm for IP based fixed-outline SOC placement. ACM Great Lakes Symposium on VLSI Ou He, Sheqin Dong, Jinian Bian, Yuchun Ma, Xianlong Hong
2007	J	`jnl`	An efficient quadratic placement based on search space traversing technology. Integr. Yongqiang Lu, Xianlong Hong, Qiang Zhou, Yici Cai, Jun Gu
2007	—	`conf`	CMP-aware Maze Routing Algorithm for Yield Enhancement. ISVLSI Hailong Yao, Yici Cai, Xianlong Hong
2007	C	`conf`	Clock-Tree Aware Placement Based on Dynamic Clock-Tree Building. ISCAS Yanfeng Wang, Qiang Zhou, Xianlong Hong, Yici Cai
2007	—	`conf`	Congestion Driven Buffer Planning for X-Architecture. ISQED Hongjie Bai, Sheqin Dong, Xianlong Hong
2007	—	`conf`	DpRouter: A Fast and Accurate Dynamic-Pattern-Based Global Routing Algorithm. ASP-DAC Zhen Cao, Tong Jing, Jinjun Xiong, Yu Hu, Lei He, Xianlong Hong
2007	—	`conf`	Dummy fill aware buffer insertion during routing. ACM Great Lakes Symposium on VLSI Yanming Jia, Yici Cai, Xianlong Hong
2007	C	`conf`	Effective Acceleration of Iterative Slack Distribution Process. ISCAS Xinjie Wei, Yici Cai, Xianlong Hong
2007	J	`jnl`	Efficient Thermal via Planning Approach and Its Application in 3-D Floorplanning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Shan Zeng, Jinian Bian, Wenjian Yu, Hannah Honghua Yang, Vijay Pitchumani, Chung-Kuan Cheng
2007	—	`conf`	Fast Decoupling Capacitor Budgeting for Power/Ground Network Using Random Walk Approach. ASP-DAC Le Kang, Yici Cai, Yi Zou, Jin Shi, Xianlong Hong, Sheldon X.-D. Tan
2007	—	`conf`	Interconnect Power Optimization Based on Timing Analysis. ISVLSI Liu Yang, Sheqin Dong, Yuchun Ma, Xianlong Hong
2007	—	`conf`	Logic and Layout Aware Voltage Island Generation for Low Power Design. ASP-DAC Liangpeng Guo, Yici Cai, Qiang Zhou, Xianlong Hong
2007	—	`conf`	Micro-architecture Pipelining Optimization with Throughput-Aware Floorplanning. ASP-DAC Yuchun Ma, Zhuoyuan Li, Jason Cong, Xianlong Hong, Glenn Reinman, Sheqin Dong, Qiang Zhou
2007	—	`conf`	New timing and routability driven placement algorithms for FPGA synthesis. ACM Great Lakes Symposium on VLSI Yue Zhuo, Hao Li, Qiang Zhou, Yici Cai, Xianlong Hong
2007	J	`jnl`	Partitioning-based decoupling capacitor budgeting via sequence of linear programming. Integr. Jeffrey Fan, Sheldon X.-D. Tan, Yici Cai, Xianlong Hong
2007	J	`jnl`	Pattern-Based Iterative Method for Extreme Large Power/Ground Analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jin Shi, Yici Cai, Sheldon X.-D. Tan, Jeffrey Fan, Xianlong Hong
2007	—	`conf`	Physical aware clock skew rescheduling. ACM Great Lakes Symposium on VLSI Xinjie Wei, Yici Cai, Xianlong Hong
2007	—	`conf`	Planar-CRX: A Single-Layer Zero Skew Clock Routing in X-Architecture. ISQED Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu, Bing Lu
2007	—	`conf`	Power Delivery Aware Floorplanning for Voltage Island Designs. ISQED Yici Cai, Bin Liu, Jin Shi, Qiang Zhou, Xianlong Hong
2007	—	`conf`	Practical Implementation of Stochastic Parameterized Model Order Reduction via Hermite Polynomial Chaos. ASP-DAC Yi Zou, Yici Cai, Qiang Zhou, Xianlong Hong, Sheldon X.-D. Tan, Le Kang
2007	—	`conf`	Simultaneous Switching Noise Consideration for Power/Ground Network Optimization. CAD/Graphics Le Kang, Yici Cai, Jin Shi, Xianlong Hong, Sheldon X.-D. Tan, Xiaoyi Wang
2007	A	`conf`	Statistical model order reduction for interconnect circuits considering spatial correlations. DATE Jeffrey Fan, Ning Mi, Sheldon X.-D. Tan, Yici Cai, Xianlong Hong
2007	J	`jnl`	Stochastic Interconnect Tree Construction Algorithm with Accurate Delay and Power Consideration. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Yibo Wang, Yici Cai, Xianlong Hong, Yi Zou
2007	A	`conf`	Stochastic extended Krylov subspace method for variational analysis of on-chip power grid networks. ICCAD Ning Mi, Sheldon X.-D. Tan, Pu Liu, Jian Cui, Yici Cai, Xianlong Hong
2007	—	`conf`	Thermal Effects with Leakage Power Considered in 2D/3D Floorplanning. CAD/Graphics Pingqiang Zhou, Yuchun Ma, Qiang Zhou, Xianlong Hong
2007	—	`conf`	Thermal-driven Symmetry Constraint for Analog Layout with CBL Representation. ASP-DAC Jiayi Liu, Sheqin Dong, Yuchun Ma, Di Long, Xianlong Hong
2007	C	`conf`	Unified Quadratic Programming Approach For 3-D Mixed Mode Placement. ISCAS Haixia Yan, Zhuoyuan Li, Xianlong Hong, Qiang Zhou
2007	J	`jnl`	Voltage Island Generation in Cell Based Dual-Vdd Design. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Yici Cai, Bin Liu, Qiang Zhou, Xianlong Hong
2007	J	`jnl`	lambda-OAT: lambda-Geometry Obstacle-Avoiding Tree Construction With O(nlog n) Complexity. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Tom Tong Jing, Zhe Feng, Yu Hu, Xianlong Hong, Xiaodong Hu, Guiying Yan
2006	—	`conf`	A Novel Tour Construction Heuristic for Traveling Salesman Problem Using LFF Principle. JCIS Sheqin Dong, Fan Guo, Jun Yuan, Rensheng Wang, Xianlong Hong
2006	J	`jnl`	A Two-Step Heuristic Algorithm for Minimum-Crosstalk Routing Resource Assignment. IEEE Trans. Circuits Syst. II Express Briefs Yici Cai, Bin Liu, Qiang Zhou, Xianlong Hong
2006	—	`conf`	A Two-stage Incremental Floorplanning Algorithm with Boundary Constraints. APCCAS Liu Yang, Sheqin Dong, Xianlong Hong, Yuchun Ma
2006	J	`jnl`	A coupling and crosstalk-considered timing-driven global routing algorithm for high-performance circuit design. Integr. Jingyu Xu, Xianlong Hong, Tong Jing, Ling Zhang, Jun Gu
2006	C	`conf`	A novel low-power physical design methodology for MTCMOS. ISCAS Xin Zhao, Yici Cai, Qiang Zhou, Xianlong Hong
2006	C	`conf`	A novel technique integrating buffer insertion into timing driven placement. ISCAS Lijuan Luo, Qiang Zhou, Yici Cai, Xianlong Hong, Yibo Wang
2006	J	`jnl`	ACO-Steiner: Ant Colony Optimization Based Rectilinear Steiner Minimal Tree Algorithm. J. Comput. Sci. Technol. Yu Hu, Tong Jing, Zhe Feng, Xianlong Hong, Xiaodong Hu, Guiying Yan
2006	—	`conf`	An ISPD Zhe Feng, Yu Hu, Tong Jing, Xianlong Hong, Xiaodong Hu, Guiying Yan
2006	C	`conf`	Buffer planning based on block exchanging. ISCAS Hongjie Bai, Sheqin Dong, Xianlong Hong, Song Chen
2006	—	`conf`	CDCTree: novel obstacle-avoiding routing tree construction based on current driven circuit model. ASP-DAC Yiyu Shi, Tong Jing, Lei He, Zhe Feng, Xianlong Hong
2006	—	`conf`	Clock Skew Scheduling Under Process Variations. ISQED Xinjie Wei, Yici Cai, Xianlong Hong
2006	C	`conf`	Congestion-driven W-shape multilevel full-chip routing framework. ISCAS Hailong Yao, Yici Cai, Xianlong Hong
2006	—	`conf`	DFM-aware Routing for Yield Enhancement. APCCAS Xianlong Hong, Yici Cai, Hailong Yao, Duo Li
2006	—	`conf`	DraXRouter: global routing in X-Architecture with dynamic resource assignment. ASP-DAC Zhen Cao, Tong Jing, Yu Hu, Yiyu Shi, Xianlong Hong, Xiaodong Hu, Guiying Yan
2006	—	`conf`	Efficient early stage resonance estimation techniques for C4 package. ASP-DAC Jin Shi, Yici Cai, Sheldon X.-D. Tan, Xianlong Hong
2006	A	`conf`	Efficient process-hotspot detection using range pattern matching. ICCAD Hailong Yao, Subarna Sinha, Charles C. Chiang, Xianlong Hong, Yici Cai
2006	J	`jnl`	Efficient thermal-oriented 3D floorplanning and thermal via planning for two-stacked-die integration. ACM Trans. Design Autom. Electr. Syst. Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Jinian Bian, Hannah Honghua Yang, Vijay Pitchumani
2006	—	`conf`	Floorplanning by A Revised 3-D Corner Block List with sub-C+-tree. JCIS Sheqin Dong, Rensheng Wang, Fan Guo, Jun Yuan, Xianlong Hong
2006	C	`conf`	Floorplanning for 2.5-D system integration using multi-layer-BSG structure. ISCAS Sheqin Dong, Shuyi Zheng, Xianlong Hong
2006	J	`jnl`	General Floorplans with L/T-Shaped Blocks Using Corner Block List. J. Comput. Sci. Technol. Yuchun Ma, Xianlong Hong, Sheqin Dong, Chung-Kuan Cheng, Jun Gu
2006	J	`jnl`	Hierarchical 3-D Floorplanning Algorithm for Wirelength Optimization. IEEE Trans. Circuits Syst. I Regul. Pap. Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Yici Cai, Jinian Bian, Hannah Honghua Yang, Vijay Pitchumani, Chung-Kuan Cheng
2006	—	`conf`	High accurate pattern based precondition method for extremely large power/ground grid analysis. ISPD Jin Shi, Yici Cai, Sheldon X.-D. Tan, Xianlong Hong
2006	C	`conf`	High performance clock routing in X-architecture. ISCAS Weixiang Shen, Yici Cai, Jiang Hu, Xianlong Hong, Bing Lu
2006	—	`conf`	Integrating dynamic thermal via planning with 3D floorplanning algorithm. ISPD Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Shan Zeng, Jinian Bian, Hannah Honghua Yang, Vijay Pitchumani, Chung-Kuan Cheng
2006	J	`jnl`	Legitimate Skew Clock Routing with Buffer Insertion. J. VLSI Signal Process. Xinjie Wei, Yici Cai, Meng Zhao, Xianlong Hong
2006	—	`conf`	Localized On-Chip Power Delivery Network Optimization via Sequence of Linear Programming. ISQED Jeffrey Fan, I-Fan Liao, Sheldon X.-D. Tan, Yici Cai, Xianlong Hong
2006	J	`jnl`	Multilevel Routing With Redundant Via Insertion. IEEE Trans. Circuits Syst. II Express Briefs Hailong Yao, Yici Cai, Qiang Zhou, Xianlong Hong
2006	J	`jnl`	Obstacle-avoiding rectilinear minimum-delay Steiner tree construction toward IP-block-based SOC design. IEEE Trans. Circuits Syst. II Express Briefs Jingyu Xu, Xianlong Hong, Tong Jing, Yang Yang
2006	C	`conf`	On handling the fixed-outline constraints of floorplanning using less flexibility first principles. ISCAS Shaojun Wei, Sheqin Dong, Xianlong Hong, Youliang Wu
2006	J	`jnl`	Partitioning-Based Approach to Fast On-Chip Decoupling Capacitor Budgeting and Minimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Hang Li, Jeffrey Fan, Zhenyu Qi, Sheldon X.-D. Tan, Lifeng Wu, Yici Cai, Xianlong Hong
2006	C	`conf`	Performance and power aware buffered tree construction. ISCAS Yibo Wang, Yici Cai, Xianlong Hong
2006	—	`conf`	Power driven placement with layout aware supply voltage assignment for voltage island generation in Dual-Vdd designs. ASP-DAC Bin Liu, Yici Cai, Qiang Zhou, Xianlong Hong
2006	J	`jnl`	Power/Ground Network Optimization Considering Decap Leakage Currents. IEEE Trans. Circuits Syst. II Express Briefs Yici Cai, Jingjing Fu, Xianlong Hong, Sheldon X.-D. Tan, Zuying Luo
2006	J	`jnl`	Priority-Based Routing Resource Assignment Considering Crosstalk. J. Comput. Sci. Technol. Yici Cai, Bin Liu, Yan Xiong, Qiang Zhou, Xianlong Hong
2006	—	`conf`	Signal-path driven partition and placement for analog circuit. ASP-DAC Di Long, Xianlong Hong, Sheqin Dong
2006	—	`conf`	Stochastic Local Search Using the Search Space Smoothing Meta-Heuristic: A Case Study. JCIS Sheqin Dong, Fan Guo, Jun Yuan, Rensheng Wang, Xianlong Hong
2006	J	`jnl`	Time-domain analysis methodology for large-scale RLC circuits and its applications. Sci. China Ser. F Inf. Sci. Zuying Luo, Yici Cai, Sheldon X.-D. Tan, Xianlong Hong, Xiaoyi Wang, Zhu Pan, Jingjing Fu
2006	J	`jnl`	VLSI Block Placement With Alignment Constraints. IEEE Trans. Circuits Syst. II Express Briefs Song Chen, Sheqin Dong, Xianlong Hong, Yuchun Ma, Chung-Kuan Cheng
2006	—	`conf`	Variational Circuit Simulator based on a Unified Methodology using Arithmetic over Taylor Polynomials. APCCAS Qiang Zhou, Yi Zou, Yici Cai, Xianlong Hong
2005	Misc	`conf`	A Fast Buffered Routing Tree Construction Algorithm under Accurate Delay Model. VLSI Design Yibo Wang, Yici Cai, Xianlong Hong
2005	J	`jnl`	A Fast Delay Computation for the Hybrid Structured Clock Network. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Yi Zou, Yici Cai, Qiang Zhou, Xianlong Hong, Sheldon X.-D. Tan
2005	—	`conf`	A Hybrid Genetic Algorithm and Application to the Crosstalk Aware Track Assignment Problem. ICNC (3) Yici Cai, Bin Liu, Xiong Yan, Qiang Zhou, Xianlong Hong
2005	—	`conf`	A Min-area Solution to Performance and RLC Crosstalk Driven Global Routing Problem. ASP-DAC Tong Jing, Ling Zhang, Jinghong Liang, Jingyu Xu, Xianlong Hong, Jinjun Xiong, Lei He
2005	C	`conf`	A New Buffer Planning Algorithm Based on Room Resizing. EUC Hongjie Bai, Sheqin Dong, Xianlong Hong, Song Chen
2005	—	`conf`	A New Methodology of Integrating High Level Synthesis and Floorplan for SoC Design. ICESS Yunfeng Wang, Jinian Bian, Xianlong Hong, Liu Yang, Qiang Zhou, Qiang Wu
2005	—	`conf`	A Routing Paradigm with Novel Resources Estimation and Routability Models for X-Architecture Based Physical Design. SAMOS Yu Hu, Tong Jing, Xianlong Hong, Xiaodong Hu, Guiying Yan
2005	—	`conf`	A Thermal Aware Floorplanning Algorithm Supporting Voltage Islands for Low Power SOC Design. PATMOS Yici Cai, Bin Liu, Qiang Zhou, Xianlong Hong
2005	—	`conf`	A divide-and-conquer 2.5-D floorplanning algorithm based on statistical wirelength estimation. ISCAS (6) Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Yici Cai, Jinian Bian, Hannal Yang, Prashant Saxena, Vijay Pitchumani
2005	—	`conf`	A global interconnect optimization algorithm under accurate delay model using solution space smoothing. ISCAS (1) Yici Cai, Yibo Wang, Xianlong Hong
2005	—	`conf`	A new algorithm for layout of dark field alternating phase shifting masks. ACM Great Lakes Symposium on VLSI Qinglang Luo, Xianlong Hong, Qiang Zhou, Yici Cai
2005	—	`conf`	A new approach based on LFF for optimization of dynamic hardware reconfigurations. ISCAS (2) Zhe Zhou, Sheqin Dong, Xianlong Hong, Yuliang Wu, Yoji Kajitani
2005	—	`conf`	An efficient algorithm for buffered routing tree construction under fixed buffer locations with accurate delay models. ISCAS (1) Yiqian Zhang, Xianlong Hong, Yici Cai
2005	—	`conf`	An efficient algorithm to fixed-outline floorplanning based on instance augmentation. CAD/Graphics Rong Liu, Sheqin Dong, Xianlong Hong
2005	—	`conf`	An improved P-admissible floorplan representation based on Corner Block List. ASP-DAC Renshen Wang, Sheqin Dong, Xianlong Hong
2005	—	`conf`	An improved direct boundary element method for substrate coupling resistance extraction. ACM Great Lakes Symposium on VLSI Xiren Wang, Wenjian Yu, Zeyi Wang, Xianlong Hong
2005	—	`conf`	An-OARSMan: obstacle-avoiding routing tree construction with good length performance. ASP-DAC Yu Hu, Tong Jing, Xianlong Hong, Zhe Feng, Xiaodong Hu, Guiying Yan
2005	—	`conf`	Analysis of buffered hybrid structured clock networks. ASP-DAC Yi Zou, Qiang Zhou, Yici Cai, Xianlong Hong, Sheldon X.-D. Tan
2005	—	`conf`	Buffer Planning Algorithm Based on Partial Clustered Floorplanning. ISQED Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Chung-Kuan Cheng
2005	J	`jnl`	Buffer planning as an Integral part of floorplanning with consideration of routing congestion. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Chung-Kuan Cheng, Jun Gu
2005	—	`conf`	Clock network minimization methodology based on incremental placement. ASP-DAC Liang Huang, Yici Cai, Qiang Zhou, Xianlong Hong, Jiang Hu, Yongqiang Lu
2005	J	`jnl`	Crosstalk and Congestion Driven Layer Assignment Algorithm. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Bin Liu, Yici Cai, Qiang Zhou, Xianlong Hong
2005	J	`jnl`	Crosstalk-Aware Routing Resource Assignment. J. Comput. Sci. Technol. Hailong Yao, Yici Cai, Qiang Zhou, Xianlong Hong
2005	—	`conf`	Efficient Simulation of Power/Ground Networks with Package and Vias. PATMOS Jin Shi, Yici Cai, Xianlong Hong, Sheldon X.-D. Tan
2005	—	`conf`	Fast Decap Allocation Algorithm For Robust On-Chip Power Delivery. ISQED Zhenyu Qi, Hang Li, Sheldon X.-D. Tan, Lifeng Wu, Yici Cai, Xianlong Hong
2005	—	`conf`	Fixed-outline floorplanning based on common subsequence. ACM Great Lakes Symposium on VLSI Rong Liu, Sheqin Dong, Xianlong Hong
2005	—	`conf`	Fixed-outline floorplanning with constraints through instance augmentation. ISCAS (2) Rong Liu, Sheqin Dong, Xianlong Hong, Yoji Kajitani
2005	—	`conf`	Floorplanning with Consideration of White Space Resource Distribution for Repeater Planning. ISQED Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Chung-Kuan Cheng
2005	—	`conf`	Improved multilevel routing with redundant via placement for yield and reliability. ACM Great Lakes Symposium on VLSI Hailong Yao, Yici Cai, Xianlong Hong, Qiang Zhou
2005	—	`conf`	Integrated routing resource assignment for RLC crosstalk minimization. ISCAS (2) Yici Cai, Bin Liu, Qiang Zhou, Xianlong Hong
2005	—	`conf`	Interconnect delay optimization via high level re-synthesis after floorplanning. ISCAS (6) Yunfeng Wang, Jinian Bian, Xianlong Hong
2005	—	`conf`	LFF algorithm for heterogeneous FPGA floorplanning. ASP-DAC Jun Yuan, Sheqin Dong, Xianlong Hong, Yuliang Wu
2005	J	`jnl`	Modeling and Analysis of Mesh Tree Hybrid Power/Ground Networks with Multiple Voltage Supply in Time Domain. J. Comput. Sci. Technol. Yici Cai, Jin Shi, Zuying Luo, Xianlong Hong
2005	—	`conf`	Multi-stage Detailed Placement Algorithm for Large-Scale Mixed-Mode Layout Design. ICCSA (4) Lijuan Luo, Qiang Zhou, Xianlong Hong, Hanbin Zhou
2005	J	`jnl`	Navigating Register Placement for Low Power Clock Network Design. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Yongqiang Lu, Chin Ngai Sze, Xianlong Hong, Qiang Zhou, Yici Cai, Liang Huang, Jiang Hu
2005	A*	`conf`	Navigating registers in placement for clock network minimization. DAC Yongqiang Lu, Cliff C. N. Sze, Xianlong Hong, Qiang Zhou, Yici Cai, Liang Huang, Jiang Hu
2005	—	`conf`	Obstacle-Avoiding Rectilinear Minimum-Delay Steiner Tree Construction towards IP-Block-Based SOC Design. ISQED Jingyu Xu, Xianlong Hong, Tong Jing, Yang Yang
2005	—	`conf`	Optimal two-dimension common centroid layout generation for MOS transistors unit-circuit. ISCAS (3) Di Long, Xianlong Hong, Sheqin Dong
2005	A*	`conf`	Partitioning-based approach to fast on-chip decap budgeting and minimization. DAC Hang Li, Zhenyu Qi, Sheldon X.-D. Tan, Lifeng Wu, Yici Cai, Xianlong Hong
2005	—	`conf`	Performance constrained floorplanning based on partial clustering [IC layout]. ISCAS (2) Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Chung-Kuan Cheng
2005	—	`conf`	Register placement for low power clock network. ASP-DAC Yongqiang Lu, Cliff C. N. Sze, Xianlong Hong, Qiang Zhou, Yici Cai, Liang Huang, Jiang Hu
2005	—	`conf`	Relaxed hierarchical power/ground grid analysis. ASP-DAC Yici Cai, Zhu Pan, Sheldon X.-D. Tan, Xianlong Hong, Wenting Hou, Lifeng Wu
2005	J	`jnl`	Reliable buffered clock tree routing algorithm with process variation tolerance. Sci. China Ser. F Inf. Sci. Yici Cai, Yan Xiong, Xianlong Hong, Yi Liu
2005	J	`jnl`	Shielding Area Optimization Under the Solution of Interconnect Crosstalk. J. Comput. Sci. Technol. Yici Cai, Xin Zhao, Qiang Zhou, Xianlong Hong
2005	J	`jnl`	Spanning graph-based nonrectilinear steiner tree algorithms. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Qi Zhu, Hai Zhou, Tong Jing, Xianlong Hong, Yang Yang
2005	—	`conf`	The polygonal contraction heuristic for rectilinear Steiner tree construction. ASP-DAC Yin Wang, Xianlong Hong, Tong Jing, Yang Yang, Xiaodong Hu, Guiying Yan
2005	J	`jnl`	Timing-Driven Global Routing with Efficient Buffer Insertion. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Jingyu Xu, Xianlong Hong, Tong Jing
2005	—	`conf`	Timing-driven global routing with efficient buffer insertion. ISCAS (3) Jingyu Xu, Xianlong Hong, Tong Jing
2005	—	`conf`	VLSI block placement with alignment constraints based on corner block list. ISCAS (6) Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Chung-Kuan Cheng
2005	—	`conf`	VLSI on-chip power/ground network optimization considering decap leakage currents. ASP-DAC Jingjing Fu, Zuying Luo, Xianlong Hong, Yici Cai, Sheldon X.-D. Tan, Zhu Pan
2005	—	`conf`	Via-Aware Global Routing for Good VLSI Manufacturability and High Yield. ASAP Yang Yang, Tong Jing, Xianlong Hong, Yu Hu, Qi Zhu, Xiaodong Hu, Guiying Yan
2005	—	`conf`	Zero skew clock routing with tree topology construction using simulated annealing method. ISCAS (1) Xinjie Wei, Yici Cai, Xianlong Hong
2004	C	`conf`	A Fast Delay Analysis Algorithm for The Hybrid Structured Clock Network. ICCD Yi Zou, Yici Cai, Qiang Zhou, Xianlong Hong, Sheldon X.-D. Tan
2004	J	`jnl`	A buffer planning algorithm for chip-level floorplanning. Sci. China Ser. F Inf. Sci. Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Yici Cai, Chung-Kuan Cheng, Jun Gu
2004	—	`conf`	A buffer planning algorithm with congestion optimization. ASP-DAC Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Yici Cai, Chung-Kuan Cheng, Jun Gu
2004	—	`conf`	A coupling and crosstalk considered timing-driven global routing algorithm for high performance circuit design. ASP-DAC Jingyu Xu, Xianlong Hong, Tong Jing, Ling Zhang, Jun Gu
2004	—	`conf`	A fast decoupling capacitor budgeting algorithm for robust on-chip power delivery. ASP-DAC Jingjing Fu, Zuying Luo, Xianlong Hong, Yici Cai, Sheldon X.-D. Tan, Zhu Pan
2004	—	`conf`	Algorithm for yield driven correction of layout. ISCAS (5) Yang Wang, Yici Cai, Xianlong Hong, Qiang Zhou
2004	—	`conf`	An Efficient Low-Degree RMST Algorithm for VLSI/ULSI Physical Design. PATMOS Yin Wang, Xianlong Hong, Tong Jing, Yang Yang, Xiaodong Hu, Guiying Yan
2004	J	`jnl`	Area minimization of power distribution network using efficient nonlinear programming techniques. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Xiaohai Wu, Xianlong Hong, Yici Cai, Zuying Luo, Chung-Kuan Cheng, Jun Gu, Wayne Wei-Ming Dai
2004	—	`conf`	Buffer allocation algorithm with consideration of routing congestion. ASP-DAC Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Yici Cai, Chung-Kuan Cheng, Jun Gu
2004	J	`jnl`	Corner block list representation and its application to floorplan optimization. IEEE Trans. Circuits Syst. II Express Briefs Xianlong Hong, Sheqin Dong, Gang Huang, Yici Cai, Chung-Kuan Cheng, Jun Gu
2004	J	`jnl`	Corner block list representation and its application with boundary constraints. Sci. China Ser. F Inf. Sci. Xianlong Hong, Yuchun Ma, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu
2004	—	`conf`	Crosstalk driven routing resource assignment. ISCAS (5) Hailong Yao, Qiang Zhou, Xianlong Hong, Yici Cai
2004	—	`conf`	Efficient octilinear Steiner tree construction based on spanning graphs. ASP-DAC Qi Zhu, Hai Zhou, Tong Jing, Xianlong Hong, Yang Yang
2004	J	`jnl`	Fast Evaluation of Bounded Slice-Line Grid. J. Comput. Sci. Technol. Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Chung-Kuan Cheng, Jun Gu
2004	—	`conf`	Layer assignment algorithm for RLC crosstalk minimization. ISCAS (5) Bin Liu, Yici Cai, Qiang Zhou, Xianlong Hong
2004	J	`jnl`	Leakage Current Estimation of CMOS Circuit with Stack Effect. J. Comput. Sci. Technol. Yong-Jun Xu, Zuying Luo, Xiaowei Li, Li-Jian Li, Xianlong Hong
2004	—	`conf`	Module placement based on quadratic programming and rectangle packing using less flexibility first principle. ISCAS (5) Sheqin Dong, Zhong Yang, Xianlong Hong, Yuliang Wu
2004	—	`conf`	Partial random walk for large linear network analysis. ISCAS (5) Weikun Guo, Sheldon X.-D. Tan, Zuying Luo, Xianlong Hong
2004	—	`conf`	Performance and RLC crosstalk driven global routing. ISCAS (5) Ling Zhang, Tong Jing, Xianlong Hong, Jingyu Xu, Jinjun Xiong, Lei He
2004	—	`conf`	Quick and effective buffered legitimate skew clock routing. ISCAS (5) Meng Zhao, Xinjie Wei, Yici Cai, Xianlong Hong
2004	—	`conf`	Recursively combine floorplan and Q-place in mixed mode placement based on circuit's variety of block configuration. ISCAS (5) Changqi Yang, Xianlong Hong, Hannah Honghua Yang, Qiang Zhou, Yici Cai, Yongqiang Lu
2004	—	`conf`	Shielding area optimization under the solution of interconnect crosstalk. ISCAS (5) Xin Zhao, Yici Cai, Qiang Zhou, Xianlong Hong, Lei He, Jinjun Xiong
2004	—	`conf`	Simultaneous Wire Sizing and Decoupling Capacitance Budgeting for Robust On-Chip Power Delivery. PATMOS Jingjing Fu, Zuying Luo, Xianlong Hong, Yici Cai, Sheldon X.-D. Tan, Zhu Pan
2004	J	`jnl`	Stairway compaction using corner block list and its applications with rectilinear blocks. ACM Trans. Design Autom. Electr. Syst. Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu
2004	—	`conf`	Transient Analysis of On-Chip Power Distribution Networks Using Equivalent Circuit Modeling. ISQED Zhu Pan, Yici Cai, Sheldon X.-D. Tan, Zuying Luo, Xianlong Hong
2004	J	`jnl`	UTACO: a unified timing and congestion optimization algorithm for standard cell global routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Tong Jing, Xianlong Hong, Jingyu Xu, Haiyun Bao, Chung-Kuan Cheng, Jun Gu
2003	J	`jnl`	A Novel Timing-Driven Global Routing Algorithm Considering Coupling Effects for High Performance Circuit Design. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Jingyu Xu, Xianlong Hong, Tong Jing, Yici Cai, Jun Gu
2003	—	`conf`	A buffer planning algorithm based on dead space redistribution. ASP-DAC Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Yici Cai, Chung-Kuan Cheng, Jun Gu
2003	—	`conf`	A novel timing-driven global routing algorithm considering coupling effects for high performance circuit design. ASP-DAC Jingyu Xu, Xianlong Hong, Tong Jing, Yici Cai, Jun Gu
2003	—	`conf`	A path-based timing-driven quadratic placement algorithm. ASP-DAC Wenting Hou, Xianlong Hong, Weimin Wu, Yici Cai
2003	—	`conf`	Algorithms for analog VLSI 2D stack generation and block merging. ISCAS (4) Rui Liu, Sheqin Dong, Xianlong Hong, Di Long, Jun Gu
2003	J	`jnl`	An efficient hierarchical timing-driven Steiner tree algorithm for global routing. Integr. Jingyu Xu, Xianlong Hong, Tong Jing, Yici Cai, Jun Gu
2003	—	`conf`	An integrated floorplanning with an efficient buffer planning algorithm. ISPD Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Yici Cai, Chung-Kuan Cheng, Jun Gu
2003	—	`conf`	Arbitrary convex and concave rectilinear block packing based on corner block list. ISCAS (5) Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Song Chen, Chung-Kuan Cheng, Jun Gu
2003	—	`conf`	BBE: hierarchical computation of 3-D interconnect capacitance with BEM block extraction. ASP-DAC Taotao Lu, Zeyi Wang, Xianlong Hong
2003	J	`jnl`	CNB: A Critical-Network-Based Timing Optimization Method for Standard Cell Global Routing. J. Comput. Sci. Technol. Xianlong Hong, Tong Jing, Jingyu Xu, Haiyun Bao, Jun Gu
2003	—	`conf`	Combining clustering and partitioning in quadratic placement. ISCAS (4) Yongqiang Lu, Xianlong Hong, Wenting Hou, Weimin Wu, Yici Cai
2003	—	`conf`	Congestion driven incremental placement algorithm for standard cell layout. ASP-DAC Zhuoyuan Li, Weimin Wu, Xianlong Hong
2003	J	`jnl`	Deterministic VLSI Block Placement Algorithm Using Less Flexibility First Principle. J. Comput. Sci. Technol. Sheqin Dong, Xianlong Hong, Yuliang Wu, Jun Gu
2003	A*	`conf`	Dynamic global buffer planning optimization based on detail block locating and congestion analysis. DAC Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Yici Cai, Chung-Kuan Cheng, Jun Gu
2003	C	`conf`	Enhanced QMM-BEM Solver for 3-D Finite-Domain Capacitance Extraction with Multilayered Dielectrics. ICCD Wenjian Yu, Zeyi Wang, Xianlong Hong
2003	—	`conf`	Evaluating a bounded slice-line grid assignment in O(nlogn) time. ISCAS (4) Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Yici Cai, Chung-Kuan Cheng, Jun Gu
2003	J	`jnl`	FaSa: A Fast and Stable Quadratic Placement Algorithm. J. Comput. Sci. Technol. Wenting Hou, Xianlong Hong, Weimin Wu, Yici Cai
2003	J	`jnl`	SSTT: Efficient Local Search for GSI Global Routing. J. Comput. Sci. Technol. Tong Jing, Xianlong Hong, Haiyun Bao, Jingyu Xu, Jun Gu
2003	—	`conf`	UTACO: a unified timing and congestion optimizing algorithm for standard cell global routing. ASP-DAC Tong Jing, Xianlong Hong, Haiyun Bao, Yici Cai, Jingyu Xu, Chung-Kuan Cheng, Jun Gu
2003	J	`jnl`	VLSI Module Placement with Pre-Placed Modules and with Consideration of Congestion Using Solution Space Smoothing. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Sheqin Dong, Xianlong Hong, Song Chen, Xin Qi, Ruijie Wang, Jun Gu
2003	—	`conf`	VLSI module placement with pre-placed modules and considering congestion using solution space smoothing. ASP-DAC Sheqin Dong, Xianlong Hong, Xin Qi, Ruijie Wang, Song Chen, Jun Gu
2002	—	`conf`	A 3-D Minimum-Order Boundary Integral Equation Technique to Extract Frequency-Dependant Inductance and Resistance in ULSI. ASP-DAC/VLSI Design Shuzhou Fang, Zeyi Wang, Xianlong Hong
2002	J	`jnl`	A multi-step standard-cell placement algorithm of optimizing timing and congestion behavior. Sci. China Ser. F Inf. Sci. Wenting Hou, Xianlong Hong, Weimin Wu, Yici Cai
2002	—	`conf`	A novel and efficient timing-driven global router for standard cell layout design based on critical network concept. ISCAS (1) Tong Jing, Xianlong Hong, Haiyun Bao, Yici Cai, Jingyu Xu, Jun Gu
2002	—	`conf`	An Efficient Hierarchical Timing-Driven Steiner Tree Algorithm for Global Routing. ASP-DAC/VLSI Design Jingyu Xu, Xianlong Hong, Tong Jing, Yici Cai, Jun Gu
2002	J	`jnl`	An Optimum Placement Search Algorithm Based on Extended Corner Block List. J. Comput. Sci. Technol. Sheqin Dong, Shuo Zhou, Xianlong Hong, Chung-Kuan Cheng, Jun Gu, Yici Cai
2002	—	`conf`	Stairway Compaction using Corner Block List and Its Applications with Rectilinear Blocks. ASP-DAC/VLSI Design Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu
2001	—	`conf`	A new congestion-driven placement algorithm based on cell inflation. ASP-DAC Wenting Hou, Hong Yu, Xianlong Hong, Yici Cai, Weimin Wu, Jun Gu, William H. Kao
2001	A	`conf`	Area Minimization of Power Distribution Network Using Efficient Nonlinear Programming Techniques. ICCAD Xiaohai Wu, Xianlong Hong, Yici Cai, Chung-Kuan Cheng, Jun Gu, Wayne Wei-Ming Dai
2001	A*	`conf`	Floorplanning with Abutment Constraints and L-Shaped/T-Shaped Blocks based on Corner Block List. DAC Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu
2001	J	`jnl`	Floorplanning with abutment constraints based on corner block list. Integr. Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu
2001	—	`conf`	VLSI block placement using less flexibility first principles. ASP-DAC Sheqin Dong, Xianlong Hong, Youliang Wu, Yizhou Lin, Jun Gu
2001	—	`conf`	VLSI floorplanning with boundary constraints based on corner block list. ASP-DAC Yuchun Ma, Sheqin Dong, Xianlong Hong, Yici Cai, Chung-Kuan Cheng, Jun Gu
2000	—	`conf`	A simplified hybrid method for calculating the frequency-dependent inductances of transmission lines with rectangular cross section. ASP-DAC Shuzhou Fang, Xiaobo Tang, Zeyi Wang, Xianlong Hong
2000	—	`conf`	Area routing oriented hierarchical corner stitching with partial bin. ASP-DAC Yan Zhang, Baohua Wang, Yici Cai, Xianlong Hong
2000	A	`conf`	Corner Block List: An Effective and Efficient Topological Representation of Non-Slicing Floorplan. ICCAD Xianlong Hong, Gang Huang, Yici Cai, Jiangchun Gu, Sheqin Dong, Chung-Kuan Cheng, Jun Gu
2000	—	`conf`	Hierarchical computation of 3-D interconnect capacitance using direct boundary element method. ASP-DAC Jiangchun Gu, Zeyi Wang, Xianlong Hong
2000	—	`conf`	MMP: a novel placement algorithm for combined macro block and standard cell layout design. ASP-DAC Hong Yu, Xianlong Hong, Yici Cai
1999	—	`conf`	A New Global Routing Algorithm Independent Of Net Ordering. ASP-DAC Haiyun Bao, Xianlong Hong, Yici Cai
1999	—	`conf`	A Timing-Driven Block Placer Based on Sequence Pair Model. ASP-DAC Gang Huang, Xianlong Hong, Changge Qiao, Yici Cai
1999	—	`conf`	Design and Optimization of Power/Ground Network for Cell-Based VLSIs with Macro Cells. ASP-DAC Xiaohai Wu, Changge Qiao, Xianlong Hong
1999	—	`conf`	FSM Modeling of Synchronous VHDL Design for Symbolic Model Checking. ASP-DAC Jinsong Bei, Hongxing Li, Jinian Bian, Hongxi Xue, Xianlong Hong
1999	—	`conf`	The Hierarchical h-Adaptive 3-D Boundary Element Computation of VLSI Interconnect Capacitance. ASP-DAC Jinsong Hou, Zeyi Wang, Xianlong Hong
1997	J	`jnl`	TIGER: an efficient timing-driven global router for gate array and standard cell layout design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Xianlong Hong, Tianxiong Xue, Jin Huang, Chung-Kuan Cheng, Ernest S. Kuh
1997	—	`conf`	VEAP: Global optimization based efficient algorithm for VLSI placement. ASP-DAC Tianming Kong, Xianlong Hong, Changge Qiao
1993	A*	`conf`	An Efficient Timing-Driven Global Routing Algorithm. DAC Jin Huang, Xianlong Hong, Chung-Kuan Cheng, Ernest S. Kuh
1993	A*	`conf`	Performance-Driven Steiner Tree Algorithm for Global Routing. DAC Xianlong Hong, Tianxiong Xue, Ernest S. Kuh, Chung-Kuan Cheng, Jin Huang
1992	A*	`conf`	FARM: An Efficient Feed-Through Pin Assignment Algorithm. DAC Xianlong Hong, Jin Huang, Chung-Kuan Cheng, Ernest S. Kuh