Xiangyu Zhang

29 papers C 4Journal 14Unranked 11
YearRankTypeTitle / Venue / Authors
2026 J jnl
An Energy-Efficient Edge Coprocessor for Neural Rendering With Explicit Data Reuse Strategies.
IEEE Trans. Very Large Scale Integr. Syst.
Binzhe Yuan, Xiangyu Zhang, Zeyu Zheng, Yuefeng Zhang, Haochuan Wan, Zhechen Yuan, Junsheng Chen, Yunxiang He, Junran Ding, Xiaoming Zhang, Chaolin Rao, Wenyan Su, Pingqiang Zhou, Jingyi Yu, Xin Lou
2026 — conf
Scalarium: A Unified Scala-based Co-Simulation Framework for Agile Chip Development.
ASP-DAC
Yuefeng Zhang, Cheng Zhang, Wenkai Zhou, Binzhe Yuan, Junsheng Chen, Xiangyu Zhang, Hao Geng, Xin Lou
2024 C conf
A Multi-scale Block PatchMatch-based Unified Algorithm for Efficient 6-D Vision Processing.
ISCAS
Hongyu Wang, Xiangyu Zhang, Xin Lou
2024 — conf
An FPGA Accelerator for 3D Cone-beam Sparse-view Computed Tomography Reconstruction.
AICAS
Yuhan Gu, Qing Wu, Zhechen Yuan, Xiangyu Zhang, Wenyan Su, Yuyao Zhang, Xin Lou
2024 J jnl
FPGA Accelerator for Human Activity Recognition Based on Radar.
IEEE Trans. Circuits Syst. II Express Briefs
Kangjie Long, Chaolin Rao, Xiangyu Zhang, Wenbin Ye, Xin Lou
2024 J jnl
RAW Images-Based Motion-Assisted Object Detection Accelerator Using Deformable Parts Models Features on 1080p Videos.
IEEE Trans. Circuits Syst. I Regul. Pap.
Ling Zhang, Haoyan Li, Xiangyu Zhang, Xin Lou
2024 J jnl
Reconfigurable and Energy-Efficient Architecture for Deploying Multi-Layer RNNs on FPGA.
IEEE Trans. Circuits Syst. I Regul. Pap.
Xiangyu Zhang, Yiren Zhu, Xin Lou
2023 C conf
An Efficient Frequency Domain Vision Pipeline From RAW Images to Backend Tasks.
ISCAS
Haoyan Li, Wei Zhou, Xiangyu Zhang, Xin Lou
2023 — conf
Image Frequency Separation Residual Network for End-to-end RAW to RGB Mapping.
AICAS
Mengchuan Dong, Wei Zhou, Cong Pang, Xiangyu Zhang, Xin Lou
2022 — conf
A 39pJ/label 1920x1080 165.7 FPS Block PatchMatch Based Stereo Matching Processor on FPGA.
CICC
Hongyu Wang, Wei Zhou, Xiangyu Zhang, Xin Lou
2022 J jnl
A Block PatchMatch-Based Energy-Resource Efficient Stereo Matching Processor on FPGA.
IEEE Trans. Circuits Syst. I Regul. Pap.
Hongyu Wang, Wei Zhou, Xiangyu Zhang, Xin Lou
2022 J jnl
A Raw Image-Based End-to-End Object Detection Accelerator Using HOG Features.
IEEE Trans. Circuits Syst. I Regul. Pap.
Xiangyu Zhang, Ling Zhang, Xin Lou
2022 C conf
An End-to-end Computer Vision System Architecture.
ISCAS
Ling Zhang, Wei Zhou, Xiangyu Zhang, Xin Lou
2022 — conf
FPGA Accelerator for Radar-Based Human Activity Recognition.
AICAS
Kangjie Long, Chaolin Rao, Xiangyu Zhang, Wen Bin Ye, Xin Lou
2021 — conf
Motion Assisted Video-based Stereo Matching.
APCCAS
Shengyu Gao, Hongyu Wang, Teng Wang, Yang Wang, Xiangyu Zhang, Xin Lou
2021 — conf
Robust Multi-Source Direction of Arrival Estimation Using a Single Acoustic Vector Sensor.
APCCAS
Jianhua Geng, Sifan Wang, Juan Li, Jingwei Li, Xiangyu Zhang, Xin Lou
2021 — conf
Spatial Non-Maximum Suppression for Object Detection using Correlation and Dynamic Thresholds.
ISOCC
Xiangyu Zhang, Wenyan Su, Juan Li, Jingwei Li, Xin Lou
2021 — conf
Stereo Point Cloud Refinement for 3D Object Detection.
APCCAS
Wangchao Liu, Teng Wang, Yang Wang, Xiangyu Zhang, Xin Lou
2019 J jnl
A Hardware-Efficient Recognition Accelerator Using Haar-Like Feature and SVM Classifier.
IEEE Access
Aiwen Luo, Fengwei An, Xiangyu Zhang, Hans Jürgen Mattausch
2019 J jnl
Energy-Efficient Hardware Implementation of Road-Lane Detection Based on Hough Transform with Parallelized Voting Procedure and Local Maximum Algorithm.
IEICE Trans. Inf. Syst.
Jungang Guan, Fengwei An, Xiangyu Zhang, Lei Chen, Hans Jürgen Mattausch
2018 J jnl
A Hardware Architecture for Cell-Based Feature-Extraction and Classification Using Dual-Feature Space.
IEEE Trans. Circuits Syst. Video Technol.
Fengwei An, Xiangyu Zhang, Aiwen Luo, Lei Chen, Hans Jürgen Mattausch
2018 J jnl
A Modular and Reconfigurable Pipeline Architecture for Learning Vector Quantization.
IEEE Trans. Circuits Syst. I Regul. Pap.
Xiangyu Zhang, Fengwei An, Lei Chen, Idaku Ishii, Hans Jürgen Mattausch
2018 J jnl
Resource-Efficient Object-Recognition Coprocessor With Parallel Processing of Multiple Scan Windows in 65-nm CMOS.
IEEE Trans. Very Large Scale Integr. Syst.
Aiwen Luo, Fengwei An, Xiangyu Zhang, Lei Chen, Hans Jürgen Mattausch
2017 J jnl
A Vector-Quantization Compression Circuit With On-Chip Learning Ability for High-Speed Image Sensor.
IEEE Access
Zunkai Huang, Xiangyu Zhang, Lei Chen, Yongxin Zhu, Fengwei An, Hui Wang, Songlin Feng
2017 — conf
Object-recognition VLSI for pedestrian detection in automotive applications.
ASICON
Fengwei An, Xiangyu Zhang, Lei Chen, Idaku Ishii
2017 J jnl
Real-Time Straight-Line Detection for XGA-Size Videos by Hough Transform with Parallelized Voting Procedures.
Sensors
Jungang Guan, Fengwei An, Xiangyu Zhang, Lei Chen, Hans Jürgen Mattausch
2016 J jnl
A Memory-Based Modular Architecture for SOM and LVQ with Dynamic Configuration.
IEEE Trans. Multi Scale Comput. Syst.
Fengwei An, Xiangyu Zhang, Lei Chen, Hans Jürgen Mattausch
2016 C conf
Dynamically reconfigurable system for LVQ-based on-chip learning and recognition.
ISCAS
Fengwei An, Xiangyu Zhang, Lei Chen, Hans Jürgen Mattausch
2016 — conf
Pixel-based pipeline hardware architecture for high-performance Haar-like feature extraction.
APCCAS
Yuki Fujita, Fengwei An, Aiwen Luo, Xiangyu Zhang, Lei Chen, Hans Jürgen Mattausch