Xiangyu Dong

36 papers A* 7A 9B 1C 4Journal 9Unranked 5
YearRankTypeTitle / Venue / Authors
2014 J jnl
Building and Optimizing MRAM-Based Commodity Memories.
ACM Trans. Archit. Code Optim.
Jue Wang, Xiangyu Dong, Yuan Xie
2014 A conf
Enabling high-performance LPDDRx-compatible MRAM.
ISLPED
Jue Wang, Xiangyu Dong, Yuan Xie
2014 J jnl
Endurance-aware cache line management for non-volatile caches.
ACM Trans. Archit. Code Optim.
Jue Wang, Xiangyu Dong, Yuan Xie, Norman P. Jouppi
2014 J jnl
Preventing STT-RAM Last-Level Caches from Port Obstruction.
ACM Trans. Archit. Code Optim.
Jue Wang, Xiangyu Dong, Yuan Xie
2014 C conf
ProactiveDRAM: A DRAM-initiated retention management scheme.
ICCD
Jue Wang, Xiangyu Dong, Yuan Xie
2014 A conf
Using multi-level cell STT-RAM for fast and energy-efficient local checkpointing.
ICCAD
Ping Chi, Cong Xu, Tao Zhang, Xiangyu Dong, Yuan Xie
2013 B conf
A circuit-architecture co-optimization framework for evaluating emerging memory hierarchies.
ISPASS
Xiangyu Dong, Norman P. Jouppi, Yuan Xie
2013 J jnl
A circuit-architecture co-optimization framework for exploring nonvolatile memory hierarchies.
ACM Trans. Archit. Code Optim.
Xiangyu Dong, Norman P. Jouppi, Yuan Xie
2013 C conf
Low-current probabilistic writes for power-efficient STT-RAM caches.
ICCD
Nikolaos Strikos, Vasileios Kontorinis, Xiangyu Dong, Houman Homayoun, Dean M. Tullsen
2013 A conf
OAP: an obstruction-aware cache management policy for STT-RAM last-level caches.
DATE
Jue Wang, Xiangyu Dong, Yuan Xie
2013 A* conf
i
HPCA
Jue Wang, Xiangyu Dong, Yuan Xie, Norman P. Jouppi
2012 J jnl
NVSim: A Circuit-Level Performance, Energy, and Area Model for Emerging Nonvolatile Memory.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Xiangyu Dong, Cong Xu, Yuan Xie, Norman P. Jouppi
2012 A* conf
Point and discard: a hard-error-tolerant architecture for non-volatile last level caches.
DAC
Jue Wang, Xiangyu Dong, Yuan Xie
2011 — conf
AdaMS: Adaptive MLC/SLC phase-change memory design for file storage.
ASP-DAC
Xiangyu Dong, Yuan Xie
2011 A conf
An energy-efficient 3D CMP design with fine-grained voltage scaling.
DATE
Jishen Zhao, Xiangyu Dong, Yuan Xie
2011 A* conf
Architecting on-chip interconnects for stacked 3D STT-RAM caches in CMPs.
ISCA
Asit K. Mishra, Xiangyu Dong, Guangyu Sun, Yuan Xie, Narayanan Vijaykrishnan, Chita R. Das
2011 A conf
Design implications of memristor-based RRAM cross-point structures.
DATE
Cong Xu, Xiangyu Dong, Norman P. Jouppi, Yuan Xie
2011 C conf
Energy-efficient multi-level cell phase-change memory system with data encoding.
ICCD
Jue Wang, Xiangyu Dong, Guangyu Sun, Dimin Niu, Yuan Xie
2011 J jnl
Hybrid checkpointing using emerging nonvolatile memories for future exascale systems.
ACM Trans. Archit. Code Optim.
Xiangyu Dong, Yuan Xie, Naveen Muralimanohar, Norman P. Jouppi
2011 — ch.
Influence of Stacked 3D Memory/Cache Architectures on GPUs.
3D Integration for NoC-based SoC Architectures
Ahmed Al-Maashri, Guangyu Sun, Xiangyu Dong, Yuan Xie, Narayanan Vijaykrishnan
2011 J jnl
Stacking magnetic random access memory atop microprocessors: an architecture-level evaluation.
IET Comput. Digit. Tech.
Xiangyu Dong, Xiaoxia Wu, Yuan Xie, Yiran Chen, Hai (Helen) Li
2011 J jnl
Three-dimensional Integrated Circuits: Design, EDA, and Architecture.
Found. Trends Electron. Des. Autom.
Guangyu Sun, Yibo Chen, Xiangyu Dong, Jin Ouyang, Yuan Xie
2010 — conf
3D memory stacking for fast checkpointing/restore applications.
3DIC
Jing Xie, Xiangyu Dong, Yuan Xie
2010 — conf
Architectural benefits and design challenges for three-dimensional integrated circuits.
APCCAS
Jing Xie, Jishen Zhao, Xiangyu Dong, Yuan Xie
2010 A* conf
Cost-aware three-dimensional (3D) many-core multiprocessor design.
DAC
Jishen Zhao, Xiangyu Dong, Yuan Xie
2010 A* conf
Cost-driven 3D integration with interconnect layers.
DAC
Xiaoxia Wu, Guangyu Sun, Xiangyu Dong, Reetuparna Das, Yuan Xie, Chita R. Das, Jian Li
2010 — conf
Energy and performance driven circuit design for emerging phase-change memory.
ASP-DAC
Dimin Niu, Yibo Chen, Xiangyu Dong, Yuan Xie
2010 A conf
Energy- and endurance-aware design of phase change memory caches.
DATE
Yongsoo Joo, Dimin Niu, Xiangyu Dong, Guangyu Sun, Naehyuck Chang, Yuan Xie
2010 J jnl
Fabrication Cost Analysis and Cost-Aware Design Space Exploration for 3-D ICs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Xiangyu Dong, Jishen Zhao, Yuan Xie
2010 A conf
Simple but Effective Heterogeneous Main Memory with On-Chip Memory Controller Support.
SC
Xiangyu Dong, Yuan Xie, Naveen Muralimanohar, Norman P. Jouppi
2009 C conf
3D GPU architecture using cache stacking: Performance, cost, power and thermal analysis.
ICCD
Ahmed Al-Maashri, Guangyu Sun, Xiangyu Dong, Vijay Narayanan, Yuan Xie
2009 A* conf
A novel architecture of the 3D stacked MRAM L2 cache for CMPs.
HPCA
Guangyu Sun, Xiangyu Dong, Yuan Xie, Jian Li, Yiran Chen
2009 A conf
Leveraging 3D PCRAM technologies to reduce checkpoint overhead for future exascale systems.
SC
Xiangyu Dong, Naveen Muralimanohar, Norman P. Jouppi, Richard Kaufmann, Yuan Xie
2009 A conf
PCRAMsim: System-level performance, energy, and area modeling for Phase-Change RAM.
ICCAD
Xiangyu Dong, Norman P. Jouppi, Yuan Xie
2009 — conf
System-level cost analysis and design exploration for three-dimensional integrated circuits (3D ICs).
ASP-DAC
Xiangyu Dong, Yuan Xie
2008 A* conf
Circuit and microarchitecture evaluation of 3D stacking magnetic RAM (MRAM) as a universal memory replacement.
DAC
Xiangyu Dong, Xiaoxia Wu, Guangyu Sun, Yuan Xie, Hai Li, Yiran Chen