Xianghong Hu

23 papers A* 1Journal 20Unranked 2
YearRankTypeTitle / Venue / Authors
2026 J jnl
An efficient DSP packing framework for FPGA-based mixed-precision DCNN processor.
J. Syst. Archit.
Xueming Li, Jinhui Pan, Hongmin Huang, Yuanmiao Lin, Xianghong Hu, Shuting Cai, Xiaoming Xiong
2025 J jnl
A DSP-Based Precision-Scalable MAC With Hybrid Dataflow for Arbitrary-Basis-Quantization CNN Accelerator.
IEEE Comput. Archit. Lett.
Yuanmiao Lin, Shansen Fu, Xueming Li, Chaoming Yang, Rongfeng Li, Hongmin Huang, Xianghong Hu, Shuting Cai, Xiaoming Xiong
2025 J jnl
A High-Efficiency CNN Accelerator With Mixed Low-Precision Quantization.
IET Circuits Devices Syst.
Xianghong Hu, Jinhui Pan, Yue Ding, Wenji Huang, Zhejun Zheng, Xueming Li, Hongmin Huang, Xiaoming Xiong
2025 J jnl
A Multiple-Aspect Optimal CNN Accelerator in Top1 Accuracy, Performance, and Power Efficiency.
IEEE Comput. Archit. Lett.
Xianghong Hu, Yuanmiao Lin, Xueming Li, Ruidian Zhan, Jie Cao, Dayong Zhu, Shuting Cai, Xin Zheng, Xiaoming Xiong
2025 J jnl
A Precision-Scalable Accelerator with Sign-Magnitude Representation and Dual Adder Trees.
ACM Trans. Embed. Comput. Syst.
Xianghong Hu, Chaoming Yang, Xueming Li, Rongfeng Li, Yuanmiao Lin, Shansen Fu, Hongmin Huang, Shuting Cai, Xiaoming Xiong
2025 J jnl
A precision-scalable sparse CNN accelerator with fine-grained mixed bitwidth configurability.
IEICE Electron. Express
Rongfeng Li, Xueming Li, Chaoming Yang, Xianghong Hu, Yuanmiao Lin, Shansen Fu, Hongmin Huang, Shuting Cai, Xiaoming Xiong
2025 J jnl
An FPGA Accelerator With Efficient Weight Compression by Combining Bit-Level Sparsity and Mixed-Precision Quantization.
IEEE Trans. Circuits Syst. II Express Briefs
Yuanmiao Lin, Zhaozhang Feng, Xueming Li, Hongmin Huang, Ruidian Zhan, Xianghong Hu, Shuting Cai, Xiaoming Xiong
2025 J jnl
An FPGA-based bit-level weight sparsity and mixed-bit accelerator for neural networks.
J. Syst. Archit.
Xianghong Hu, Shansen Fu, Yuanmiao Lin, Xueming Li, Chaoming Yang, Rongfeng Li, Hongmin Huang, Shuting Cai, Xiaoming Xiong
2024 J jnl
An Efficient VCD Parser for Dynamic Power Estimation of Digital Integrated Circuits.
IEEE Embed. Syst. Lett.
Xin Zheng, Shaofen Zeng, Yongfeng Zhong, Chenyu Huang, Xianghong Hu, Xiaoming Xiong
2023 J jnl
A Tiny Accelerator for Mixed-Bit Sparse CNN Based on Efficient Fetch Method of SIMO SPad.
IEEE Trans. Circuits Syst. II Express Briefs
Xianghong Hu, Xuejiao Liu, Yu Liu, Haowei Zhang, Xijie Huang, Xihao Guan, Luhong Liang, Chi-Ying Tsui, Xiaoming Xiong, Kwang-Ting Cheng
2023 J jnl
High-performance Reconfigurable DNN Accelerator on a Bandwidth-limited Embedded System.
ACM Trans. Embed. Comput. Syst.
Xianghong Hu, Hongmin Huang, Xueming Li, Xin Zheng, Qinyuan Ren, Jingyu He, Xiaoming Xiong
2022 J jnl
A hardware-efficient computing engine for FPGA-based deep convolutional neural network accelerator.
Microelectron. J.
Xueming Li, Hongmin Huang, Taosheng Chen, Huaien Gao, Xianghong Hu, Xiaoming Xiong
2022 J jnl
A high speed processor for elliptic curve cryptography over NIST prime field.
IET Circuits Devices Syst.
Xianghong Hu, Xueming Li, Xin Zheng, Yuan Liu, Xiaoming Xiong
2022 — conf
An Efficient Parallel Architecture for Convolutional Neural Networks Accelerator on FPGAs.
HP3C
Hongmin Huang, Xueming Li, Yadong Qin, Xianghong Hu, Xiaoming Xiong
2022 J jnl
An efficient loop tiling framework for convolutional neural network inference accelerators.
IET Circuits Devices Syst.
Hongmin Huang, Xianghong Hu, Xueming Li, Xiaoming Xiong
2022 A* conf
SDQ: Stochastic Differentiable Quantization with Mixed Precision.
ICML
Xijie Huang, Zhiqiang Shen, Shichao Li, Zechun Liu, Xianghong Hu, Jeffry Wicaksana, Eric P. Xing, Kwang-Ting Cheng
2022 J jnl
SDQ: Stochastic Differentiable Quantization with Mixed Precision.
CoRR
Xijie Huang, Zhiqiang Shen, Shichao Li, Zechun Liu, Xianghong Hu, Jeffry Wicaksana, Eric P. Xing, Kwang-Ting Cheng
2022 — conf
TAC-RAM: A 65nm 4Kb SRAM Computing-in-Memory Design with 57.55 TOPS/W supporting Multibit Matrix-Vector Multiplication for Binarized Neural Network.
AICAS
Xiaomeng Wang, Xuejiao Liu, Xianghong Hu, Xiaopeng Zhong, Xizi Chen, Yu Liu, Patrick Kong, Fengshi Tian, Chi-Ying Tsui
2022 J jnl
TiNNA: A Tiny Accelerator for Neural Networks With Efficient DSP Optimization.
IEEE Trans. Circuits Syst. II Express Briefs
Xianghong Hu, Xueming Li, Hongmin Huang, Xin Zheng, Xiaoming Xiong
2021 J jnl
Low-Power Reconfigurable Architecture of Elliptic Curve Cryptography for IoT.
IEICE Trans. Electron.
Xianghong Hu, Hongmin Huang, Xin Zheng, Yuan Liu, Xiaoming Xiong
2021 J jnl
Subgraph feature extraction based on multi-view dictionary learning for graph classification.
Knowl. Based Syst.
Xin Zheng, Shouzhi Liang, Bo Liu, Xiaoming Xiong, Xianghong Hu, Yuan Liu
2020 J jnl
The Software/Hardware Co-Design and Implementation of SM2/3/4 Encryption/Decryption and Digital Signature System.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Xin Zheng, Chongyao Xu, Xianghong Hu, Yun Zhang, Xiaoming Xiong
2019 J jnl
A Resources-Efficient Configurable Accelerator for Deep Convolutional Neural Networks.
IEEE Access
Xianghong Hu, Yuhang Zeng, Zicong Li, Xin Zheng, Shuting Cai, Xiaoming Xiong