Xiangdong Chen

62 papers A* 2A 2B 1C 3Misc 1Journal 34Unranked 19
YearRankTypeTitle / Venue / Authors
2026 J jnl
IEEE Trans. Veh. Technol.
Qingquan Liu, Xiangdong Chen, Shen Li, Meng Li
2026 J jnl
Knowl. Based Syst.
Xiaomei Long, Xinyue Wang, Cheng Yang, Zongbo He, Qian He, Xiangdong Chen
2025 A* conf
SOSP
Xiangdong Chen, Zhaofeng Li, Jerry Zhang, Vikram Narayanan, Anton Burtsev
2025 J jnl
Energy Inform.
Ziming Ouyang, Zhaohui Li, Xiangdong Chen
2025 J jnl
Energy Inform.
Ziming Ouyang, Zhaohui Li, Xiangdong Chen
2025 J jnl
Inf. Sci.
Cheng Yang, Xiangdong Chen, Mengjia Ruan
2025 C conf
INDIN
Tuan Li, Xiangdong Chen, Yuhao Xiao, Zhigang Wang, Ning Fu, Jun Ma
2025 J jnl
Eng. Appl. Artif. Intell.
Xinyue Wang, Xiangdong Chen, Jun Jiang, Ronggao Gong, Biao Wang
2025 A conf
ACSAC
Zhaofeng Li, Jerry Zhang, Joshua Tlatelpa-Agustin, Xiangdong Chen, Anton Burtsev
2024 J jnl
IEEE Trans. Instrum. Meas.
Xing Ding, Jing Li, Kun Tang, Xiangdong Chen, Hui Li
2024 J jnl
IEEE Trans. Ind. Electron.
Haochi Ying, Xing Ding, Xiangdong Chen
2024 conf
USENIX ATC
Xiangdong Chen, Zhaofeng Li, Tirth Jain, Vikram Narayanan, Anton Burtsev
2024 A conf
ACSAC
Zhaofeng Li, Vikram Narayanan, Xiangdong Chen, Jerry Zhang, Anton Burtsev
2024 conf
KISV@SOSP
Xiangdong Chen, Zhaofeng Li, Jerry Zhang, Anton Burtsev
2023 conf
KISV@SOSP
Xiangdong Chen, Zhaofeng Li, Lukas Mesicek, Vikram Narayanan, Anton Burtsev
2023 conf
PLOS@SOSP
Arthur Lafrance, David Detweiler, Zhaofeng Li, Xiangdong Chen, Vikram Narayanan, Anton Burtsev
2022 J jnl
IEEE Trans. Instrum. Meas.
Xing Ding, Mingxin Zhu, Xiangdong Chen, Jiashu Zhang, Xiang Yu
2022 J jnl
Biomed. Signal Process. Control.
Huijun Ding, Qian Cen, Xiaoyu Si, Zhanpeng Pan, Xiangdong Chen
2022 conf
ICMIP
Yinan Wang, Rongchuan Cao, Yingzhou Guan, Xiangdong Chen, Tianliang Liu, Zhenghua Yu
2022 J jnl
IEEE Trans. Instrum. Meas.
Xing Ding, Jing Li, Xiangdong Chen, Jiashu Zhang, Mingxin Zhu
2022 J jnl
IEEE Trans. Image Process.
Xingxin He, Leyuan Fang, Mingkui Tan, Xiangdong Chen
2022 J jnl
Educ. Inf. Technol.
Chen Guo, Peter Shea, Xiangdong Chen
2022 conf
ITSC
Shan Jiang, Xi Lin, Meng Li, Xiangdong Chen
2022 conf
ITSC
Xiangdong Chen, Xi Lin, Meng Li
2021 conf
TALE
Jinwen Liu, Xiangdong Chen, Bin He, Ting Zhang
2021 J jnl
Inf.
Ming Li, Jason Li-Ying, Yuandi Wang, Xiangdong Chen
2021 J jnl
Int. J. Comput. Math.
Zhongguo Zhou, Tongtong Hang, Tengfei Jiang, Qi Zhang, Huiguo Tang, Xiangdong Chen
2021 J jnl
Transp. Sci.
Xiangdong Chen, Meng Li, Xi Lin, Yafeng Yin, Fang He
2020 J jnl
IEEE Access
Xiangdong Chen, Jianghong Deng
2020 J jnl
Neurocomputing
Xingxin He, Leyuan Fang, Hossein Rabbani, Xiangdong Chen, Zhimin Liu
2019 J jnl
IEEE Trans. Medical Imaging
Leyuan Fang, Chong Wang, Shutao Li, Hossein Rabbani, Xiangdong Chen, Zhimin Liu
2019 J jnl
IEEE Signal Process. Lett.
Laifeng Huang, Xingxin He, Leyuan Fang, Hossein Rabbani, Xiangdong Chen
2019 J jnl
J. Vis. Commun. Image Represent.
Leyuan Fang, Yuxuan Jin, Laifeng Huang, Siyu Guo, Guangzhe Zhao, Xiangdong Chen
2019 J jnl
J. Real Time Image Process.
Xiangdong Chen, Qi Wang, Young-Sup Lee
2019 conf
CSCL
Xiangdong Chen, Chen Guo
2018 J jnl
IEEE Trans. Instrum. Meas.
Xiang Yu, Xiangdong Chen, Xing Ding, Xuan Zhao
2018 conf
BigComp
Weiwei Miao, Jingping Yin, Chengling Jiang, Lei Wei, Xiangdong Chen, Bo Guo, Wei Li, Rui Liu, Jia Yu, Wen Ye
2018 C conf
ICCE
Chen Guo, Xiangdong Chen
2017 J jnl
Scientometrics
Ming Li, Xiangdong Chen, Gupeng Zhang
2017 conf
SITIS
Yipeng Hua, Xiaoyang Miao, Xiangdong Chen
2017 Misc conf
ISKE
Bin Wu, Han Yu, Xiangdong Chen
2017 J jnl
Inf.
Xiangdong Chen, Fei Wang, Wei Wang, Valerie Hunstock
2016 J jnl
IEEE Trans. Instrum. Meas.
Xing Ding, Xiangdong Chen, Wenzhuo Ma, Xinpeng Chen, Ning Li
2016 conf
ICIIP
Yiwei Wang, Xinyi Peng, Sichen Zhou, Xiangdong Chen
2016 conf
WCSP
Mingxia Liu, Xiangdong Chen, Wei Xu, Hua Zhang, Xiaohu You, Weiwei Miao
2015 conf
SITIS
Xiangdong Chen, Liwen He, Jiaye Tang, Young-Sup Lee
2015 J jnl
IEEE Trans. Circuits Syst. Video Technol.
Xiangdong Chen, Liwen He, Gwanggil Jeon, Jechang Jeong
2015 J jnl
计算机科学
Xiangdong Chen
2014 conf
ICHL
Chen Qiao, Xiangdong Chen
2014 J jnl
IEEE Trans. Circuits Syst. Video Technol.
Xiangdong Chen, Gwanggil Jeon, Jechang Jeong
2014 J jnl
J. Electronic Imaging
Xiangdong Chen, Gwanggil Jeon, Jechang Jeong, Liwen He
2013 J jnl
Digit. Signal Process.
Xiangdong Chen, Gwanggil Jeon, Jechang Jeong
2012 J jnl
IEICE Trans. Commun.
Xiangdong Chen, Gwanggil Jeon, Jechang Jeong
2012 conf
IC-NIDC
Xiangdong Chen, Jechang Jeong
2012 C conf
VCIP
Xiangdong Chen, Jechang Jeong, Gwanggil Jeon
2011 J jnl
Quantum Inf. Process.
Wenliang Jin, Xiangdong Chen
2010 conf
ICHL
Dandan Gao, Xiangdong Chen
2009 conf
CSIE (2)
Xiangdong Chen, Jun Xia, Aizhong Ye, Yongyong Zhang
2004 J jnl
IEEE Multim.
Zhiying Zhou, Adrian David Cheok, Wei Liu, Xiangdong Chen, Farzam Farbiz, Xubo Yang, Michael Haller
2002 conf
IWEC
Zhiying Zhou, Farzam Farbiz, Xiangdong Chen, Adrian David Cheok, Lin Wei
1999 A* conf
ICRA
Xiangjing An, Wensen Chang, Xiangdong Chen
1999 B conf
IJCNN
Shoujue Wang, Huaxiang Li, Xiangdong Chen, Yujian Li
redb/extractors/decompiler/bninja/arch/x86.py
← Index redb/extractors/decompiler/bninja/arch/x86.py python
from binaryninja.enums import (
    InstructionTextTokenType,
)

# Support both package and standalone imports
try:
    from .architecture import Architecture
except ImportError:
    # Fallback to absolute imports (for multiprocessing spawned processes)
    from redb.extractors.decompiler.bninja.arch.architecture import Architecture


class Arch_x86(Architecture):
    """The concrete class for architecture-dependent details for x86_64"""

    def __init__(self):
        # general purpose registers for 64bits
        self.gpr_64 = [
            "RAX",
            "RBX",
            "RCX",
            "RDX",
            "RSI",
            "RDIR9",
            "R10",
            "R11",
            "R12",
            "R13",
            "R14",
            "R15",
        ]

        self.gpr_32 = [
            "EAX",
            "EBX",
            "ECX",
            "EDX",
            "ESI",
            "EDI",
            "R8D",
            "R9D",
            "R10D",
            "R11D",
            "R12D",
            "R13D",
            "R14D",
            "R15D",
        ]

        self.gpr_16 = [
            "AX",
            "BX",
            "CX",
            "DX",
            "SI",
            "DI",
            "R8W",
            "R9W",
            "R10W",
            "R11W",
            "R12W",
            "R13W",
            "R14W",
            "R15W",
        ]

        self.gpr_8 = [
            "AL",
            "BL",
            "CL",
            "DL",
            "SIL",
            "DIL",
            "R8B",
            "R9B",
            "R10B",
            "R11B",
            "R12B",
            "R13B",
            "R14B",
            "R15B",
        ]

        self.fpu_x87 = ["ST0", "ST1", "ST2", "ST3", "ST4", "ST5", "ST6", "ST7"]

        self.sse_xmm = [
            "XMM0",
            "XMM1",
            "XMM2",
            "XMM3",
            "XMM4",
            "XMM5",
            "XMM6",
            "XMM7",
            "XMM8",
            "XMM9",
            "XMM10",
            "XMM11",
            "XMM12",
            "XMM13",
            "XMM14",
            "XMM15",
        ]

        self.avx_ymm = [
            "YMM0",
            "YMM1",
            "YMM2",
            "YMM3",
            "YMM4",
            "YMM5",
            "YMM6",
            "YMM7",
            "YMM8",
            "YMM9",
            "YMM10",
            "YMM11",
            "YMM12",
            "YMM13",
            "YMM14",
            "YMM15",
        ]
        self.flags = ["FLAGS", "EFLAGS", "RFLAGS"]
        self.stack_registers = ["RBP", "RSP", "SP", "BP"]
        self.size = 8
        self.global_registers = (
            self.gpr_64
            + self.gpr_32
            + self.gpr_16
            + self.gpr_8
            + self.fpu_x87
            + self.sse_xmm
            + self.avx_ymm
        )
        self.opcode_categories = self._initialize_opcode_categories()

        ## instructions
        self.instructions = []

    def is_register(self, register):
        register = register.upper()
        return register in self.global_registers

    def is_general_purpose_register(self, register):
        register = register.upper()
        return (
            register in self.gpr_64
            or register in self.gpr_32
            or register in self.gpr_16
            or register in self.gpr_8
        )

    def is_stack_register(self, register):
        register = register.upper()
        return register in self.stack_registers

    def is_xmm_register(self, register):
        register = register.upper()
        return register in self.sse_xmm

    def is_control_flow(self, instr_tokens):
        return False

    def is_control_flow_instruction(self, instr_tokens):
        """Check if an instruction is a control flow instruction (jump, call, return, loop)."""
        try:
            # Extract the mnemonic from the instruction tokens
            mnemonic = None
            for token in instr_tokens:
                if token.type == InstructionTextTokenType.InstructionToken:
                    mnemonic = token.text.upper()
                    break

            if not mnemonic:
                return False

            # Check if it's a jump, call, return, or loop instruction
            return (
                mnemonic.startswith("J")  # All jumps (JMP, JE, JNE, etc.)
                or mnemonic == "CALL"  # Function calls
                or mnemonic == "RET"  # Return
                or mnemonic == "RETN"  # Another form of return
                or mnemonic.startswith("LOOP")
            )  # Loop instructions

        except Exception as e:
            print(e)
            # If we can't determine, assume it's not a control flow instruction
            return False

    def is_control_flow_instruction_by_mnemonic(self, mnemonic):
        """Check if an instruction is a control flow instruction based on its mnemonic."""
        if not mnemonic:
            return False

        mnemonic = mnemonic.upper()
        return (
            mnemonic.startswith("J")  # All jumps (JMP, JE, JNE, etc.)
            or mnemonic == "CALL"  # Function calls
            or mnemonic == "RET"  # Return
            or mnemonic == "RETN"  # Another form of return
            or mnemonic.startswith("LOOP")
        )

    def _initialize_opcode_categories(self):
        """Initialize mapping of opcodes to categories similar to Ghidra's implementation."""
        opcode_categories = {}
        opcode_index = {}  # Add this to mimic Ghidra's opcodeIndex

        # Define common opcodes array similar to Ghidra's COMMON_OPCODES
        COMMON_OPCODES = [
            # Core instructions (tracked individually)
            "MOV",
            "PUSH",
            "POP",
            "LEA",
            "CALL",
            "RET",  # Data movement and control
            "ADD",
            "SUB",
            "MUL",
            "DIV",  # Basic arithmetic
            "AND",
            "OR",
            "XOR",
            "NOT",  # Logical operations
            "JMP",
            "JE",
            "JNE",  # Basic jumps
            "TEST",
            "CMP",  # Comparisons
            # Grouped categories (aggregated tracking)
            "SIMD_MOVE",  # MOVAPS, MOVDQA, MOVDQU, etc.
            "COND_JUMP_EXT",  # Other conditional jumps (JG, JL, JGE, etc.)
            "STRING_OP",  # MOVS, STOS, LODS, SCAS, CMPS
            "STACK_ADV",  # ENTER, LEAVE, PUSHA, POPA
            "ARITHMETIC_ADV",  # IMUL, IDIV, ADC, SBB
            "BIT_OP",  # SHL, SHR, SAR, ROL, ROR, etc.
            "FPU_OP",  # FLD, FST, FADD, etc.
            "SYSTEM_OP",  # SYSCALL, INT, SYSENTER
            "CRYPTO_OP",  # AES*, SHA* instructions
            "MISC_OP",  # Rare but interesting (CPUID, RDTSC, etc.)
        ]

        # Create index map like Ghidra
        for i, opcode in enumerate(COMMON_OPCODES):
            opcode_index[opcode] = i

        # Now categorize opcodes using if/elif/else structure like in Ghidra
        for opcode in COMMON_OPCODES:
            # String Operations (checking these first to avoid MOV confusion)
            if opcode.startswith("MOVS") or opcode in [
                "STOS",
                "LODS",
                "SCAS",
                "CMPS",
                "REP",
                "REPE",
                "REPNE",
            ]:
                opcode_categories[opcode] = "STRING_MANIPULATION"

            # Data Movement (after string ops to avoid MOVS confusion)
            elif opcode.startswith("MOV") or opcode in ["LEA", "XCHG"]:
                opcode_categories[opcode] = "DATA_MOVEMENT"

            # Stack Operations
            elif opcode in ["PUSH", "POP", "ENTER", "LEAVE", "PUSHA", "POPA"]:
                opcode_categories[opcode] = "STACK_MANAGEMENT"

            # Control Flow (non-conditional)
            elif opcode in ["JMP", "CALL", "RET"]:
                opcode_categories[opcode] = "CONTROL_FLOW"

            # Conditional Jumps and Loops
            elif opcode.startswith("J") or opcode.startswith("LOOP"):
                opcode_categories[opcode] = "CONDITIONAL_JUMP"

            # Arithmetic
            elif opcode in [
                "ADD",
                "SUB",
                "MUL",
                "DIV",
                "IMUL",
                "IDIV",
                "ADC",
                "SBB",
                "INC",
                "DEC",
                "NEG",
            ]:
                opcode_categories[opcode] = "ARITHMETIC"

            # Logical
            elif opcode in ["AND", "OR", "XOR", "NOT", "TEST", "CMP"]:
                opcode_categories[opcode] = "LOGICAL"

            # Shifts & Rotates
            elif opcode in ["SHL", "SHR", "SAR", "SAL", "ROL", "ROR", "RCL", "RCR"]:
                opcode_categories[opcode] = "SHIFT_ROTATE"

            # System & Interrupts
            elif opcode in [
                "SYSCALL",
                "INT",
                "SYSENTER",
                "SYSEXIT",
                "SGDT",
                "SIDT",
                "SLDT",
                "WRMSR",
                "RDMSR",
            ]:
                opcode_categories[opcode] = "SYSTEM_CALLS"

            # Floating Point
            elif opcode.startswith("F"):
                opcode_categories[opcode] = "FPU_ARITHMETIC"

            # System Information and Random Number Generation
            elif opcode in ["PUSHF", "POPF", "CPUID", "RDTSC", "RDRAND", "RDSEED"]:
                opcode_categories[opcode] = "CPU_FEATURES"

            # Cryptography
            elif opcode.startswith("AES") or opcode.startswith("SHA"):
                opcode_categories[opcode] = "CRYPTOGRAPHIC"

            # Miscellaneous (including flag operations)
            else:
                opcode_categories[opcode] = "MISC"

        # Additional categorization for opcodes not in COMMON_OPCODES
        # This can be used in the normalize_opcode method

        # Store both maps as instance variables
        # self.opcode_categories = opcode_categories
        self.opcode_index = opcode_index

        return opcode_categories

    def is_simd_register(self, register):
        return register in self.sse_xmm