Xiang Gao

17 papers C 1Journal 5Unranked 11
YearRankTypeTitle / Venue / Authors
2025 J jnl
A Dual-Path SPD/PFD PLL With PVT-Insensitive Loop Bandwidth.
IEEE Solid State Circuits Lett.
Yan Chen, Gaofeng Jin, Haojie Xu, Yu Cui, Lei Zeng, Xiang Gao
2025 J jnl
A Low-Jitter Fractional-N LC-PLL With a 1/4 DTC-Range-Reduction Technique.
IEEE Solid State Circuits Lett.
Gaofeng Jin, Fei Feng, Yan Chen, Hanli Liu, Xiang Gao
2024 — conf
+A 112Gbps DSP-Based PAM4 SerDes Receiver with a Wide Band Equalization Tuning AFE in 7nm FinFET.
ICTA
Huanan Guo, Yufeng Yao, Jiazhen Ni, Xiang Gao
2024 J jnl
A Fractional-N Sampling PLL With a Merged Constant-Slope DTC and Sampling PD.
IEEE J. Solid State Circuits
Gaofeng Jin, Fei Feng, Wen Chen, Yiyang Shu, Xun Luo, Xiang Gao
2024 C conf
Analysis of Random Clock Jitter Effect in Time-Interleaved DACs.
ISCAS
Hong Chen, Nan Wang, Xiang Gao
2022 J jnl
A Flexible 0.73-15.5 GHz Single LC VCO Clock Generator in 12 nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs
Haojie Xu, Bao Luo, Gaofeng Jin, Fei Feng, Huanan Guo, Xiang Gao
2022 — conf
A Fully Synthesizable Injection Locked PLL with Dual-DCO Frequency Tracking in 55nm CMOS.
ICTA
Xuanchi Yu, Yan Chen, Gaofena Jin, Fei Feng, Xun Luo, Xiang Gao
2021 — conf
20.2 A 3.09-to-4.04GHz Distributed-Boosting and Harmonic-Impedance-Expanding Multi-Core Oscillator with-138.9dBc/Hz at 1MHz Offset and 195.1dBc/Hz FoM.
ISSCC
Yiyang Shu, Huizhen Jenny Qian, Xiang Gao, Xun Luo
2021 J jnl
A Low Phase Noise and High FoM Distributed-Swing-Boosting Multi-Core Oscillator Using Harmonic-Impedance-Expanding Technique.
IEEE J. Solid State Circuits
Yiyang Shu, Huizhen Jenny Qian, Xiang Gao, Xun Luo
2021 — conf
A calibration-free multi-phase sampling Type-II PLL.
ICTA
Haojie Xu, Gaofeng Jin, Jianan Wu, Huanan Guo, Xun Luo, Xiang Gao
2020 — conf
A Calibration-Free Low Spur Multi-Phase Sampling PLL.
ICTA
Gaofeng Jin, Bao Luo, Xiang Gao
2019 — conf
Low Jitter and Low Power PLL：Towards The Utopia.
ISOCC
Xiang Gao
2018 — conf
Tutorials: Low-Jitter PLLs for wireless transceivers.
ISSCC
Xiang Gao
2016 — conf
9.4 A 2×2 WLAN and Bluetooth combo SoC in 28nm CMOS with on-chip WLAN digital power amplifier, integrated 2G/BT SP3T switch and BT pulling cancelation.
ISSCC
Renaldi Winoto, Ashkan Olyaei, Mohammad Hajirostam, Wai Lau, Xiang Gao, Arnab Mitra, Ovidiu Carnu, Philip Godoy, Luns Tee, Hao Li, Erdem Erdogan, Alden Wong, Qiang Zhu, Timothy Loo, Fan Zhang, Liwei Sheng, Donghong Cui, Anuranjan Jha, Xiang Li, Wanghua Wu, Kun-Seok Lee, Derek Cheung, Ka Wo Pang, Haisong Wang, Jiexi Liu, Xingliang Zhao, Daibashish Gangopadhyay, David Cousinard, Arvind Anumula Paramanandam, Xiaoang Li, Norman Liu, Weiwei Xu, Yuan Fang, Xiaoyue Wang, Randy Tsang, Li Lin
2016 — conf
9.6 A 2.7-to-4.3GHz, 0.16psrms-jitter, -246.8dB-FOM, digital fractional-N sampling PLL in 28nm CMOS.
ISSCC
Xiang Gao, Olivier Burg, Haisong Wang, Wanghua Wu, Cao-Thong Tu, Konstantinos Manetakis, Fan Zhang, Luns Tee, Mustafa Yayla, Sining Xiang, Randy Tsang, Li Lin
2015 — conf
9.4 A 28nm CMOS digital fractional-N PLL with -245.5dB FOM and a frequency tripler for 802.11abgn/ac radio.
ISSCC
Xiang Gao, Luns Tee, Wanghua Wu, Kun-Seok Lee, Arvind Anumula Paramanandam, Anuranjan Jha, Norman Liu, Edwin Chan, Li Lin
2014 — conf
20.5 A 40nm dual-band 3-stream 802.11a/b/g/n/ac MIMO WLAN SoC with 1.1Gb/s over-the-air throughput.
ISSCC
Ming He, Renaldi Winoto, Xiang Gao, Wayne Loeb, David Signoff, Wai Lau, Yuan Lu, Donghong Cui, Kun-Seok Lee, Sai-Wang Tam, Philip Godoy, Yung Chen, Sanghoon Joo, Changhui Hu, Arvind Anumula Paramanandam, Xiaoyue Wang, Chi-Hung Lin, Li Lin