Xi Wang - RankMe

54 papers A* 8A 5B 5Journal 22Unranked 14

Year	Rank	Type	Title / Venue / Authors
2026	A*	`conf`	ChipMind: Retrieval-Augmented Reasoning for Long-Context Circuit Design Specifications. AAAI Changwen Xing, SamZaak Wong, Xinlai Wan, Yanfeng Lu, Mengli Zhang, Zebin Ma, Lei Qi, Zhengxiong Li, Nan Guan, Zhe Jiang, Xi Wang, Jun Yang
2026	A*	`conf`	FIXME: Towards End-to-End Benchmarking of LLM-Aided Design Verification. AAAI Gwok-Waa Wan, SamZaak Wong, Shengchu Su, Chenxu Niu, Ning Wang, Xinlai Wan, Qixiang Chen, Mengnv Xing, Jingyi Zhang, Jianmin Ye, Yubo Wang, Rongchang Song, Tao Ni, Qiang Xu, Nan Guan, Zhe Jiang, Xi Wang, Yong Chen, Jun Yang
2026	J	`jnl`	RTLocating: Intent-aware RTL Localization for Hardware Design Iteration. CoRR Changwen Xing, Yanfeng Lu, Lei Qi, Chenxu Niu, Jie Li, Xi Wang, Yong Chen, Jun Yang
2026	A*	`conf`	TokenPowerBench: Benchmarking the Power Consumption of LLM Inference. AAAI Chenxu Niu, Wei Zhang, Jie Li, Yongjian Zhao, Tongyang Wang, Xi Wang, Yong Chen
2025	J	`jnl`	ChatHLS: Towards Systematic Design Automation and Optimization for High-Level Synthesis. CoRR Runkai Li, Jia Xiong, Xiuyuan He, Jieru Zhao, Qiang Xu, Xi Wang
2025	J	`jnl`	ChatModel: Automating Reference Model Design and Verification with LLMs. CoRR Jianmin Ye, Tianyang Liu, Qi Tian, Shengchu Su, Zhe Jiang, Xi Wang
2025	J	`jnl`	ChipMind: Retrieval-Augmented Reasoning for Long-Context Circuit Design Specifications. CoRR Changwen Xing, SamZaak Wong, Xinlai Wan, Yanfeng Lu, Mengli Zhang, Zebin Ma, Lei Qi, Zhengxiong Li, Nan Guan, Zhe Jiang, Xi Wang, Jun Yang
2025	J	`jnl`	DeepCircuitX: A Comprehensive Repository-Level Dataset for RTL Code Understanding, Generation, and PPA Analysis. CoRR Zeju Li, Changran Xu, Zhengyuan Shi, Zedong Peng, Yi Liu, Yunhao Zhou, Lingfeng Zhou, Chengyu Ma, Jianyuan Zhong, Xi Wang, Jieru Zhao, Zhufei Chu, Xiaoyan Yang, Qiang Xu
2025	—	`conf`	EDA-Debugger: An LLM-Based Framework for Automated EDA Runtime Issue Resolution. ISQED Junyan Li, Sam-Zaak Wong, Gwok-Waa Wan, Xi Wang, Jun Yang
2025	J	`jnl`	FIXME: Towards End-to-End Benchmarking of LLM-Aided Design Verification. CoRR Gwok-Waa Wan, Shengchu Su, Ruihu Wang, Qixiang Chen, Sam-Zaak Wong, Mengnv Xing, Hefei Feng, Yubo Wang, Yinan Zhu, Jingyi Zhang, Jianmin Ye, Xinlai Wan, Tao Ni, Qiang Xu, Nan Guan, Zhe Jiang, Xi Wang, Yang Jun
2025	A	`conf`	From Concept to Practice: an Automated LLM-aided UVM Machine for RTL Verification. ICCAD Junhao Ye, Yuchen Hu, Ke Xu, Dingrong Pan, Qichun Chen, Jie Zhou, Shuai Zhao, Xinwei Fang, Xi Wang, Nan Guan, Zhe Jiang
2025	J	`jnl`	From Concept to Practice: an Automated LLM-aided UVM Machine for RTL Verification. CoRR Junhao Ye, Yuchen Hu, Ke Xu, Dingrong Pan, Qichun Chen, Jie Zhou, Shuai Zhao, Xinwei Fang, Xi Wang, Nan Guan, Zhe Jiang
2025	J	`jnl`	Insights from Verification: Training a Verilog Generation LLM with Reinforcement Learning with Testbench Feedback. CoRR Ning Wang, Bingkun Yao, Jie Zhou, Yuchen Hu, Xi Wang, Nan Guan, Zhe Jiang
2025	A*	`conf`	Location is Key: Leveraging LLM for Functional Bug Localization in Verilog Design. DAC Bingkun Yao, Ning Wang, Jie Zhou, Xi Wang, Hong Gao, Zhe Jiang, Nan Guan
2025	A	`conf`	MMCircuitEval: A Comprehensive Multimodal Circuit-Focused Benchmark for Evaluating LLMs. ICCAD Chenchen Zhao, Zhengyuan Shi, Xiangyu Wen, Chengjie Liu, Yi Liu, Yunhao Zhou, Yuxiang Zhao, Hefei Feng, Yinan Zhu, Gwok-Waa Wan, Xin Cheng, Weiyu Chen, Yongqi Fu, Chujie Chen, Chenhao Xue, Ying Wang, Yibo Lin, Jun Yang, Ning Xu, Xi Wang, Qiang Xu
2025	J	`jnl`	MMCircuitEval: A Comprehensive Multimodal Circuit-Focused Benchmark for Evaluating LLMs. CoRR Chenchen Zhao, Zhengyuan Shi, Xiangyu Wen, Chengjie Liu, Yi Liu, Yunhao Zhou, Yuxiang Zhao, Hefei Feng, Yinan Zhu, Gwok-Waa Wan, Xin Cheng, Weiyu Chen, Yongqi Fu, Chujie Chen, Chenhao Xue, Guangyu Sun, Ying Wang, Yibo Lin, Jun Yang, Ning Xu, Xi Wang, Qiang Xu
2025	A*	`conf`	ReChisel: Effective Automatic Chisel Code Generation by LLM with Reflection. DAC Juxin Niu, Xiangfeng Liu, Dan Niu, Xi Wang, Zhe Jiang, Nan Guan
2025	J	`jnl`	ReChisel: Effective Automatic Chisel Code Generation by LLM with Reflection. CoRR Juxin Niu, Xiangfeng Liu, Dan Niu, Xi Wang, Zhe Jiang, Nan Guan
2025	J	`jnl`	TokenPowerBench: Benchmarking the Power Consumption of LLM Inference. CoRR Chenxu Niu, Wei Zhang, Jie Li, Yongjian Zhao, Tongyang Wang, Xi Wang, Yong Chen
2025	A*	`conf`	UVLLM: An Automated Universal RTL Verification Framework using LLMs. DAC Yuchen Hu, Junhao Ye, Ke Xu, Jialin Sun, Shiyue Zhang, Xinyao Jiao, Dingrong Pan, Jie Zhou, Ning Wang, Weiwei Shan, Xinwei Fang, Xi Wang, Nan Guan, Zhe Jiang
2025	J	`jnl`	VeriDebug: A Unified LLM for Verilog Debugging via Contrastive Embedding and Guided Correction. CoRR Ning Wang, Bingkun Yao, Jie Zhou, Yuchen Hu, Xi Wang, Nan Guan, Zhe Jiang
2025	J	`jnl`	VerilogMonkey: Exploring Parallel Scaling for Automated Verilog Code Generation with LLMs. CoRR Juxin Niu, Yuxin Du, Dan Niu, Xi Wang, Zhe Jiang, Nan Guan
2024	J	`jnl`	A 0.61-μW Fully Integrated Keyword-Spotting ASIC With Real-Point Serial FFT-Based MFCC and Temporal Depthwise Separable CNN. IEEE J. Solid State Circuits Cai Li, Haochang Zhi, Kaiyue Yang, Junyi Qian, Zhihao Yan, Lixuan Zhu, Chao Chen, Xi Wang, Weiwei Shan
2024	A*	`conf`	ChatCPU: An Agile CPU Design and Verification Platform with LLM. DAC Xi Wang, Gwok-Waa Wan, Sam-Zaak Wong, Layton Zhang, Tianyang Liu, Qi Tian, Jianmin Ye
2024	J	`jnl`	DSC-TRCP: Dynamically Self-Calibrating Tunable Replica Critical Paths Based Timing Monitoring for Variation Resilient Circuits. IEEE J. Solid State Circuits Yuxuan Du, Junyi Qian, Zhengguo Shen, Chengjun Wu, Weiwei Shan, Xi Wang
2024	—	`conf`	Jailbreaking Pre-trained Large Language Models Towards Hardware Vulnerability Insertion Ability. ACM Great Lakes Symposium on VLSI Gwok-Waa Wan, Sam-Zaak Wong, Xi Wang
2024	J	`jnl`	Large Language Model for Verilog Generation with Golden Code Feedback. CoRR Ning Wang, Bingkun Yao, Jie Zhou, Xi Wang, Zhe Jiang, Nan Guan
2024	J	`jnl`	Location is Key: Leveraging Large Language Model for Functional Bug Localization in Verilog. CoRR Bingkun Yao, Ning Wang, Jie Zhou, Xi Wang, Hong Gao, Zhe Jiang, Nan Guan
2024	A	`conf`	MEIC: Re-thinking RTL Debug Automation using LLMs. ICCAD Ke Xu, Jialin Sun, Yuchen Hu, Xinwei Fang, Weiwei Shan, Xi Wang, Zhe Jiang
2024	J	`jnl`	MEIC: Re-thinking RTL Debug Automation using LLMs. CoRR Ke Xu, Jialin Sun, Yuchen Hu, Xinwei Fang, Weiwei Shan, Xi Wang, Zhe Jiang
2024	—	`conf`	Make Each Iteration Count. ACM TUR-C Yuchen Hu, Ke Xu, Jialin Sun, Xinwei Fang, Weiwei Shan, Xi Wang, Zhe Jiang
2024	J	`jnl`	UVLLM: An Automated Universal RTL Verification Framework using LLMs. CoRR Yuchen Hu, Junhao Ye, Ke Xu, Jialin Sun, Shiyue Zhang, Xinyao Jiao, Dingrong Pan, Jie Zhou, Ning Wang, Weiwei Shan, Xinwei Fang, Xi Wang, Nan Guan, Zhe Jiang
2023	—	`conf`	Differential Game with Mixed Strategies: A Weak Approximation Approach. CDC Tao Xu, Xi Wang, Jianping He
2021	—	`conf`	CircusTent: A Tool for Measuring the Performance of Atomic Memory Operations on Emerging Architectures. OpenSHMEM Brody Williams, John D. Leidel, Xi Wang, David Donofrio, Yong Chen
2021	—	`conf`	DMM-GAPBS: Adapting the GAP Benchmark Suite to a Distributed Memory Model. HPEC Zach Hansen, Brody Williams, John D. Leidel, Xi Wang, Yong Chen
2021	J	`jnl`	HAM: Hotspot-Aware Manager for Improving Communications With 3D-Stacked Memory. IEEE Trans. Computers Xi Wang, Antonino Tumeo, John D. Leidel, Jie Li, Yong Chen
2021	A	`conf`	xBGAS: A Global Address Space Extension on RISC-V for High Performance Computing. IPDPS Xi Wang, John D. Leidel, Brody Williams, Alan Ehret, Miguel Mark, Michel A. Kinsy, Yong Chen
2020	—	`conf`	CircusTent: A Benchmark Suite for Atomic Memory Operations. MEMSYS Brody Williams, John D. Leidel, Xi Wang, David Donofrio, Yong Chen
2020	A	`conf`	PAC: Paged Adaptive Coalescer for 3D-Stacked Memory. HPDC Xi Wang, John D. Leidel, Brody Williams, Yong Chen
2020	A*	`conf`	Remote Atomic Extension (RAE) for Scalable High Performance Computing. DAC Xi Wang, Brody Williams, John D. Leidel, Alan Ehret, Michel A. Kinsy, Yong Chen
2020	J	`jnl`	Toward a Microarchitecture for Efficient Execution of Irregular Applications. ACM Trans. Parallel Comput. John D. Leidel, Xi Wang, Brody Williams, Yong Chen
2019	—	`conf`	Collective Communication for the RISC-V xBGAS ISA Extension. ICPP Workshops Brody Williams, Xi Wang, John D. Leidel, Yong Chen
2019	B	`conf`	MAC: Memory Access Coalescer for 3D-Stacked Memory. ICPP Xi Wang, Antonino Tumeo, John D. Leidel, Jie Li, Yong Chen
2019	—	`conf`	PIMS: a lightweight processing-in-memory accelerator for stencil computations. MEMSYS Jie Li, Xi Wang, Antonino Tumeo, Brody Williams, John D. Leidel, Yong Chen
2019	B	`conf`	POSTER: Memory Hotspot Optimization for Data-Intensive Applications. PACT Xi Wang, Jie Li, Antonino Tumeo, John D. Leidel, Yong Chen
2018	—	`conf`	GoblinCore-64: A RISC-V Based Architecture for Data Intensive Computing. HPEC John D. Leidel, Xi Wang, Yong Chen
2018	B	`conf`	Memory Coalescing for Hybrid Memory Cube. ICPP Xi Wang, John D. Leidel, Yong Chen
2018	—	`conf`	xBGAS: Toward a RISC-V ISA Extension for Global, Scalable Shared Memory. MCHPC@SC John D. Leidel, Xi Wang, Frank Conlon, Yong Chen, David Donofrio, Farzad Fatollahi-Fard, Kurt Keville
2017	—	`conf`	OpenMP Memkind: An Extension for Heterogeneous Physical Memories. ICPP Workshops Xi Wang, John D. Leidel, Yong Chen
2017	B	`conf`	OpenSoC system architect: An open toolkit for building soft-cores on FPGAs. FPL Farzad Fatollahi-Fard, David Donofrio, John Shalf, John D. Leidel, Xi Wang, Yong Chen
2017	—	`conf`	Pressure-Driven Hardware Managed Thread Concurrency for Irregular Applications. IA3@SC John D. Leidel, Xi Wang, Yong Chen
2016	—	`conf`	Concurrent Dynamic Memory Coalescing on GoblinCore-64 Architecture. MEMSYS Xi Wang, John D. Leidel, Yong Chen
2009	J	`jnl`	Clustering aggregation by probability accumulation. Pattern Recognit. Xi Wang, Chunyu Yang, Jie Zhou
2008	B	`conf`	Spectral aggregation for clustering ensemble. ICPR Xi Wang, Chunyu Yang, Jie Zhou