Xi Jin - RankMe

61 papers A* 2A 7B 1C 2Misc 5Journal 23Unranked 21

Year	Rank	Type	Title / Venue / Authors
2025	A*	`conf`	Exploring the Performance Improvement of Tensor Processing Engines through Transformation in the Bit-weight Dimension of MACs. HPCA Qizhe Wu, Huawen Liang, Yuchen Gui, Zhichen Zeng, Zerong He, Linfeng Tao, Xiaotian Wang, Letian Zhao, Zhaoxi Zeng, Wei Yuan, Wei Wu, Xi Jin
2025	J	`jnl`	Exploring the Performance Improvement of Tensor Processing Engines through Transformation in the Bit-weight Dimension of MACs. CoRR Qizhe Wu, Huawen Liang, Yuchen Gui, Zhichen Zeng, Zerong He, Linfeng Tao, Xiaotian Wang, Letian Zhao, Zhaoxi Zeng, Wei Yuan, Wei Wu, Xi Jin
2025	J	`jnl`	F IEEE J. Emerg. Sel. Topics Circuits Syst. Zerong He, Xi Jin, Zhongguang Xu
2025	J	`jnl`	FANNS: An FPGA-Based Approximate Nearest-Neighbor Search Accelerator. IEEE Trans. Very Large Scale Integr. Syst. Wei Yuan, Xi Jin
2025	J	`jnl`	GHVSA: Graph-based high-dimensional vector search accelerator. J. Syst. Archit. Wei Yuan, Huawen Liang, Xi Jin
2025	A*	`conf`	MHE-TPE: Multi-Operand High-Radix Encoder for Mixed-Precision Fixed-Point Tensor Processing Engines. MICRO Qizhe Wu, Jinyi Zhou, Zhanhe Hu, Zhichen Zeng, Huawen Liang, Jiuru Zhu, Linfeng Tao, Xin Zhang, Zekang Cheng, Letian Zhao, Wei Yuan, Xiaotian Wang, Xi Jin
2025	C	`conf`	SageSC: Accelerating GraphSAGE Minibatch Inference on Memory-Intensive Graphs. ICCD Yuchen Gui, Wei Yuan, Qizhe Wu, Huawen Liang, Letian Zhao, Linfeng Tao, Zhongguang Xu, Xi Jin
2024	—	`conf`	A FPGA-HBM-Based Hardware Streaming Accelerator for GNN Sampling. ASAP Yuchen Gui, Qizhe Wu, Wei Yuan, Huawen Liang, Xiaotian Wang, Xi Jin
2024	—	`conf`	Artificial Neural Network based Model for Power GaN HEMTs down to 4.2K. ICTA Zikun Xiang, Haochen Zhang, Bolun Zeng, Lei Yang, Liling Qiu, Xi Jin, Guoping Guo, Chao Luo, Haiding Sun
2024	C	`conf`	EN-T: Optimizing Tensor Computing Engines Performance via Encoder-Based Methodology. ICCD Qizhe Wu, Yuchen Gui, Zhichen Zeng, Xiaotian Wang, Huawen Liang, Xi Jin
2024	J	`jnl`	EN-TensorCore: Advancing TensorCores Performance through Encoder-Based Methodology. CoRR Qizhe Wu, Yuchen Gui, Zhichen Zeng, Xiaotian Wang, Huawen Liang, Xi Jin
2024	A	`conf`	Efficient Message Passing Architecture for GCN Training on HBM-based FPGAs with Orthogonal Topology On-Chip Networks. FPGA Qizhe Wu, Letian Zhao, Yuchen Gui, Huawen Liang, Xiaotian Wang, Xi Jin
2024	—	`conf`	HBM-Based Hardware Accelerator for GNN Sampling and Aggregation. HPEC Yuchen Gui, Qizhe Wu, Wei Yuan, Huawen Liang, Xiaotian Wang, Xi Jin
2024	Misc	`conf`	RingTK: A Ring, Parallel and High Performance Top-K Sorter on FPGA. FCCM Huawen Liang, Qizhe Wu, Wei Yuan, Teng Tian, Xi Jin
2024	—	`conf`	Task-Level Parallelism for the Multifrontal Method in Tightly Coupled CPU-FPGA Architectures. HPEC Zerong He, Zekang Cheng, Zhongguang Xu, Xi Jin
2024	—	`conf`	Tightly-Coupled FPGA Accelerator for Molecular Dynamics Simulation: Hardware-Software Co-Design and Fine-Grained Task Management. HPEC Zekang Cheng, Zerong He, Xi Jin
2023	J	`jnl`	Degree-Aware Graph Neural Network Quantization. Entropy Ziqin Fan, Xi Jin
2023	—	`conf`	Dynamic Neural Network Accelerator for Multispectral detection Based on FPGA. ICACT Xiaotian Wang, Letian Zhao, Wei Wu, Xi Jin
2023	J	`jnl`	FTW-GAT: An FPGA-Based Accelerator for Graph Attention Networks With Ternary Weights. IEEE Trans. Circuits Syst. II Express Briefs Zerong He, Teng Tian, Qizhe Wu, Xi Jin
2023	—	`conf`	MCANet: Multiscale Cross-Modality Attention Network for Multispectral Pedestrian Detection. MMM (1) Xiaotian Wang, Letian Zhao, Wei Wu, Xi Jin
2023	—	`conf`	Scheduling Memory Access Optimization for HBM Based on CLOS. ICACT Shuang Xue, Huawei Liang, Qizhe Wu, Xi Jin
2022	—	`conf`	An SSD-Based Accelerator for Singular Value Decomposition Recommendation Algorithm on Edge. HPEC Wei Wu, Letian Zhao, Qizhe Wu, Xiaotian Wang, Teng Tian, Xi Jin
2022	J	`jnl`	BaPipe: Balanced Pipeline Parallelism for DNN Training. Parallel Process. Lett. Letian Zhao, Rui Xu, Tianqi Wang, Teng Tian, Xiaotian Wang, Wei Wu, Chio-In Ieong, Xi Jin
2022	J	`jnl`	Exploration of Balanced Design in Resource-Constrained Edge Device for Efficient CNNs. IEEE Trans. Circuits Syst. II Express Briefs Xiaotian Wang, Teng Tian, Letian Zhao, Wei Wu, Xi Jin
2022	J	`jnl`	FP-GNN: Adaptive FPGA accelerator for Graph Neural Networks. Future Gener. Comput. Syst. Teng Tian, Letian Zhao, Xiaotian Wang, Qizhe Wu, Wei Yuan, Xi Jin
2022	J	`jnl`	G-NMP: Accelerating Graph Neural Networks with DIMM-based Near-Memory Processing. J. Syst. Archit. Teng Tian, Xiaotian Wang, Letian Zhao, Wei Wu, Xuecang Zhang, Fangmin Lu, Tianqi Wang, Xi Jin
2022	J	`jnl`	Hardware Acceleration of Sampling Algorithms in Sample and Aggregate Graph Neural Networks. CoRR Yuchen Gui, Boyi Wei, Wei Yuan, Xi Jin
2022	—	`conf`	HuGraph: Acceleration of GCN Training on Heterogeneous FPGA Clusters with Quantization. HPEC Letian Zhao, Qizhe Wu, Xiaotian Wang, Teng Tian, Wei Wu, Xi Jin
2022	J	`jnl`	QEGCN: An FPGA-based accelerator for quantized GCNs with edge-level parallelism. J. Syst. Archit. Wei Yuan, Teng Tian, Qizhe Wu, Xi Jin
2021	B	`conf`	A Gather Accelerator for GNNs on FPGA Platform. ICPADS Wei Yuan, Teng Tian, Huawen Liang, Xi Jin
2021	J	`jnl`	A hybrid precision low power computing-in-memory architecture for neural networks. Microprocess. Microsystems Rui Xu, Linfeng Tao, Tianqi Wang, Xi Jin, Chenxia Li, Zhengda Li, Jun Ren
2021	—	`conf`	Software-Hardware Co-Optimization on Partial-Sum Problem for PIM-based Neural Network Accelerator. HPEC Qizhe Wu, Linfeng Tao, Huawen Liang, Wei Yuan, Teng Tian, Shuang Xue, Xi Jin
2020	J	`jnl`	A Real-Time Learning-Based Super-Resolution System on FPGA. Parallel Process. Lett. Daolu Zha, Xi Jin, Rui Shang, Pengfei Yang
2020	J	`jnl`	BaPipe: Exploration of Balanced Pipeline Parallelism for DNN Training. CoRR Letian Zhao, Rui Xu, Tianqi Wang, Teng Tian, Xiaotian Wang, Wei Wu, Chio-In Ieong, Xi Jin
2020	J	`jnl`	Enhancing energy efficiency of RISC-V processor-based embedded graphics systems through frame buffer compression. Microprocess. Microsystems Yuzhi Zhou, Xi Jin, Tian Xiang, Daolu Zha
2020	A	`conf`	Exploration of Memory Access Optimization for FPGA-based 3D CNN Accelerator. DATE Teng Tian, Xi Jin, Letian Zhao, Xiaotian Wang, Jie Wang, Wei Wu
2020	J	`jnl`	FPDeep: Scalable Acceleration of CNN Training on Deeply-Pipelined FPGA Clusters. IEEE Trans. Computers Tianqi Wang, Tong Geng, Ang Li, Xi Jin, Martin C. Herbordt
2020	J	`jnl`	FPGA Implementation of A∗ Algorithm for Real-Time Path Planning. Int. J. Reconfigurable Comput. Yuzhi Zhou, Xi Jin, Tianqi Wang
2020	—	`conf`	RISC-V Graphics Rendering Instruction Set Extensions for Embedded AI Chips Implementation. BDET Yuzhi Zhou, Xi Jin, Tian Xiang
2020	—	`conf`	TB-DNN: A Thin Binarized Deep Neural Network with High Accuracy. ICACT Jie Wang, Xi Jin, Wei Wu
2019	J	`jnl`	A Scalable Framework for Acceleration of CNN Training on Deeply-Pipelined FPGA Clusters with Weight and Workload Balancing. CoRR Tong Geng, Tianqi Wang, Ang Li, Xi Jin, Martin C. Herbordt
2019	—	`conf`	Accelerating AP3M-Based Computational Astrophysics Simulations with Reconfigurable Clusters. ASAP Tianqi Wang, Tong Geng, Xi Jin, Martin C. Herbordt
2019	A	`conf`	CINT - An Energy-efficient Mixed-signal In-Memory CNN Accelerator Based on NOR Flash Memory. MobiSys Linfeng Tao, Rui Xu, Teng Tian, Zikun Xiang, Yifei Li, Xi Jin, Jun Ren, Zhengda Li, Chenxia Li
2019	Misc	`conf`	FP-AMR: A Reconfigurable Fabric Framework for Adaptive Mesh Refinement Applications. FCCM Tianqi Wang, Tong Geng, Xi Jin, Martin C. Herbordt
2018	—	`conf`	A Real-Time Learning-Based Super-Resolution System Using Direct Simple Functions. ASAP Daolu Zha, Xi Jin, Rui Shang, Pengfei Yang
2018	—	`conf`	A pipelined division for fixed operation using user-defined floating point. ICACT Pengfei Yang, Daolu Zha, Xi Jin
2018	—	`conf`	Accelerating a radio astronomy correlator on FPGA. ICACT Shuaizhi Guo, Linlin Zheng, Xi Jin
2018	A	`conf`	An efficient resource-optimized learning prefetcher for solid state drives. DATE Rui Xu, Xi Jin, Linfeng Tao, Shuaizhi Guo, Zikun Xiang, Teng Tian
2018	J	`jnl`	RP-Ring: A Heterogeneous Multi-FPGA Accelerator. Int. J. Reconfigurable Comput. Shuaizhi Guo, Tianqi Wang, Linfeng Tao, Teng Tian, Zikun Xiang, Xi Jin
2018	—	`conf`	Soft-Core. Multiple-Lane, FPGA-based ADCs for a Liquid Helium Environment. HPEC Zikun Xiang, Tianqi Wang, Tong Geng, Tian Xiang, Xi Jin, Martin C. Herbordt
2017	—	`conf`	An Efficient Hardware Prefetcher Exploiting the Prefetch Potential of Long-Stride Access Pattern on Virtual Address. ISPA/IUCC Teng Tian, Tianqi Wang, Xi Jin
2016	J	`jnl`	A real-time global stereo-matching on FPGA. Microprocess. Microsystems Daolu Zha, Xi Jin, Tian Xiang
2016	J	`jnl`	An Accelerating Solution for N-Body MOND Simulation with FPGA-SoC. Int. J. Reconfigurable Comput. Bo Peng, Tianqi Wang, Xi Jin, Chuanjun Wang
2016	A	`conf`	An FPGA-SOC Based Accelerating Solution for N-body Simulations in MOND (Abstract Only). FPGA Bo Peng, Tianqi Wang, Xi Jin, Chuanjun Wang
2016	A	`conf`	An Improved Global Stereo-Matching on FPGA for Real-Time Applications (Abstract Only). FPGA Daolu Zha, Xi Jin, Tian Xiang
2016	—	`conf`	FPGA acceleration of TreePM N-body simulations for Modified Newton Dynamics. FPT Tianqi Wang, Linlin Zheng, Xi Jin, Bo Peng, Chuanjun Wang
2016	—	`conf`	Fixed-ratio DXT format Frame Buffer Compressor for mobile graphics systems. FPT Yuzhi Zhou, Xi Jin, Tian Xiang
2016	Misc	`conf`	RP-Ring: A Heterogeneous Multi-FPGA Accelerating Solution for N-Body Simulations. FCCM Tianqi Wang, Xi Jin, Bo Peng, Chuanjun Wang, Linlin Zheng
2016	A	`conf`	an Extensible Heterogeneous Multi-FPGA Framework for Accelerating N-body Simulation (Abstract Only). FPGA Tianqi Wang, Bo Peng, Xi Jin
2015	Misc	`conf`	Design of a Distributed Compressor for Astronomy SSD. FCCM Bo Peng, Xi Jin, Tianqi Wang, Xueliang Du
2014	Misc	`conf`	A Multi-phase Clock Time-to-Digital Convertor Based on ISERDES Architecture. FCCM Tian Xiang, Lei Zhao, Xi Jin, Tianqi Wang, Shaoping Chu, Cong Ma, Shubin Liu, Qi An, Xue Ben