Xi Chen

21 papers A* 1B 1C 1Misc 1Journal 8Unranked 9
YearRankTypeTitle / Venue / Authors
2026 — conf
30.1 A 28nm 127.54TFLOPS/W MXFP6 and 117.42TFLOPS/W MXFP8 Compute-in-Memory Macro with Adaptive-Preserved-Bit-Width and Serial-Dual-Bit-Sliding Schemes.
ISSCC
Xing Wang, Yucheng Du, Tianhui Jiao, Defa Wu, Xi Chen, Miaoyu Tang, Yi Yang, Zhichao Liu, An Guo, Gaoming Fu, Peng Li, Jun Dong, Bo Liu, Xinning Liu, Weiwei Shan, Hao Cai, Guangyu Sun, Lin Tong, Jun Yang, Xin Si
2026 J jnl
An LSGQ-FFS Framework for Adaptive Optimization of Hybrid INT-CIM Architecture.
IEEE Trans. Very Large Scale Integr. Syst.
Shaochen Li, Xi Chen, Yujia Xiong, Yuhan Liu, Lingyi Kong, He Wang, Tianhui Jiao, Xing Wang, Xiaomin Li, Yan Yan, Yuchen Ma, Xin Si
2025 — conf
14.6 A 28nm 64kb Bit-Rotated Hybrid-CIM Macro with an Embedded Sign-Bit-Processing Array and a Multi-Bit-Fusion Dual-Granularity Cooperative Quantizer.
ISSCC
Xi Chen, Shaochen Li, Zhican Zhang, Wentao Zheng, Xiao Tan, Yuchen Tang, Yuhui Shi, Lizheng Ren, Yibo Mai, Feiran Liu, Jinwu Chen, Zhaoyang Zhang, An Guo, Tianzhu Xiong, Bo Wang, Xinning Liu, Weiwei Shan, Bo Liu, Hao Cai, Jun Yang, Xin Si
2025 — conf
14.7 NeuroPilot: A 28nm, 69.4fJ/node and 0.22ns/node, 32×32 Mimetic-Path-Searching CIM-Macro with Dynamic-Logic Pilot PE and Dual-Direction Searching.
ISSCC
An Guo, Jingmin Zhang, Xingyu Pu, Yi Yang, Defa Wu, Yuchen Tang, Yuhui Shi, Yinghai Gao, Zhichao Liu, Bo Wang, Tianzhu Xiong, Zhaoyang Zhang, Xi Chen, Jinwu Chen, Feiran Liu, Xing Wang, Xinning Liu, Weiwei Shan, Bo Liu, Hao Cai, Xin Si, Jun Yang
2025 J jnl
A 22-nm 64-kB lightning-like hybrid computing-in-memory macro with a compressed adder tree and analog-storage quantizers for transformer and CNNs.
Sci. China Inf. Sci.
An Guo, Xi Chen, Fangyuan Dong, Jinwu Chen, Zhihang Yuan, Xing Hu, Guangyu Sun, Xiaomin Li, Arindam Basu, Jun Yang, Xin Si
2025 J jnl
A 28-nm 16-kb Aggregation and Combination Computing-in-Memory Macro With Dual-Level Sparsity Modulation and Sparse-Tracking ADCs for GCNs.
IEEE J. Solid State Circuits
Zhaoyang Zhang, Yanqi Zhang, Feiran Liu, Zhichao Liu, Yinhai Gao, Yuchen Ma, Yutong Zhang, An Guo, Tianzhu Xiong, Jinwu Chen, Xi Chen, Bo Wang, Yuchen Tang, Jun Yang, Xin Si
2025 A* conf
AIM: Software and Hardware Co-design for Architecture-level IR-drop Mitigation in High-performance PIM.
ISCA
Yuanpeng Zhang, Xing Hu, Xi Chen, Zhihang Yuan, Cong Li, Jingchen Zhu, Zhao Wang, Chenguang Zhang, Xin Si, Wei Gao, Qiang Wu, Runsheng Wang, Guangyu Sun
2025 J jnl
AIM: Software and Hardware Co-design for Architecture-level IR-drop Mitigation in High-performance PIM.
CoRR
Yuanpeng Zhang, Xing Hu, Xi Chen, Zhihang Yuan, Cong Li, Jingchen Zhu, Zhao Wang, Chenguang Zhang, Xin Si, Wei Gao, Qiang Wu, Runsheng Wang, Guangyu Sun
2025 C conf
Modeling of Less-Significant Group Quantization for Hybrid CIM Architecture.
ISCAS
Shaochen Li, Xi Chen, Lingyi Kong, He Wang, Xing Wang, Yi Yang, Xin Si
2025 — conf
TRIFP-DCIM: A Toggle-Rate-Immune Floating-point Digital Compute-in-Memory Design with Adaptive-Asymmetric Compute-Tree.
ASP-DAC
Xing Wang, Tianhui Jiao, Shaochen Li, Yuchen Ma, Zhican Zhang, Zhichao Liu, Xi Chen, Xin Si
2024 — conf
34.3 A 22nm 64kb Lightning-Like Hybrid Computing-in-Memory Macro with a Compressed Adder Tree and Analog-Storage Quantizers for Transformer and CNNs.
ISSCC
An Guo, Xi Chen, Fangyuan Dong, Jinwu Chen, Zhihang Yuan, Xing Hu, Yuanpeng Zhang, Jingmin Zhang, Yuchen Tang, Zhican Zhang, Gang Chen, Dawei Yang, Zhaoyang Zhang, Lizheng Ren, Tianzhu Xiong, Bo Wang, Bo Liu, Weiwei Shan, Xinning Liu, Hao Cai, Guangyu Sun, Jun Yang, Xin Si
2024 — conf
A 28nm 16kb Aggregation and Combination Computing-in-Memory Macro with Dual-level Sparsity Modulation and Sparse-Tracking ADCs for GCNs.
CICC
Zhaoyang Zhang, Zhichao Liu, Feiran Liu, Yinhai Gao, Yuchen Ma, Yutong Zhang, An Guo, Tianzhu Xiong, Jinwu Chen, Xi Chen, Bo Wang, Yuchen Tang, Xingyu Pu, Xing Wang, Jun Yang, Xin Si
2024 J jnl
Toggle Rate Aware Quantization Model Based on Digital Floating-Point Computing-In-Memory Architecture.
IEEE Trans. Circuits Syst. II Express Briefs
Xi Chen, Yitong Zhao, An Guo, Jinwu Chen, Fangyuan Dong, Zhaoyang Zhang, Tianzhu Xiong, Bo Wang, Yuyao Kong, Xin Si
2023 — conf
A 28nm 64-kb 31.6-TFLOPS/W Digital-Domain Floating-Point-Computing-Unit and Double-Bit 6T-SRAM Computing-in-Memory Macro for Floating-Point CNNs.
ISSCC
An Guo, Xin Si, Xi Chen, Fangyuan Dong, Xingyu Pu, Dongqi Li, Yongliang Zhou, Lizheng Ren, Yeyang Xue, Xueshan Dong, Hui Gao, Yiran Zhang, Jingmin Zhang, Yuyao Kong, Tianzhu Xiong, Bo Wang, Hao Cai, Weiwei Shan, Jun Yang
2023 — conf
Evaluation Model for Current-Domain SRAM-based Computing-in-Memory Circuits.
MCSoC
Yiran Zhang, Bo Wang, Jinwu Chen, Xi Chen, Xin Si
2023 J jnl
Evaluation Platform of Time-Domain Computing-in-Memory Circuits.
IEEE Trans. Circuits Syst. II Express Briefs
Yuyao Kong, Xi Chen, Xin Si, Jun Yang
2023 J jnl
From macro to microarchitecture: reviews and trends of SRAM-based compute-in-memory circuits.
Sci. China Inf. Sci.
Zhaoyang Zhang, Jinwu Chen, Xi Chen, An Guo, Bo Wang, Tianzhu Xiong, Yuyao Kong, Xingyu Pu, Shengnan He, Xin Si, Jun Yang
2022 — conf
A Quantization Model Based on a Floating-point Computing-in-Memory Architecture.
APCCAS
Xi Chen, An Guo, Xinbing Xu, Xin Si, Jun Yang
2022 J jnl
VCCIM: a voltage coupling based computing-in-memory architecture in 28 nm for edge AI applications.
CCF Trans. High Perform. Comput.
An Guo, Chen Xue, Xi Chen, Xin Si
2017 Misc conf
FP-DNN: An Automated Framework for Mapping Deep Neural Networks onto FPGAs with RTL-HLS Hybrid Templates.
FCCM
Yijin Guan, Hao Liang, Ningyi Xu, Wenqiang Wang, Shaoshuai Shi, Xi Chen, Guangyu Sun, Wei Zhang, Jason Cong
2017 B conf
FxpNet: Training a deep convolutional neural network in fixed-point representation.
IJCNN
Xi Chen, Xiaolin Hu, Hucheng Zhou, Ningyi Xu