Xi Chen - RankMe

21 papers A* 3A 4Journal 7Unranked 6

Year	Rank	Type	Title / Venue / Authors
2011	A*	`conf`	A method to leverage pre-silicon collateral and analysis for post-silicon testing and validation. DAC Gary Miller, Bandana Bhattarai, Yu-Chin Hsu, Jay Dutt, Xi Chen, George Bakewell
2009	J	`jnl`	Runtime deadlock analysis for system level design. Des. Autom. Embed. Syst. Eric Cheung, Xi Chen, Harry Hsieh, Abhijit Davare, Alberto L. Sangiovanni-Vincentelli, Yosinori Watanabe
2007	J	`jnl`	Assertion-Based Design Exploration of DVS in Network Processor Architectures CoRR Jia Yu, Wei Wu, Xi Chen, Harry Hsieh, Jun Yang, Felice Balarin
2007	—	`conf`	Bridging RTL and gate: correlating different levels of abstraction for design debugging. HLDVT Eric Cheung, Xi Chen, Fur-Shing Tsai, Yu-Chin Hsu, Harry Hsieh
2006	A	`conf`	Communication and co-simulation infrastructure for heterogeneous system integration. DATE Guang Yang, Xi Chen, Felice Balarin, Harry Hsieh, Alberto L. Sangiovanni-Vincentelli
2006	—	`conf`	Runtime Deadlock Analysis of SystemC Designs. HLDVT Eric Cheung, Piyush Satapathy, Vi Pham, Harry Hsieh, Xi Chen
2006	J	`jnl`	Verification Approach of Metropolis Design Framework for Embedded Systems. Int. J. Parallel Program. Xi Chen, Harry Hsieh, Felice Balarin
2005	A	`conf`	Assertion-Based Design Exploration of DVS in Network Processor Architectures. DATE Jia Yu, Wei Wu, Xi Chen, Harry Hsieh, Jun Yang, Felice Balarin
2005	A*	`conf`	Simulation based deadlock analysis for system level designs. DAC Xi Chen, Abhijit Davare, Harry Hsieh, Alberto L. Sangiovanni-Vincentelli, Yosinori Watanabe
2004	J	`jnl`	Assertion Based Verification and Analysis of Network Processor Architectures. Des. Autom. Embed. Syst. Xi Chen, Yan Luo, Harry Hsieh, Laxmi N. Bhuyan, Felice Balarin
2004	—	`conf`	Assertion-based power/performance analysis of network processor architectures. HLDVT Jia Yu, Wei Wu, Xi Chen, Harry Hsieh, Jun Yang, Felice Balarin
2004	J	`jnl`	Logic of constraints: a quantitative performance and functional constraint formalism. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Watanabe
2004	A	`conf`	Utilizing Formal Assertions for System Design of Network Processors. DATE Xi Chen, Yan Luo, Harry Hsieh, Laxmi N. Bhuyan, Felice Balarin
2003	A	`conf`	Automatic Generation of Simulation Monitors from Quantitative Constraint Formula. DATE Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Watanabe
2003	A*	`conf`	Automatic trace analysis for logic of constraints. DAC Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Watanabe
2003	—	`conf`	Case Studies of Model Checking for Embedded System Designs. ACSD Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Watanabe
2003	J	`jnl`	Formal Verification for Embedded System Designs. Des. Autom. Embed. Syst. Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Watanabe
2003	J	`jnl`	Shared memory multiprocessor architectures for software IP routers. IEEE Trans. Parallel Distributed Syst. Yan Luo, Laxmi Narayan Bhuyan, Xi Chen
2003	—	`ch.`	Simulation Trace Verification for Quantitative Constraints. Embedded Software for SoC Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Watanabe
2003	—	`conf`	Verifying LOC based functional and performance constraints. HLDVT Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Watanabe
2002	—	`conf`	Formal verification of embedded system designs at multiple levels of abstraction. HLDVT Xi Chen, Fang Chen, Harry Hsieh, Felice Balarin, Yosinori Watanabe