Wu-Tung Cheng

167 papers A* 5A 44B 10C 3Misc 14Journal 29Unranked 61
YearRankTypeTitle / Venue / Authors
2025 Misc conf
APT: Optimal Tree for Diagnosis Simulation.
VTS
Wu-Tung Cheng
2025 — conf
Improving Effect-Cause Diagnosis Performance with Minimal Memory Overhead on Asymmetric Partition Trees (APT).
ITC-Asia
Wu-Tung Cheng, Szczepan Urban, Manish Sharma, Jakub Janicki
2025 Misc conf
Innovation Practices Track: Frontiers in Diagnosis and Debug.
VTS
Suriyaprakash Natarajan, Saghir A. Shaikh, Wu-Tung Cheng, Sankaran Menon
2025 A conf
Using Distinguishing Bits to Improve Chain Diagnosis Coverage for Silicon Defects.
ITC
Wu-Tung Cheng, Manish Sharma, Artur Stelmach, Jakub Janicki, Preston McWithey, Gaurav Veda, Szczepan Urban, Jayant D'Souza
2024 A conf
Adaptive Diagnosis Points for 100% Chain Diagnosis Coverage.
ITC
Wu-Tung Cheng, Manish Sharma, Xin Yang, Artur Stelmach, Szczepan Urban, Jakub Janicki, Preston McWithey
2022 Misc conf
Accurate Estimation of Test Pattern Counts for a Wide-Range of EDT Input/Output Channel Configurations.
VTS
Shi-Xuan Zheng, Chung-Yu Yeh, Kuen-Jong Lee, Chen Wang, Wu-Tung Cheng, Mark Kassab, Janusz Rajski, Sudhakar M. Reddy
2022 J jnl
Efficient Test Compression Configuration Selection.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Chong-Siao Ye, Shi-Xuan Zheng, Fong-Jyun Tsai, Chen Wang, Kuen-Jong Lee, Wu-Tung Cheng, Sudhakar M. Reddy, Justyna Zawada, Mark Kassab, Janusz Rajski
2022 A conf
Industry Evaluation of Reversible Scan Chain Diagnosis.
ITC
Soumya Mittal, Szczepan Urban, Kun Young Chung, Jakub Janicki, Wu-Tung Cheng, Martin Parley, Manish Sharma, Shaun Nicholson
2021 J jnl
Autonomous Scan Patterns for Laser Voltage Imaging.
IEEE Trans. Emerg. Top. Comput.
Wu-Tung Cheng, Sylwester Milewski, Grzegorz Mrugalski, Janusz Rajski, Maciej Trawka, Jerzy Tyszer
2021 — conf
Diagnosis and Yield Learning.
ITC-Asia
Yu Huang, Wu-Tung Cheng, Ruifeng Guo, Sameer Chillarige
2021 — conf
On Modeling CMOS Library Cells for Cell Internal Fault Test Pattern Generation.
ATS
Xijiang Lin, Wu-Tung Cheng, Takeo Kobayashi, Andreas Glowatz
2020 J jnl
Diagnosis of Intermittent Scan Chain Faults Through a Multistage Neural Network Reasoning Process.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Mason Chern, Shih-Wei Lee, Shi-Yu Huang, Yu Huang, Gaurav Veda, Kun-Han Tsai, Wu-Tung Cheng
2020 B conf
Efficient Prognostication of Pattern Count with Different Input Compression Ratios.
ETS
Fong-Jyun Tsai, Chong-Siao Ye, Yu Huang, Kuen-Jong Lee, Wu-Tung Cheng, Sudhakar M. Reddy, Mark Kassab, Janusz Rajski
2020 — conf
Estimation of Test Data Volume for Scan Architectures with Different Numbers of Input Channels.
ITC-Asia
Fong-Jyun Tsai, Chong-Siao Ye, Yu Huang, Kuen-Jong Lee, Wu-Tung Cheng, Sudhakar M. Reddy, Mark Kassab, Janusz Rajski, Shi-Xuan Zheng
2020 — conf
GPU-based Hybrid Parallel Logic Simulation for Scan Patterns.
ITC-Asia
Liyang Lai, Qiting Zhang, Kun-Han Hans Tsai, Wu-Tung Cheng
2020 A conf
Prediction of Test Pattern Count and Test Data Volume for Scan Architectures under Different Input Channel Configurations.
ITC
Fong-Jyun Tsai, Chong-Siao Ye, Kuen-Jong Lee, Shi-Xuan Zheng, Yu Huang, Wu-Tung Cheng, Sudhakar M. Reddy, Mark Kassab, Janusz Rajski, Chen Wang, Justyna Zawada
2020 J jnl
Scan Integrity Tests for EDT Compression.
IEEE Des. Test
Wu-Tung Cheng, Grzegorz Mrugalski, Janusz Rajski, Maciej Trawka, Jerzy Tyszer
2019 B conf
A supervised machine learning application in volume diagnosis.
ETS
Yue Tian, Gaurav Veda, Wu-Tung Cheng, Manish Sharma, Huaxing Tang, Neerja Bawaskar, Sudhakar M. Reddy
2019 — conf
Deep Learning Based Test Compression Analyzer.
ATS
Cheng-Hung Wu, Yu Huang, Kuen-Jong Lee, Wu-Tung Cheng, Gaurav Veda, Sudhakar M. Reddy, Chun-Cheng Hu, Chong-Siao Ye
2019 — conf
Improving scan chain diagnostic accuracy using multi-stage artificial neural networks.
ASP-DAC
Mason Chern, Shih-Wei Lee, Shi-Yu Huang, Yu Huang, Gaurav Veda, Kun-Han Hans Tsai, Wu-Tung Cheng
2019 Misc conf
On Cyclic Scan Integrity Tests for EDT-based Compression.
VTS
Wu-Tung Cheng, Grzegorz Mrugalski, Janusz Rajski, Maciej Trawka, Jerzy Tyszer
2019 — conf
Reversible Scan Based Diagnostic Patterns.
VLSI-DAT
Yu Huang, Szczepan Urban, Wu-Tung Cheng, Manish Sharma, Fengju Niu, Junna Zhong, Wen-Lung Hsu
2019 — conf
TEA: A Test Generation Algorithm for Designs with Timing Exceptions.
ATS
Naixing Wang, Chen Wang, Kun-Han Tsai, Wu-Tung Cheng, Xijiang Lin, Mark Kassab, Irith Pomeranz
2018 J jnl
Circuit and Methodology for Testing Small Delay Faults in the Clock Network.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Shaofu Yang, Zhi-Yuan Wen, Shi-Yu Huang, Kun-Han Tsai, Wu-Tung Cheng
2017 — conf
Automatic Identification of Yield Limiting Layout Patterns Using Root Cause Deconvolution on Volume Scan Diagnosis Data.
ATS
Wu-Tung Cheng, Randy Klingenberg, Brady Benware, Wu Yang, Manish Sharma, Geir Eide, Yue Tian, Sudhakar M. Reddy, Yan Pan, Sherwin Fernandes, Atul Chittora
2017 — conf
On designing two-dimensional scan architecture for test chips.
VLSI-DAT
Yu Huang, Wu-Tung Cheng
2017 — conf
Scan Chain Diagnosis Based on Unsupervised Machine Learning.
ATS
Yu Huang, Brady Benware, Randy Klingenberg, Huaxing Tang, Jayant Dsouza, Wu-Tung Cheng
2017 B conf
Volume diagnosis data mining.
ETS
Wu-Tung Cheng, Yue Tian, Sudhakar M. Reddy
2016 — conf
A wide-range clock signal generation scheme for speed grading of a logic core.
HPCS
Shi-Yu Huang, Tzu-Heng Huang, Kun-Han Tsai, Wu-Tung Cheng
2016 J jnl
Delay Characterization and Testing of Arbitrary Multiple-Pin Interconnects.
IEEE Des. Test
Shi-Yu Huang, Meng-Ting Tsai, Kun-Han Tsai, Wu-Tung Cheng
2016 — conf
On Achieving Maximal Chain Diagnosis Resolution through Test Pattern Selection.
ATS
Xijiang Lin, Sudhakar M. Reddy, Wu-Tung Cheng
2016 A conf
Online slack-time binning for IO-registered die-to-die interconnects.
ITC
Chih-Chieh Zheng, Shi-Yu Huang, Shyue-Kung Lu, Ting-Chi Wang, Kun-Han Tsai, Wu-Tung Cheng
2016 B conf
Testing of small delay faults in a clock network.
ETS
Shaofu Yang, Shi-Yu Huang, Kun-Han Tsai, Wu-Tung Cheng
2016 J jnl
Versatile Transition-Time Monitoring for Interconnects via Distributed TDC.
IEEE Des. Test
Shi-Yu Huang, Chih-Chieh Cheng, Meng-Ting Tsai, Kuan-Chen Huang, Kun-Han Tsai, Wu-Tung Cheng
2015 — conf
A test-application-count based learning technique for test time reduction.
VLSI-DAT
Guo-Yu Lin, Kun-Han Tsai, Jiun-Lang Huang, Wu-Tung Cheng
2015 B conf
Advancements in diagnosis driven yield analysis (DDYA): A survey of state-of-the-art scan diagnosis and yield analysis technologies.
ETS
Yu Huang, Wu Yang, Wu-Tung Cheng
2015 — conf
Diagnosing timing related cell internal defects for FinFET technology.
VLSI-DAT
Huaxing Tang, Ting-Pu Tai, Wu-Tung Cheng, Brady Benware, Friedrich Hapke
2015 J jnl
Diagnosis and Layout Aware (DLA) Scan Chain Stitching.
IEEE Trans. Very Large Scale Integr. Syst.
Jing Ye, Yu Huang, Yu Hu, Wu-Tung Cheng, Ruifeng Guo, Liyang Lai, Ting-Pu Tai, Xiaowei Li, Wei-pin Changchien, Daw-Ming Lee, Ji-Jan Chen, Sandeep C. Eruvathi, Kartik K. Kumara, Charles C. C. Liu, Sam Pan
2015 Misc conf
Embedded Tutorial ET2: Volume Diagnosis for Yield Improvement.
VLSID
Wu-Tung Cheng, Sudhakar M. Reddy
2015 A conf
Feedback-bus oscillation ring: a general architecture for delay characterization and test of interconnects.
DATE
Shi-Yu Huang, Meng-Ting Tsai, Kun-Han Hans Tsai, Wu-Tung Cheng
2015 J jnl
General Timing-Aware Built-In Self-Repair for Die-to-Die Interconnects.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Shi-Yu Huang, Meng-Ting Tsai, Zeng-Fu Zeng, Kun-Han Hans Tsai, Wu-Tung Cheng
2015 — conf
Identify problematic layout patterns through volume diagnosis.
VLSI-DAT
Wu-Tung Cheng
2015 A conf
Monitoring the delay of long interconnects via distributed TDC.
ITC
Meng-Ting Tsai, Shi-Yu Huang, Kun-Han Tsai, Wu-Tung Cheng
2015 J jnl
Nonintrusive On-Line Transition-Time Binning and Timing Failure Threat Detection for Die-to-Die Interconnects.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Shi-Yu Huang, Meng-Ting Tsai, Hua-Xuan Li, Zeng-Fu Zeng, Kun-Han Hans Tsai, Wu-Tung Cheng
2015 — conf
On Improving Transition Test Set Quality to Detect CMOS Transistor Stuck-Open Faults.
ATS
Xijiang Lin, Wu-Tung Cheng, Janusz Rajski
2015 J jnl
Scan Test Bandwidth Management for Ultralarge-Scale System-on-Chip Architectures.
IEEE Trans. Very Large Scale Integr. Syst.
Wu-Tung Cheng, Yan Dong, Grady Giles, Yu Huang, Jakub Janicki, Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer
2014 J jnl
Diagnose Failures Caused by Multiple Locations at a Time.
IEEE Trans. Very Large Scale Integr. Syst.
Jing Ye, Yu Hu, Xiaowei Li, Wu-Tung Cheng, Yu Huang, Huaxing Tang
2014 — conf
Diagnosing Cell Internal Defects Using Analog Simulation-Based Fault Models.
ATS
Huaxing Tang, Brady Benware, Michael Reese, Joseph Caroselli, Thomas Herrmann, Friedrich Hapke, Robert Tao, Wu-Tung Cheng, Manish Sharma
2014 — conf
On-Line Transition-Time Monitoring for Die-to-Die Interconnects in 3D ICs.
ATS
Shi-Yu Huang, Hua-Xuan Li, Zeng-Fu Zeng, Kun-Han Tsai, Wu-Tung Cheng
2014 B conf
On-the-fly timing-aware built-in self-repair for high-speed interposer wires in 2.5-D ICs.
ETS
Shi-Yu Huang, Zeng-Fu Zeng, Kun-Han Tsai, Wu-Tung Cheng
2014 J jnl
Parametric Fault Testing and Performance Characterization of Post-Bond Interposer Wires in 2.5-D ICs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Li-Ren Huang, Shi-Yu Huang, Kun-Han Tsai, Wu-Tung Cheng
2014 J jnl
Pulse-Vanishing Test for Interposers Wires in 2.5-D IC.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Shi-Yu Huang, Jeo-Yen Lee, Kun-Han Tsai, Wu-Tung Cheng
2014 — conf
Test Compression Improvement with EDT Channel Sharing in SoC Designs.
NATW
Yu Huang, Mark Kassab, Jay Jahangiri, Janusz Rajski, Wu-Tung Cheng, Dongkwan Han, Jihye Kim, Kun Young Chung
2013 C conf
At-speed BIST for interposer wires supporting on-the-spot diagnosis.
IOLTS
Shi-Yu Huang, Jeo-Yen Lee, Kun-Han Tsai, Wu-Tung Cheng
2013 A conf
Delay testing and characterization of post-bond interposer wires in 2.5-D ICs.
ITC
Shi-Yu Huang, Li-Ren Huang, Kun-Han Tsai, Wu-Tung Cheng
2013 A conf
Diagnosis and Layout Aware (DLA) scan chain stitching.
ITC
Jing Ye, Yu Huang, Yu Hu, Wu-Tung Cheng, Ruifeng Guo, Liyang Lai, Ting-Pu Tai, Xiaowei Li, Wei-pin Changchien, Daw-Ming Lee, Ji-Jan Chen, Sandeep C. Eruvathi, Kartik K. Kumara, Charles C. C. Liu, Sam Pan
2013 Misc conf
Distributed dynamic partitioning based diagnosis of scan chain.
VTS
Yu Huang, Xiaoxin Fan, Huaxing Tang, Manish Sharma, Wu-Tung Cheng, Brady Benware, Sudhakar M. Reddy
2013 A conf
EDT bandwidth management - Practical scenarios for large SoC designs.
ITC
Jakub Janicki, Jerzy Tyszer, Wu-Tung Cheng, Yu Huang, Mark Kassab, Nilanjan Mukherjee, Janusz Rajski, Yan Dong, Grady Giles
2013 — conf
Improve speed path identification with suspect path expressions.
VLSI-DAT
Jiun-Lang Huang, Kun-Han Tsai, Yu-Ping Liu, Ruifeng Guo, Manish Sharma, Wu-Tung Cheng
2013 — conf
Mid-bond Interposer Wire Test.
Asian Test Symposium
Li-Ren Huang, Shi-Yu Huang, Kun-Han Tsai, Wu-Tung Cheng, Stephen K. Sunter
2013 J jnl
Oscillation-Based Prebond TSV Test.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Li-Ren Huang, Shi-Yu Huang, Stephen K. Sunter, Kun-Han Tsai, Wu-Tung Cheng
2013 J jnl
Parametric Delay Test of Post-Bond Through-Silicon Vias in 3-D ICs via Variable Output Thresholding Analysis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yu-Hsiang Lin, Shi-Yu Huang, Kun-Han Tsai, Wu-Tung Cheng, Stephen K. Sunter, Yung-Fa Chou, Ding-Ming Kwai
2013 J jnl
Programmable Leakage Test and Binning for TSVs With Self-Timed Timing Control.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Shi-Yu Huang, Yu-Hsiang Lin, Li-Ren Huang, Kun-Han Tsai, Wu-Tung Cheng
2012 — conf
A Hybrid Flow for Memory Failure Bitmap Classification.
Asian Test Symposium
Jianbo Li, Yu Huang, Wu-Tung Cheng, Chris Schuermyer, Dong Xiang, Eric Faehn, Ruth Farrugia
2012 A conf
A unified method for parametric fault characterization of post-bond TSVs.
ITC
Yu-Hsiang Lin, Shi-Yu Huang, Kun-Han Tsai, Wu-Tung Cheng, Stephen K. Sunter
2012 — conf
Diagnosis of Cell Internal Defects with Multi-cycle Test Patterns.
Asian Test Symposium
Xiaoxin Fan, Manish Sharma, Wu-Tung Cheng, Sudhakar M. Reddy
2012 — conf
Embedded Tutorial Summary: Diagnosis for Accelerating Yield and Failure Analysis.
Asian Test Symposium
Wu-Tung Cheng, Feng-Ming Kuo
2012 A conf
Improved volume diagnosis throughput using dynamic design partitioning.
ITC
Xiaoxin Fan, Huaxing Tang, Yu Huang, Wu-Tung Cheng, Sudhakar M. Reddy, Brady Benware
2012 — conf
Programmable Leakage Test and Binning for TSVs.
Asian Test Symposium
Yu-Hsiang Lin, Shi-Yu Huang, Kun-Han Tsai, Wu-Tung Cheng
2012 J jnl
Scan-Based Speed-Path Debug for a Microprocessor.
IEEE Des. Test Comput.
Jing Zeng, Ruifeng Guo, Wu-Tung Cheng, Michael Mateja, Jing Wang
2012 A* conf
Small delay testing for TSVs in 3-D ICs.
DAC
Shi-Yu Huang, Yu-Hsiang Lin, Kun-Han Tsai, Wu-Tung Cheng, Stephen K. Sunter, Yung-Fa Chou, Ding-Ming Kwai
2011 A conf
A novel Test Access Mechanism for failure diagnosis of multiple isolated identical cores.
ITC
Manish Sharma, Avijit Dutta, Wu-Tung Cheng, Brady Benware, Mark Kassab
2011 A conf
Deterministic IDDQ diagnosis using a net activation based model.
ITC
Andras Kun, Ralf Arnold, Peter Heinrich, Gwenolé Maugard, Huaxing Tang, Wu-Tung Cheng
2011 — conf
Diagnosis of Multiple Faults Based on Fault-Tuple Equivalence Tree.
DFT
Xun Tang, Wu-Tung Cheng, Ruifeng Guo, Huaxing Tang, Sudhakar M. Reddy
2011 — conf
On Using Design Partitioning to Reduce Diagnosis Memory Footprint.
Asian Test Symposium
Xiaoxin Fan, Huaxing Tang, Sudhakar M. Reddy, Wu-Tung Cheng, Brady Benware
2010 A conf
A scalable quantitative measure of IR-drop effects for scan pattern generation.
ICCAD
Meng-Fan Wu, Kun-Han Tsai, Wu-Tung Cheng, Hsin-Cheih Pan, Jiun-Lang Huang, Augusli Kifli
2010 A conf
Case study of scan chain diagnosis and PFA on a low yield wafer.
ITC
Yu Huang, Brady Benware, Wu-Tung Cheng, Ting-Pu Tai, Feng-Ming Kuo, Yuan-Shih Chen
2010 — conf
Diagnosis of Multiple Physical Defects Using Logic Fault Models.
Asian Test Symposium
Xun Tang, Wu-Tung Cheng, Ruifeng Guo, Sudhakar M. Reddy
2010 — conf
Emulating and diagnosing IR-drop by using dynamic SDF.
ASP-DAC
Ke Peng, Yu Huang, Ruifeng Guo, Wu-Tung Cheng, Mohammad Tehranipoor
2010 — conf
Enhance Profiling-Based Scan Chain Diagnosis by Pattern Masking.
Asian Test Symposium
Wu-Tung Cheng, Yu Huang
2010 B conf
Full-circuit SPICE simulation based validation of dynamic delay estimation.
ETS
Ke Peng, Yu Huang, Pinki Mallick, Wu-Tung Cheng, Mohammad Tehranipoor
2010 — conf
Improved weight assignment for logic switching activity during at-speed test pattern generation.
ASP-DAC
Meng-Fan Wu, Hsin-Cheih Pan, Teng-Han Wang, Jiun-Lang Huang, Kun-Han Tsai, Wu-Tung Cheng
2010 J jnl
On Reducing Scan Shift Activity at RTL.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Elif Alpaslan, Yu Huang, Xijiang Lin, Wu-Tung Cheng, Jennifer Dworak
2010 B conf
Scan based speed-path debug for a microprocessor.
ETS
Jing Zeng, Ruifeng Guo, Wu-Tung Cheng, Michael Mateja, Jing Wang, Kun-Han Tsai, Ken Amstutz
2010 A conf
Test cycle power optimization for scan-based designs.
ITC
Kun-Han Tsai, Yu Huang, Wu-Tung Cheng, Ting-Pu Tai, Augusli Kifli
2009 — conf
At-Speed Scan Test Method for the Timing Optimization and Calibration.
Asian Test Symposium
Kun-Han Tsai, Ruifeng Guo, Wu-Tung Cheng
2009 A conf
Improving compressed test pattern generation for multiple scan chain failure diagnosis.
DATE
Xun Tang, Ruifeng Guo, Wu-Tung Cheng, Sudhakar M. Reddy
2009 — conf
On Improving Diagnostic Test Generation for Scan Chain Failures.
Asian Test Symposium
Xun Tang, Ruifeng Guo, Wu-Tung Cheng, Sudhakar M. Reddy, Yu Huang
2009 — conf
Scan Chain Diagnosis by Adaptive Signal Profiling with Manufacturing ATPG Patterns.
Asian Test Symposium
Yu Huang, Wu-Tung Cheng, Ruifeng Guo, Ting-Pu Tai, Feng-Ming Kuo, Yuan-Shih Chen
2009 B conf
Speed-Path Debug Using At-Speed Scan Test Patterns.
ETS
Ruifeng Guo, Wu-Tung Cheng, Kun-Han Tsai
2008 — conf
A Robust Automated Scan Pattern Mismatch Debugger.
ATS
Kun-Han Tsai, Ruifeng Guo, Wu-Tung Cheng
2008 Misc conf
Automatic Test Pattern Generation for Interconnect Open Defects.
VTS
Stefan Spinner, Ilia Polian, Piet Engelke, Bernd Becker, Martin Keim, Wu-Tung Cheng
2008 A conf
Detection and Diagnosis of Static Scan Cell Internal Defect.
ITC
Ruifeng Guo, Liyang Lai, Yu Huang, Wu-Tung Cheng
2008 B conf
Diagnose Multiple Stuck-at Scan Chain Faults.
ETS
Yu Huang, Wu-Tung Cheng, Ruifeng Guo
2008 A conf
Efficiently Performing Yield Enhancements by Identifying Dominant Physical Root Cause from Test Fail Data.
ITC
Manish Sharma, Brady Benware, Lei Ling, David Abercrombie, Lincoln Lee, Martin Keim, Huaxing Tang, Wu-Tung Cheng, Ting-Pu Tai, Yi-Jung Chang, Reinhart Lin, Albert Mann
2008 — conf
Enhancing Transition Fault Model for Delay Defect Diagnosis.
ATS
Wu-Tung Cheng, Brady Benware, Ruifeng Guo, Kun-Han Tsai, Takeo Kobayashi, Kazuyuki Maruo, Michinobu Nakao, Yoshiaki Fukui, Hideyuki Otake
2008 A conf
Extraction, Simulation and Test Generation for Interconnect Open Defects Based on Enhanced Aggressor-Victim Model.
ITC
Stefan Hillebrecht, Ilia Polian, Piet Engelke, Bernd Becker, Martin Keim, Wu-Tung Cheng
2008 — conf
Hyperactive Faults Dictionary to Increase Diagnosis Throughput.
ATS
Chen Liu, Wu-Tung Cheng, Huaxing Tang, Sudhakar M. Reddy, Wei Zou, Manish Sharma
2008 Misc conf
Reducing Scan Shift Power at RTL.
VTS
Elif Alpaslan, Yu Huang, Xijiang Lin, Wu-Tung Cheng, Jennifer Dworak
2008 J jnl
Survey of Scan Chain Diagnosis.
IEEE Des. Test Comput.
Yu Huang, Ruifeng Guo, Wu-Tung Cheng, James Chien-Mo Li
2008 J jnl
X-Press: Two-Stage X-Tolerant Compactor With Programmable Selector.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Janusz Rajski, Jerzy Tyszer, Grzegorz Mrugalski, Wu-Tung Cheng, Nilanjan Mukherjee, Mark Kassab
2007 — conf
A RTL Testability Analyzer Based on Logical Virtual Prototyping.
ATS
Yu Huang, Nilanjan Mukherjee, Wu-Tung Cheng, Greg Aldrich
2007 A conf
A complete test set to diagnose scan chain failures.
ITC
Ruifeng Guo, Yu Huang, Wu-Tung Cheng
2007 A conf
Diagnose compound scan chain and system logic defects.
ITC
Yu Huang, Wu-Tung Cheng, Ruifeng Guo, Will Hsu, Yuan-Shih Chen, Albert Mann
2007 A conf
Faster defect localization in nanometer technology based on defective cell diagnosis.
ITC
Manish Sharma, Wu-Tung Cheng, Ting-Pu Tai, Y. S. Cheng, Will Hsu, Chen Liu, Sudhakar M. Reddy, Albert Mann
2007 — conf
Fault Dictionary Based Scan Chain Failure Diagnosis.
ATS
Ruifeng Guo, Yu Huang, Wu-Tung Cheng
2007 — conf
Improving Performance of Effect-Cause Diagnosis with Minimal Memory Overhead.
ATS
Huaxing Tang, Chen Liu, Wu-Tung Cheng, Sudahkar M. Reddy, Wei Zou
2007 A conf
Interconnect open defect diagnosis with minimal physical information.
ITC
Chen Liu, Wei Zou, Sudhakar M. Reddy, Wu-Tung Cheng, Manish Sharma, Huaxing Tang
2007 — conf
Programmable Scan-Based Logic Built-In Self Test.
ATS
Liyang Lai, Wu-Tung Cheng, Thomas Rinderknecht
2007 — conf
Scan Diagnosis and Its Successful Industrial Applications.
ATS
Wu Yang, Wu-Tung Cheng, Yu Huang, Martin Keim, Randy Klingenberg
2007 Misc conf
Speeding Up Effect-Cause Defect Diagnosis Using a Small Dictionary.
VTS
Wei Zou, Wu-Tung Cheng, Sudhakar M. Reddy, Huaxing Tang
2007 J jnl
X-Tolerant Compactor with On-Chip Registration and Signature-Based Diagnosis.
IEEE Des. Test Comput.
Jerzy Tyszer, Janusz Rajski, Grzegorz Mrugalski, Nilanjan Mukherjee, Mark Kassab, Wu-Tung Cheng, Manish Sharma, Liyang Lai
2006 — conf
A Field Programmable Memory BIST Architecture Supporting Algorithms with Multiple Nested Loops.
ATS
Xiaogang Du, Nilanjan Mukherjee, Chris Hill, Wu-Tung Cheng, Sudhakar M. Reddy
2006 A conf
Diagnosis with Limited Failure Information.
ITC
Yu Huang, Wu-Tung Cheng, Nagesh Tamarapalli, Janusz Rajski, Randy Klingenberg, Will Hsu, Yuan-Shih Chen
2006 A conf
Improving Transition Fault Test Pattern Quality through At-Speed Diagnosis.
ITC
Nandu Tendolkar, Dawit Belete, Bill Schwarz, Bob Podnar, Akshay Gupta, Steve Karako, Wu-Tung Cheng, Alex Babin, Kun-Han Tsai, Nagesh Tamarapalli, Greg Aldrich
2006 — conf
Interconnect Open Defect Diagnosis with Physical Information.
ATS
Wei Zou, Wu-Tung Cheng, Sudhakar M. Reddy
2006 Misc conf
On Methods to Improve Location Based Logic Diagnosis.
VLSI Design
Wei Zou, Wu-Tung Cheng, Sudhakar M. Reddy, Huaxing Tang
2006 A conf
Signature Based Diagnosis for Logic BIST.
ITC
Wu-Tung Cheng, Manish Sharma, Thomas Rinderknecht, Liyang Lai, Chris Hill
2006 — conf
The Next Step in Volume Scan Diagnosis: Standard Fail Data Format.
ATS
Andreas Leininger, Ajay Khoche, Martin Fischer, Nagesh Tamarapalli, Wu-Tung Cheng, Randy Klingenberg, Wu Yang
2006 A conf
X-Press Compactor for 1000x Reduction of Test Data.
ITC
Janusz Rajski, Jerzy Tyszer, Grzegorz Mrugalski, Wu-Tung Cheng, Nilanjan Mukherjee, Mark Kassab
2005 — conf
Achieving High Test Quality with Reduced Pin Count Testing.
Asian Test Symposium
Jay Jahangiri, Nilanjan Mukherjee, Wu-Tung Cheng, Subramanian Mahadevan, Ron Press
2005 — conf
Bridge Defect Diagnosis with Physical Information.
Asian Test Symposium
Wei Zou, Wu-Tung Cheng, Sudhakar M. Reddy
2005 A conf
Compressed pattern diagnosis for scan chain failures.
ITC
Yu Huang, Wu-Tung Cheng, Janusz Rajski
2005 A conf
Compression mode diagnosis enables high volume monitoring diagnosis flow.
ITC
Andreas Leininger, Peter Muhmenthaler, Wu-Tung Cheng, Nagesh Tamarapalli, Wu Yang, Kun-Han Hans Tsai
2005 — conf
Full-speed field programmable memory BIST supporting multi-level looping.
MTDT
Xiaogang Du, Nilanjan Mukherjee, Wu-Tung Cheng, Sudhakar M. Reddy
2005 A conf
Full-speed field-programmable memory BIST architecture.
ITC
Xiaogang Du, Nilanjan Mukherjee, Wu-Tung Cheng, Sudhakar M. Reddy
2005 C conf
Hardware Ef.cient LBISTWith Complementary Weights.
ICCD
Liyang Lai, Janak H. Patel, Thomas Rinderknecht, Wu-Tung Cheng
2005 — conf
Using fault model relaxation to diagnose real scan chain defects.
ASP-DAC
Yu Huang, Wu-Tung Cheng, Greg Crowell
2005 A conf
X-filter: filtering unknowns from compacted test responses.
ITC
Manish Sharma, Wu-Tung Cheng
2004 Misc conf
At-Speed Built-in Self-Repair Analyzer for Embedded Word-Oriented Memories.
VLSI Design
Xiaogang Du, Sudhakar M. Reddy, Wu-Tung Cheng, Joseph Rayhawk, Nilanjan Mukherjee
2004 — conf
Compactor Independent Direct Diagnosis.
Asian Test Symposium
Wu-Tung Cheng, Kun-Han Tsai, Yu Huang, Nagesh Tamarapalli, Janusz Rajski
2004 A conf
Intermittent Scan Chain Fault Diagnosis Based on Signal Probability Analysis.
DATE
Yu Huang, Wu-Tung Cheng, Cheng-Ju Hsieh, Huan-Yung Tseng, Alou Huang, Yu-Ting Hung
2004 Misc conf
Logic BIST Using Constrained Scan Cells.
VTS
Liyang Lai, Thomas Rinderknecht, Wu-Tung Cheng, Janak H. Patel
2004 A conf
Logic BIST with Scan Chain Segmentation.
ITC
Liyang Lai, Janak H. Patel, Thomas Rinderknecht, Wu-Tung Cheng
2004 Misc conf
Memory BIST Using ESP.
VTS
Xiaogang Du, Sudhakar M. Reddy, Don E. Ross, Wu-Tung Cheng, Joseph Rayhawk
2003 A conf
BIST for Deep Submicron ASIC Memories with High Performance Application.
ITC
Theo J. Powell, Wu-Tung Cheng, Joseph Rayhawk, Omer Samman, Paul Policke, Sherry Lai
2003 — conf
Efficient Diagnosis for Multiple Intermittent Scan Chain Hold-Time Faults.
Asian Test Symposium
Yu Huang, Wu-Tung Cheng, Cheng-Ju Hsieh, Huan-Yung Tseng, Alou Huang, Yu-Ting Hung
2003 A conf
Silicon Diagnosis.
ITC
Wu-Tung Cheng
2003 — conf
Static Pin Mapping and SOC Test Scheduling for Cores with Multiple Test Sets.
ISQED
Yu Huang, Wu-Tung Cheng, Chien-Chung Tsai, Nilanjan Mukherjee, Sudhakar M. Reddy
2003 A conf
Statistical Diagnosis for Intermittent Scan Chain Hold-Time Fault.
ITC
Yu Huang, Wu-Tung Cheng, Sudhakar M. Reddy, Cheng-Ju Hsieh, Yu-Ting Hung
2003 — conf
Testing Delay Faults in Embedded CAMs.
Asian Test Symposium
Xiaogang Du, Sudhakar M. Reddy, Joseph Rayhawk, Wu-Tung Cheng
2003 A* conf
Using embedded infrastructure IP for SOC post-silicon verification.
DAC
Yu Huang, Wu-Tung Cheng
2002 — conf
Constraint Driven Pin Mapping for Concurrent SOC Testing.
ASP-DAC/VLSI Design
Yu Huang, Nilanjan Mukherjee, Chien-Chung Tsai, Omer Samman, Yahya Zaidan, Yanping Zhang, Wu-Tung Cheng, Sudhakar M. Reddy
2002 — conf
Core - Clustering Based SOC Test Scheduling Optimization.
Asian Test Symposium
Yu Huang, Sudhakar M. Reddy, Wu-Tung Cheng
2002 J jnl
On Concurrent Test of Core-Based SOC Design.
J. Electron. Test.
Yu Huang, Wu-Tung Cheng, Chien-Chung Tsai, Nilanjan Mukherjee, Omer Samman, Yahya Zaidan, Sudhakar M. Reddy
2002 A conf
Optimal Core Wrapper Width Selection and SOC Test Scheduling Based on 3-D Bin Packing Algorithm.
ITC
Yu Huang, Sudhakar M. Reddy, Wu-Tung Cheng, Paul Reuter, Nilanjan Mukherjee, Chien-Chung Tsai, Omer Samman, Yahya Zaidan
2002 J jnl
Synthesis of Scan Chains for Netlist Descriptions at RT-Level.
J. Electron. Test.
Yu Huang, Chien-Chung Tsai, Nilanjan Mukherjee, Omer Samman, Wu-Tung Cheng, Sudhakar M. Reddy
2001 — conf
Effect of RTL coding style on testability.
CICC
Yu Huang, Chien-Chung Tsai, Nilanjan Mukherhee, Wu-Tung Cheng, Sudhakar M. Reddy
2001 A conf
On RTL scan design.
ITC
Yu Huang, Chien-Chung Tsai, Nilanjan Mukherjee, Omer Samman, Dan Devries, Wu-Tung Cheng, Sudhakar M. Reddy
2001 — conf
Resource Allocation and Test Scheduling for Concurrent Test of Core-Based SoC D.
Asian Test Symposium
Yu Huang, Wu-Tung Cheng, Chien-Chung Tsai, Nilanjan Mukherjee, Omer Samman, Yahya Zaidan, Sudhakar M. Reddy
2000 — conf
Current status and future trend on CAD tools for VLSI testing Wu-Tung Cheng.
Asian Test Symposium
Wu-Tung Cheng
2000 Misc conf
SIFAR: Static Test Compaction for Synchronous Sequential Circuits Based on Single Fault Restoration.
VTS
Xijiang Lin, Wu-Tung Cheng, Irith Pomeranz, Sudhakar M. Reddy
1999 A conf
High time for high level ATPG.
ITC
Wu-Tung Cheng
1996 A conf
A Universal Technique for Accelerating Simulation of Scan Test Patterns.
ITC
Bejoy G. Oomman, Wu-Tung Cheng, John A. Waicukauski
1992 J jnl
Optimal diagnostic methods for wiring interconnects.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Wu-Tung Cheng, James L. Lewandowski, Eleanor Wu
1992 J jnl
PROOFS: a fast, memory-efficient sequential circuit fault simulator.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Thomas M. Niermann, Wu-Tung Cheng, Janak H. Patel
1990 A conf
Diagnosis for wiring interconnects.
ITC
Wu-Tung Cheng, James L. Lewandowski, Eleanor Wu
1990 J jnl
Differential fault simulation for sequential circuits.
J. Electron. Test.
Wu-Tung Cheng, Meng-Lin Yu
1990 — conf
PROOFS: a super fast fault simulator for sequential circuits.
EURO-DAC
Wu-Tung Cheng, Janak H. Patel
1990 A* conf
Proofs: A Fast, Memory Efficient Sequential Circuit Fault Simulator.
DAC
Thomas M. Niermann, Wu-Tung Cheng, Janak H. Patel
1989 A* conf
Differential Fault Simulation - a Fast Method Using Minimal Memory.
DAC
Wu-Tung Cheng, Meng-Lin Yu
1989 J jnl
Gentest: An Automatic Test-Generation System for Sequential Circuits.
Computer
Wu-Tung Cheng, Tapan J. Chakraborty
1988 A* conf
Split Circuit Model for Test Generation.
DAC
Wu-Tung Cheng
1988 C conf
The BACK algorithm for sequential test generation.
ICCD
Wu-Tung Cheng
1987 J jnl
A Minimum Test Set for Multiple Fault Detection in Ripple Carry Adders.
IEEE Trans. Computers
Wu-Tung Cheng, Janak H. Patel
1985 A conf
Multiple-Fault Detection in Iterative Logic Arrays.
ITC
Wu-Tung Cheng, Janak H. Patel
1985 — —
Testing and Error Detection in Iterative Logic Arrays
Wu-Tung Cheng