Wu-Shiung Feng

56 papers A* 3A 1B 1C 5Misc 1Journal 26Unranked 19
YearRankTypeTitle / Venue / Authors
2017 J jnl
A Simple Drain Current Model for MOS Transistors with the Lorentz Force Effect.
Sensors
Hwang-Cherng Chow, Prasenjit Chatterjee, Wu-Shiung Feng
2016 J jnl
Drain Current Modulation of a Single Drain MOSFET by Lorentz Force for Magnetic Sensing Application.
Sensors
Prasenjit Chatterjee, Hwang-Cherng Chow, Wu-Shiung Feng
2008 C conf
A 24GHz low-power CMOS receiver design.
ISCAS
Chen-Yuan Chu, Chien-Cheng Wei, Hui-Chen Hsu, Shu-Hau Feng, Wu-Shiung Feng
2008 J jnl
Model-order reductions for MIMO systems using global Krylov subspace methods.
Math. Comput. Simul.
Chia-Chi Chu, Ming-Hong Lai, Wu-Shiung Feng
2007 C conf
Applications of AOGL Model-Order Reduction Techniques in Interconnect Analysis.
ISCAS
Ming-Hong Lai, Chia-Chi Chu, Wu-Shiung Feng
2007 J jnl
Lyapunov-Based Error Estimations of MIMO Interconnect Reductions by Using the Global Arnoldi Algorithm.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Chia-Chi Chu, Ming-Hong Lai, Wu-Shiung Feng
2007 J jnl
On the Equivalent of Structure Preserving Reductions Approach and Adjoint Networks Approach for VLSI Interconnect Reductions.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Ming-Hong Lai, Chia-Chi Chu, Wu-Shiung Feng
2006 J jnl
A Brief Comparison of Two-phase and NOR-based Four-phase Pipelined Asynchronous Systems.
J. Inf. Sci. Eng.
Ying-Haw Shu, Shing Tenqchen, Ming-Chang Sun, Wu-Shiung Feng
2006 J jnl
An Adjoint Network Approach for RLCG Interconnect Model Order Reductions.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Chia-Chi Chu, Herng-Jer Lee, Ming-Hong Lai, Wu-Shiung Feng
2006 J jnl
MIMO Interconnects Order Reductions by Using the Multiple Point Adaptive-Order Rational Global Arnoldi Algorithm.
IEICE Trans. Electron.
Chia-Chi Chu, Ming-Hong Lai, Wu-Shiung Feng
2006 C conf
MIMO interconnects order reductions by using the global Arnoldi algorithm.
ISCAS
Ming-Hong Lai, Chia-Chi Chu, Wu-Shiung Feng
2006 — conf
Model-Order Reduction Algorithm with Structure Preserving Techniques.
APCCAS
Ming-Hong Lai, Chia-Chi Chu, Wu-Shiung Feng
2006 — conf
The Multiple Point Global Lanczos Method for MIMO Interconnect Model-Order Reductions.
APCCAS
Ming-Hong Lai, Chia-Chi Chu, Wu-Shiung Feng
2006 J jnl
The Multiple Point Global Lanczos Method for Multiple-Inputs Multiple-Outputs Interconnect Order Reductions.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Chia-Chi Chu, Ming-Hong Lai, Wu-Shiung Feng
2006 C conf
The global Lanczos method for MIMO interconnect order reductions.
ISCAS
Chia-Chi Chu, Ming-Hong Lai, Wu-Shiung Feng
2006 J jnl
XNOR-based double-edge-triggered flip-flop for two-phase pipelines.
IEEE Trans. Circuits Syst. II Express Briefs
Ying-Haw Shu, Shing Tenqchen, Ming-Chang Sun, Wu-Shiung Feng
2005 — conf
A 1.8 V, 0.3 mW, 10-bit SA-ADC with new self-timed timing control for biomedical applications.
ISCAS (1)
Hwang-Cherng Chow, Bo-Wei Chen, Hsiao-Chen Chen, Wu-Shiung Feng
2005 J jnl
A One-Step Input Matching Method for Cascode CMOS Low-Noise Amplifiers.
IEICE Trans. Electron.
Ming-Chang Sun, Ying-Haw Shu, Shing Tenqchen, Wu-Shiung Feng
2005 J jnl
Error Estimations of Arnoldi-Based Interconnect Model-Order Reductions.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Chia-Chi Chu, Herng-Jer Lee, Wu-Shiung Feng
2005 — conf
Interconnect model reductions by using the AORA algorithm with considering the adjoint network.
ISCAS (2)
Chia-Chi Chu, Herng-Jer Lee, Wu-Shiung Feng, Ming-Hong Lai
2005 J jnl
Moment Computations of Distributed Coupled RLC Interconnects with Applications to Estimating Crosstalk Noise.
IEICE Trans. Electron.
Herng-Jer Lee, Chia-Chi Chu, Ming-Hong Lai, Wu-Shiung Feng
2005 J jnl
Perturbation Approach for Order Selections of Two-Sided Oblique Projection-Based Interconnect Reductions.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Chia-Chi Chu, Ming-Hong Lai, Wu-Shiung Feng
2004 — conf
An XNOR-based Double-edge-triggered Flip-Flop for Two-phase Pipelines.
CCCT (1)
Ying-Haw Shu, Shing Tenqchen, Ming-Chang Sun, Wu-Shiung Feng
2004 — conf
Applications of tree/link partitioning for moment computations of general lumped RLC networks with resistor loops.
ISCAS (1)
Herng-Jer Lee, Ming-Hong Lai, Chia-Chi Chu, Wu-Shiung Feng
2004 — conf
Blind Signal Extraction Algorithm for the License Plate Matching of Vehicle Positioning System.
DELTA
Shing Tenqchen, Ying-Haw Shu, Ming-Chang Sun, Wu-Shiung Feng
2004 — conf
Generalizations of adjoint networks technique for RLC interconnects model-order reductions.
ISCAS (1)
Herng-Jer Lee, Chia-Chi Chu, Wu-Shiung Feng
2004 — conf
Moment Computations of Nonuniform Distributed Coupled RLC Trees with Applications to Estimating Crosstalk Noise.
ISQED
Herng-Jer Lee, Chia-Chi Chu, Wu-Shiung Feng
2003 — conf
A 2.4 GHz CMOS image-reject low noise amplifier.
ISCAS (1)
Ming-Chang Sun, Shing Tenqchen, Ying-Haw Shu, Wu-Shiung Feng
2003 — conf
Interconnect modeling and sensitivity analysis using adjoint networks reduction technique.
ISCAS (4)
Herng-Jer Lee, Chia-Chi Chu, Wu-Shiung Feng
2003 J jnl
Moment Computations of Lumped Coupled RLC Trees with Applications to Estimating Crosstalk Noise.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Herng-Jer Lee, Chia-Chi Chu, Wu-Shiung Feng
2002 — conf
Crosstalk estimation in high-speed VLSI interconnect using coupled RLC-tree models.
APCCAS (1)
Herng-Jer Lee, Chia-Chi Chu, Wu-Shiung Feng
2002 — conf
Intelligent multipoint Arnoldi (IMA) approximations of FIR filters by low-order linear-phase IIR filters.
ISCAS (1)
Herng-Jer Lee, Chia-Chi Chu, Wu-Shiung Feng
2002 — conf
On-board effective inductance measurement.
APCCAS (1)
Chin Hsia, Ming-Hong Lai, Wu-Shiung Feng
2002 — conf
Pipelining Extended Givens Rotation RLS Adaptive Filters.
DELTA
Shing Tenqchen, Ji-Horn Chang, Wu-Shiung Feng, Bor-Sheng Jeng
2001 — conf
A 2.4-GHz CMOS down-conversion doubly balanced mixer with low supply voltage.
ISCAS (4)
Chih-Chun Tang, Wen-Shih Lu, Lan-Da Van, Wu-Shiung Feng
2000 C conf
A new VLSI architecture without global broadcast for 2-D digital filters.
ISCAS
Lan-Da Van, Chih-Chun Tang, Shing Tenqchen, Wu-Shiung Feng
2000 J jnl
Testable design of multiple-stage OTA-C filters.
IEEE Trans. Instrum. Meas.
Cheng-Chung Hsu, Wu-Shiung Feng
1999 Misc conf
A tree-systolic array of DLMS adaptive filter.
ICASSP
Lan-Da Van, Shing Tenqchen, Chia-Hsun Chang, Wu-Shiung Feng
1999 — conf
Design of a lower-error fixed-width multiplier for speech processing application.
ISCAS (3)
Lan-Da Van, Shuenn-Shyang Wang, Shing Tenqchen, Wu-Shiung Feng, Bor-Shenn Jeng
1995 J jnl
Relaxation-based transient sensitivity computations for MOSFET circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Chun-Jung Chen, Wu-Shiung Feng
1994 — conf
An Accurate Time-Domain Current Waveform Simulator for VLSI Circuits.
EDAC-ETC-EUROASIC
Jyh-Herng Wang, Jen-Teng Fan, Wu-Shiung Feng
1994 J jnl
New efficient designs for XOR and XNOR functions on the transistor level.
IEEE J. Solid State Circuits
Jyh-Ming Wang, Sung-Chuan Fang, Wu-Shiung Feng
1994 A* conf
Transient Sensitivity Computation of MOSFET Circuits Using Iterated Timing Analysis and Selective-Tracing Waveform Eelaxation.
DAC
Chung-Jung Chen, Wu-Shiung Feng
1992 A* conf
A New Efficient Approach to Multilayer Channel Routing Problem.
DAC
Sung-Chuan Fang, Wu-Shiung Feng, Shian-Lang Lee
1992 J jnl
An H-V alternating router.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Chia-Chun Tsai, Sao-Jie Chen, Wu-Shiung Feng
1992 J jnl
An analytical CMOS inverter delay model including channel-length modulations.
IEEE J. Solid State Circuits
Hwang-Cherng Chow, Wu-Shiung Feng
1992 J jnl
An improved analytical short-channel MOSFET model valid in all regions of operating for analog/digital circuit simulation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Hwang-Cherng Chow, Wu-Shiung Feng, James B. Kuo
1991 J jnl
A knowledge-based program for compacting mask layout of integrated circuits.
Comput. Aided Des.
Pei-Yung Hsiao, S. F. Steven Chen, Chia-Chun Tsai, Wu-Shiung Feng
1991 A* conf
Constrained via Minimization with Practical Considerations for Multi-Layer VLSI/PCB Routing Problems.
DAC
Sung-Chuan Fang, Kuo-En Chang, Wu-Shiung Feng, Sao-Jie Chen
1991 A conf
Transient Sensitivity Computation for Waveform Relaxation Based Timing Simulation.
ICCAD
Chun-Jung Chen, Jyuo-Min Shyu, Wu-Shiung Feng
1990 J jnl
A new control strategy for an artificial intelligence approach to VLSI layout compaction.
Integr.
Pei-Yung Hsiao, H. F. Steven Chen, Wu-Shiung Feng
1990 J jnl
An
J. Inf. Sci. Eng.
Chia-Chun Tsai, Sao-Jie Chen, Wu-Shiung Feng
1990 J jnl
Generalized terminal connectivity problem for multilayer layout scheme.
Comput. Aided Des.
Chia-Chun Tsai, Sao-Jie Chen, Wu-Shiung Feng
1990 J jnl
Using a multiple storage quad tree on a hierarchical VLSI compaction scheme.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Pei-Yung Hsiao, Wu-Shiung Feng
1989 — conf
The Control Model for a Knowledge-Based Approach to VLSI Compaction Design.
IFIP Congress
S. F. Steven Chen, Pei-Yung Hsiao, Wu-Shiung Feng, Shun-Nan Dai, Wen-Zyh Wang
1988 B conf
A rule-based compactor for VLSI/CAD mask layout.
COMPSAC
Pei-Yung Hsiao, Chen Yung Syau, Wu-Shiung Feng, T. M. Parng, Cheng-Chung Hsu