Woosong Jung

12 papers C 1Journal 6Unranked 5
YearRankTypeTitle / Venue / Authors
2023 J jnl
A 0.99-pJ/b 10-Gb/s Receiver With Fast Recovery From Sleep Mode Under Voltage Drift.
IEEE Trans. Circuits Syst. II Express Briefs
Kwang-Hoon Lee, Jung-Hun Park, Yongjae Lee, Yeonggeun Song, Seungha Roh, Minkyo Shim, Yoonho Song, Woosong Jung, Young-Ha Hwang, Jonghyun Oh, Woo-Seok Choi, Deog-Kyoon Jeong
2023 — conf
A 0.991JS FFT-Based Fast-Locking, 0.82GHz-to-4.lGHz DPLL-Based lnput-Jitter-Filtering Clock Driver with Wide-Range Mode-Switching 8-Shaped LC Oscillator for DRAM Interfaces.
CICC
Woosong Jung, Hyojun Kim, Yeonggeun Song, Kwang-Hoon Lee, Deog-Kyoon Jeong
2023 C conf
A 14-28 Gb/s Reference-less Baud-rate CDR with Integrator-based Stochastic Phase and Frequency Detector.
ISCAS
Woosong Jung, Minkyo Shim, Seungha Roh, Deog-Kyoon Jeong
2023 J jnl
A 48 Gb/s PAM-4 Receiver With Pre-Cursor Adjustable Baud-Rate Phase Detector in 40 nm CMOS.
IEEE J. Solid State Circuits
Woosong Jung, Kwangho Lee, Kwanseo Park, Haram Ju, Jinhyung Lee, Deog-Kyoon Jeong
2022 — conf
A 100MHz-Reference, 8GHz/16GHz, 177fsrms/223fsrms RO-Based IL-ADPLL Incorporating Reference Octupler with Probability-Based Fast Phase-Error Calibration.
ISSCC
Hyojun Kim, Hyeong-Seok Oh, Woosong Jung, Yoonho Song, Jonghyun Oh, Deog-Kyoon Jeong
2022 J jnl
A 32-Gb/s PAM4-Binary Bridge With Sampler Offset Cancellation for Memory Testing.
IEEE Trans. Circuits Syst. II Express Briefs
Daeho Yun, Eonhui Lee, Woosong Jung, Kahyun Kim, Kyung-Min Beak, Jihee Kim, Hyun Bae Lee, Byeongseon Ko, Woo-Seok Choi, Deog-Kyoon Jeong
2022 J jnl
A Low-Jitter 8-GHz RO-Based ADPLL With PVT-Robust Replica-Based Analog Closed Loop for Supply Noise Compensation.
IEEE J. Solid State Circuits
Hyojun Kim, Woosong Jung, Kwandong Kim, Sungwoo Kim, Woo-Seok Choi, Deog-Kyoon Jeong
2022 J jnl
Design Techniques for 48-Gb/s 2.4-pJ/b PAM-4 Baud-Rate CDR With Stochastic Phase Detector.
IEEE J. Solid State Circuits
Haram Ju, Kwangho Lee, Kwanseo Park, Woosong Jung, Deog-Kyoon Jeong
2021 — conf
A 48 Gb/s PAM4 receiver with Baud-rate phase-detector for multi-level signal modulation in 40 nm CMOS.
A-SSCC
Kwangho Lee, Woosong Jung, Haram Ju, Jinhyung Lee, Deog-Kyoon Jeong
2021 — conf
A 48Gb/s 2.4pJ/b PAM-4 Baud-Rate Digital CDR with Stochastic Phase Detection Technique in 40nm CMOS.
A-SSCC
Haram Ju, Kwangho Lee, Woosong Jung, Deog-Kyoon Jeong
2021 J jnl
An Adaptive Offset Cancellation Scheme and Shared-Summer Adaptive DFE for 0.068 pJ/b/dB 1.62-to-10 Gb/s Low-Power Receiver in 40 nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs
Kwangho Lee, Hyojun Kim, Woosong Jung, Jinhyung Lee, Haram Ju, Kwanseo Park, Ook Kim, Deog-Kyoon Jeong
2020 — conf
A 8.4Gb/s Low Power Transmitter with 1.66 pJ/b using 40: 1 Serializer for DisplayPort Interface.
ISOCC
Woosong Jung, Jinhyung Lee, Kwangho Lee, Hyojun Kim, Deog-Kyoon Jeong