Woo-Seok Choi - RankMe

77 papers A* 1A 3C 3Journal 34Unranked 35

Year	Rank	Type	Title / Venue / Authors
2026	—	`conf`	8.8 A 0.292pJ/b 56Gb/s/wire Capacitively Driven Simultaneous Bidirectional Transceiver with PVT/Mismatch Tracking for XSR and D2D Interfaces in 28nm CMOS. ISSCC Kahyun Kim, Yoona Lee, Dae-Hoon Na, Ha-Jung Park, Jeongeun Song, Woo-Seok Choi
2026	J	`jnl`	A 42-Gb/s Noise-Tolerant Single-Ended Clock-Referenced PAM3 Transceiver for Chiplet Interfaces. IEEE J. Solid State Circuits Kahyun Kim, Dae-Hoon Na, Jeongeun Song, Ha-Jung Park, Jin-Seok Heo, Hyunjun Park, Jihee Kim, Hanseok Kim, Hyeri Roh, Jung-Hun Park, Woo-Seok Choi
2026	J	`jnl`	A 48-Gb/s PAM-4 Transceiver With Transition Boosting and RLM Calibration for Next-Generation Memory Interface Testing. IEEE Trans. Very Large Scale Integr. Syst. Chan-Ho Kye, Daeho Yun, Jeonghyeon Han, Minsu Park, Kahyun Kim, Kyungmin Baek, Eonhui Lee, Woo-Seok Choi, Deog-Kyoon Jeong, Jooyeol Rhee
2026	J	`jnl`	A Single-Ended MTA PAM-4 Receiver With Analog-Front-End Nonlinearity Compensation Using MTA-Error Correction Scheme for Memory Interfaces. IEEE Access Sanghyuk Seo, Jusung Lee, Jaeyoon Kim, Younghwan Chang, Jaekwang Yun, Yong-Un Jeong, Woo-Seok Choi
2025	—	`conf`	22.1 A 0.275pJ/b 42Gb/s/pin Clock-Referenced PAM3 Transceiver Tolerant to Supply Noise, Reference Offset and Crosstalk for Chiplets and Short-Reach Memory Interfaces. ISSCC Kahyun Kim, Jung-Hun Park, Ha-Jung Park, Jia Park, Jihee Kim, Woo-Seok Choi
2025	—	`conf`	22.3 A 42Gb/s Single-Ended Hybrid-DFE PAM-3 Receiver for GDDR7 Memory Interfaces. ISSCC Boram Kim, Hankyu Chi, Hyeongjun Ko, Sang-Yeon Byeon, Sungkwon Lee, Changhyun Pyo, Seulgi Kim, Byungjun Kang, Eunji Song, Kwangjin Na, Jin-Youp Cha, Hyesoo Kim, Shinyoung Park, Woo-Seok Choi, Kyunghoon Kim, Hae-Kang Jung, Joohwan Cho, Jonghwan Kim
2025	J	`jnl`	A 0.65-pJ/bit 3.6-TB/s/mm I/O Interface With XTalk Minimizing Affine Signaling for Next-Generation HBM With High Interconnect Density. IEEE Trans. Circuits Syst. I Regul. Pap. Hyunjun Park, Jiwon Shin, Hanseok Kim, Jihee Kim, Haengbeom Shin, Taehoon Kim, Hyeri Roh, Jung-Hun Park, Woo-Seok Choi
2025	J	`jnl`	A 2.5-48 Gb/s 16.6 ns Turn-On Time NRZ/PAM4 Pulse-Based Rapid-On/Off Baud-Rate CDR for Mobile Interfaces. IEEE Trans. Circuits Syst. II Express Briefs Jihee Kim, Yunhee Lee, Hyun-Seok Choi, Yoona Lee, Sanghee Lee, Woo-Seok Choi
2025	—	`conf`	A 3ns Idle-Exit Latency 0.28-28Gb/s/pin Single-Ended NRZ Die-to-Die Interface with Energy-Efficient Receiver and Background Noise Compensation. CICC Hyun-Seok Choi, Sunki Cho, Sanghee Lee, Hyeri Roh, Jeongeun Song, Honggyoo Ahn, Jihee Kim, Minchang Kim, Hankyu Chi, Deog-Kyoon Jeong, Woo-Seok Choi
2025	J	`jnl`	A 4 × 32 Gb/s 1.8 pJ/bit Collaborative Baud-Rate CDR With Background Eye-Climbing Algorithm and Low-Power Global Clock Distribution. IEEE J. Solid State Circuits Jihee Kim, Jia Park, Jiwon Shin, Hanseok Kim, Kahyun Kim, Haengbeom Shin, Ha-Jung Park, Woo-Seok Choi
2025	J	`jnl`	DTH-FusionNet: A Feature-Level Fusion Network Integrating Density, Thickness, and Hair Image for Alopecia Severity Classification. IEEE Access Heon Jun Shin, Woo-Seok Choi, Sang-Hyun Choi
2025	—	`conf`	DVSMOT: Dual View Sharing for Enhanced Multi-Object Tracking and ID Switch Reduction. BigComp Heon Jun Shin, Joohyung Oh, Woo-Seok Choi, Joong Hun Cho, Yeonseok Lee, Tae-Kyung Kim
2025	J	`jnl`	Implementing FFE-MLSD With Improved BER and Reduced Complexity for Long-Reach PAM4 Wireline Receivers. IEEE Access Hanseok Kim, Sihyun Lee, Piljun Jeong, Jaeha Kim, Woo-Seok Choi
2025	A	`conf`	ML-Based Fast and Accurate Performance Modeling and Prediction for High-Speed Memory Interfaces Across Different Technologies. DATE Taehoon Kim, Minjeong Kim, Hankyu Chi, Byungjun Kang, Eunji Song, Woo-Seok Choi
2024	—	`conf`	Constructing Hardware Accelerators for Number-Theoretic Transform Using High-Level Synthesis. ISOCC Hyeri Roh, Woo-Seok Choi
2024	—	`conf`	Device Parameter Extraction Method for Training Performance Predicting Models. ISOCC Minjeong Kim, Taehoon Kim, Woo-Seok Choi
2024	A	`conf`	Hyena: Optimizing Homomorphically Encrypted Convolution for Private CNN Inference. ICCAD Hyeri Roh, Woo-Seok Choi
2024	—	`conf`	JBNU at TREC 2024 Product Search Track. TREC Gi-taek An, Seong-Hyuk Yim, Jun-Yong Park, Woo-Seok Choi, Kyung-Soon Lee
2023	J	`jnl`	A 0.99-pJ/b 10-Gb/s Receiver With Fast Recovery From Sleep Mode Under Voltage Drift. IEEE Trans. Circuits Syst. II Express Briefs Kwang-Hoon Lee, Jung-Hun Park, Yongjae Lee, Yeonggeun Song, Seungha Roh, Minkyo Shim, Yoonho Song, Woosong Jung, Young-Ha Hwang, Jonghyun Oh, Woo-Seok Choi, Deog-Kyoon Jeong
2023	C	`conf`	A 48-Gb/s Single-Ended PAM-4 Receiver with Adaptive Nonlinearity Compensation. ISCAS Kahyun Kim, Daeho Yun, Kyungmin Baek, Woo-Seok Choi, Deog-Kyoon Jeong
2023	—	`conf`	A Baud-Rate Clock and Data Recovery With Collaborative Maximum-Eye Tracking Method. ISOCC Jihee Kim, Woo-Seok Choi
2023	J	`jnl`	A Context-Aware Readout System for Sparse Touch Sensing Array Using Ultra-Low-Power Always-On Event Detection. IEEE Trans. Circuits Syst. II Express Briefs Hyeri Roh, Woo-Seok Choi
2023	—	`conf`	A Near-Threshold Ring-Oscillator-Based ILCM with Edge-Selective Error Detector Achieving -64 dBc Reference-Spur and -239 dB FoM. ESSCIRC Jiwon Shin, Joonghyun Song, Jihee Kim, Woo-Seok Choi
2023	—	`conf`	A PAM4 Level Mismatch Adjustment Scheme for 48-Gb/s PAM4 Memory Tester Bridge. A-SSCC Daeho Yun, Minsu Park, Kahyun Kim, Kyungmin Baek, Eonhui Lee, Woo-Seok Choi, Deog-Kyoon Jeong
2023	—	`conf`	A Pixel Driver Design Technique to Obtain a High-Quality Depth Map in Indirect Time-of-Flight Sensors. ISOCC Jeongeun Song, Sunyoung Lee, Minseok Shin, Ohjun Kwon, Hansang Kim, Yujin Park, Gyubeom Hwang, Hyekyoung Jung, Hoesam Jeong, Changrock Song, Woo-Seok Choi
2023	—	`conf`	An Analog Integrate-and-Fire Neuron with Robust Soft Reset Mechanism. ISOCC Jia Park, Woo-Seok Choi
2023	—	`conf`	Design of Energy-Efficient Cryptographically Secure Pseudo-Random Number Generators Using High-Level Synthesis. ISOCC Hyeri Roh, Woo-Seok Choi
2023	A	`conf`	Fast Performance Evaluation Methodology for High-speed Memory Interfaces. DATE Taehoon Kim, Yoona Lee, Woo-Seok Choi
2023	J	`jnl`	Hyena: Optimizing Homomorphically Encrypted Convolution for Private CNN Inference. CoRR Hyeri Roh, Woo-Seok Choi
2023	—	`conf`	JBNU at TREC 2023 Product Search Track. TREC Gi-taek An, Woo-Seok Choi, Jun-Yong Park, Kyung-Soon Lee
2023	—	`conf`	Performance Comparison of Clocked Comparators Using Impulse Sensitivity Function. ISOCC Taehoon Kim, Woo-Seok Choi
2023	J	`jnl`	Phase Noise Analysis for Stochastically Injected Oscillators. IEEE Trans. Circuits Syst. II Express Briefs Jiwon Shin, Woo-Seok Choi
2023	J	`jnl`	Sagnac Effect Compensations and Locked States in a Ring Laser Gyroscope. Sensors Woo-Seok Choi, Kyu-Min Shim, Kyung-Ho Chong, Jun-Eon An, Cheon-Joong Kim, Byung-Yoon Park
2023	J	`jnl`	Verification and performance comparison of CNN-based algorithms for two-step helmet-wearing detection. Expert Syst. Appl. Ju-Yeon Lee, Woo-Seok Choi, Sang-Hyun Choi
2022	—	`conf`	0.41-pJ/b/dB Asymmetric Simultaneous Bidirectional Transceivers With PAM-4 Forward and PAM-2 Back Channels for 5-m Automotive Camera Link. VLSI Technology and Circuits Yunhee Lee, Woonghee Lee, Minkyo Shim, Soyeong Shin, Woo-Seok Choi, Deog-Kyoon Jeong
2022	J	`jnl`	A 2.5-32 Gb/s Gen 5-PCIe Receiver With Multi-Rate CDR Engine and Hybrid DFE. IEEE Trans. Circuits Syst. II Express Briefs Moon-Chul Choi, Sanghee Lee, Seungha Roh, Kwangho Lee, Jonghyun Oh, Sungwoo Kim, Kwandong Kim, Woo-Seok Choi, Jaeha Kim, Deog-Kyoon Jeong
2022	J	`jnl`	A 32-Gb/s PAM4-Binary Bridge With Sampler Offset Cancellation for Memory Testing. IEEE Trans. Circuits Syst. II Express Briefs Daeho Yun, Eonhui Lee, Woosong Jung, Kahyun Kim, Kyung-Min Beak, Jihee Kim, Hyun Bae Lee, Byeongseon Ko, Woo-Seok Choi, Deog-Kyoon Jeong
2022	—	`conf`	A Highly Linear Digitally Controlled Delay Line with Reduced Duty Cycle Distortion. ISOCC Joonghyun Song, Woo-Seok Choi
2022	J	`jnl`	A Low-Jitter 8-GHz RO-Based ADPLL With PVT-Robust Replica-Based Analog Closed Loop for Supply Noise Compensation. IEEE J. Solid State Circuits Hyojun Kim, Woosong Jung, Kwandong Kim, Sungwoo Kim, Woo-Seok Choi, Deog-Kyoon Jeong
2022	J	`jnl`	A Residue-Current-Locked Hybrid Low-Dropout Regulator Supporting Ultralow Dropout of Sub-50 mV With Fast Settling Time Below 10 ns. IEEE J. Solid State Circuits Young-Ha Hwang, Jonghyun Oh, Woo-Seok Choi, Deog-Kyoon Jeong, Jun-Eun Park
2022	J	`jnl`	Area and Power Efficient 10B6Q PAM-4 DC Balance Coder for Automotive Camera Link. IEEE Trans. Circuits Syst. II Express Briefs Woonghee Lee, Minkyo Shim, Yunhee Lee, Heejin Yang, Soyeong Shin, Woo-Seok Choi, Deog-Kyoon Jeong
2022	—	`conf`	Energy-Efficient High-Accuracy Spiking Neural Network Inference Using Time-Domain Neurons. AICAS Joonghyun Song, Jiwon Shin, Hanseok Kim, Woo-Seok Choi
2022	J	`jnl`	Energy-Efficient High-Accuracy Spiking Neural Network Inference Using Time-Domain Neurons. CoRR Joonghyun Song, Jiwon Shin, Hanseok Kim, Woo-Seok Choi
2022	—	`conf`	Impact of Oscillator Phase Noise on Time-Domain SNN Performance. ISOCC Jia Park, Woo-Seok Choi
2022	—	`conf`	Impact of PI Nonlinearity on High-Resolution Frequency-to-Digital Converter. ISOCC Honggyoo Ahn, Joonghyun Song, Woo-Seok Choi
2022	C	`conf`	Improving Spiking Neural Network Accuracy Using Time-based Neurons. ISCAS Hanseok Kim, Woo-Seok Choi
2022	J	`jnl`	Improving Spiking Neural Network Accuracy Using Time-based Neurons. CoRR Hanseok Kim, Woo-Seok Choi
2022	—	`conf`	Performance Variability Modeling of Analog Circuits Using Improved Orthogonal Matching Pursuit. ISOCC Hyunjun Park, Woo-Seok Choi
2021	—	`conf`	0.37-pJ/b/dB PAM-4 Transmitter and Adaptive Receiver with Fixed Data and Threshold Levels for 12-m Automotive Camera Link. ESSCIRC Woonghee Lee, Minkyo Shim, Yunhee Lee, Heejin Yang, Han-Gon Ko, Woo-Seok Choi, Deog-Kyoon Jeong
2020	J	`jnl`	A 12-Gb/s 10-ns Turn-On Time Rapid ON/OFF Baud-Rate DFE Receiver in 65-nm CMOS. IEEE J. Solid State Circuits Dongwook Kim, Mostafa Gamal Ahmed, Woo-Seok Choi, Ahmed Elkholy, Pavan Kumar Hanumolu
2019	J	`jnl`	A 0.016 mm IEEE J. Solid State Circuits Junheng Zhu, Woo-Seok Choi, Pavan Kumar Hanumolu
2019	J	`jnl`	A 15-Gb/s Sub-Baud-Rate Digital CDR. IEEE J. Solid State Circuits Dongwook Kim, Woo-Seok Choi, Ahmed Elkholy, Jack Kenney, Pavan Kumar Hanumolu
2018	J	`jnl`	A 0.45-0.7 V 1-6 Gb/s 0.29-0.58 pJ/b Source-Synchronous Transceiver Using Near-Threshold Operation. IEEE J. Solid State Circuits Woo-Seok Choi, Guanghua Shu, Mrunmay Talegaonkar, Yubo Liu, Da Wei, Luca Benini, Pavan Kumar Hanumolu
2018	—	`conf`	A 1.6ps peak-INL 5.3ns range two-step digital-to-time converter in 65nm CMOS. CICC Ahmed Elmallah, Mostafa Gamal Ahmed, Ahmed Elkholy, Woo-Seok Choi, Pavan Kumar Hanumolu
2018	J	`jnl`	A 10-MHz 2-800-mA 0.5-1.5-V 90% Peak Efficiency Time-Based Buck Converter With Seamless Transition Between PWM/PFM Modes. IEEE J. Solid State Circuits Seong Joong Kim, Woo-Seok Choi, Robert C. N. Pilawa-Podgurski, Pavan Kumar Hanumolu
2018	—	`conf`	A 15Gb/s 1.9pJ/bit sub-baud-rate digital CDR. CICC Dongwook Kim, Woo-Seok Choi, Ahmed Elkholy, Jack Kenney, Pavan Kumar Hanumolu
2018	A*	`conf`	Guaranteeing Local Differential Privacy on Ultra-Low-Power Systems. ISCA Woo-Seok Choi, Matthew Tomei, Jose Rodrigo Sanchez Vicarte, Pavan Kumar Hanumolu, Rakesh Kumar
2017	—	`conf`	29.6 A 3-to-10Gb/s 5.75pJ/b transceiver with flexible clocking in 65nm CMOS. ISSCC Romesh Kumar Nandwana, Saurabh Saxena, Ahmed Elkholy, Mrunmay Talegaonkar, Junheng Zhu, Woo-Seok Choi, Ahmed Elmallah, Pavan Kumar Hanumolu
2017	—	`conf`	A 10MHz 2mA-800mA 0.5V-1.5V 90% peak efficiency time-based buck converter with seamless transition between PWM/PFM modes. CICC Seong Joong Kim, Woo-Seok Choi, Robert C. N. Pilawa-Podgurski, Pavan Kumar Hanumolu
2017	J	`jnl`	A 2.8 mW/Gb/s, 14 Gb/s Serial Link Transceiver. IEEE J. Solid State Circuits Saurabh Saxena, Guanghua Shu, Romesh Kumar Nandwana, Mrunmay Talegaonkar, Ahmed Elkholy, Tejasvi Anand, Woo-Seok Choi, Pavan Kumar Hanumolu
2017	—	`conf`	A 45-75MHz 197-452µW oscillator with 164.6dB FoM and 2.3psrms period jitter in 65nm CMOS. CICC Junheng Zhu, Makrand Mahalley, Guanghua Shu, Woo-Seok Choi, Romesh Kumar Nandwana, Ahmed Elkholy, Bibhudatta Sahoo, Pavan Kumar Hanumolu
2017	J	`jnl`	A 5GHz Digital Fractional-N PLL Using a 1-bit Delta-Sigma Frequency-to-Digital Converter in 65 nm CMOS. IEEE J. Solid State Circuits Mrunmay Talegaonkar, Tejasvi Anand, Ahmed Elkholy, Amr Elshazly, Romesh Kumar Nandwana, Saurabh Saxena, Brian Young, Woo-Seok Choi, Pavan Kumar Hanumolu
2017	—	`—`	Design of energy-efficient high-speed wireline transceiver Woo-Seok Choi
2016	—	`conf`	23.1 A 16Mb/s-to-8Gb/s 14.1-to-5.9pJ/b source synchronous transceiver using DVFS and rapid on/off in 65nm CMOS. ISSCC Guanghua Shu, Woo-Seok Choi, Saurabh Saxena, Seong Joong Kim, Mrunmay Talegaonkar, Romesh Kumar Nandwana, Ahmed Elkholy, Da Wei, Timir Nandi, Pavan Kumar Hanumolu
2016	J	`jnl`	A 4-to-10.5 Gb/s Continuous-Rate Digital Clock and Data Recovery With Automatic Frequency Acquisition. IEEE J. Solid State Circuits Guanghua Shu, Woo-Seok Choi, Saurabh Saxena, Mrunmay Talegaonkar, Tejasvi Anand, Ahmed Elkholy, Amr Elshazly, Pavan Kumar Hanumolu
2015	—	`conf`	3.8 A 0.45-to-0.7V 1-to-6Gb/S 0.29-to-0.58pJ/b source-synchronous transceiver using automatic phase calibration in 65nm CMOS. ISSCC Woo-Seok Choi, Guanghua Shu, Mrunmay Talegaonkar, Yubo Liu, Da Wei, Luca Benini, Pavan Kumar Hanumolu
2015	—	`conf`	A 2.8mW/Gb/s 14Gb/s serial link transceiver in 65nm CMOS. VLSIC Saurabh Saxena, Guanghua Shu, Romesh Kumar Nandwana, Mrunmay Talegaonkar, Ahmed Elkholy, Tejasvi Anand, Seong Joong Kim, Woo-Seok Choi, Pavan Kumar Hanumolu
2015	J	`jnl`	A 3.7 mW Low-Noise Wide-Bandwidth 4.5 GHz Digital Fractional-N PLL Using Time Amplifier-Based TDC. IEEE J. Solid State Circuits Ahmed Elkholy, Tejasvi Anand, Woo-Seok Choi, Amr Elshazly, Pavan Kumar Hanumolu
2015	J	`jnl`	A Burst-Mode Digital Receiver With Programmable Input Jitter Filtering for Energy Proportional Links. IEEE J. Solid State Circuits Woo-Seok Choi, Tejasvi Anand, Guanghua Shu, Amr Elshazly, Pavan Kumar Hanumolu
2015	J	`jnl`	A Calibration-Free Fractional-N Ring PLL Using Hybrid Phase/Current-Mode Phase Interpolation Method. IEEE J. Solid State Circuits Romesh Kumar Nandwana, Tejasvi Anand, Saurabh Saxena, Seong Joong Kim, Mrunmay Talegaonkar, Ahmed Elkholy, Woo-Seok Choi, Amr Elshazly, Pavan Kumar Hanumolu
2014	—	`conf`	8.7 A 4-to-10.5Gb/s 2.2mW/Gb/s continuous-rate digital CDR with automatic frequency acquisition in 65nm CMOS. ISSCC Guanghua Shu, Woo-Seok Choi, Saurabh Saxena, Tejasvi Anand, Amr Elshazly, Pavan Kumar Hanumolu
2014	—	`conf`	A 3.7mW 3MHz bandwidth 4.5GHz digital fractional-N PLL with -106dBc/Hz In-band noise using time amplifier based TDC. VLSIC Ahmed Elkholy, Tejasvi Anand, Woo-Seok Choi, Amr Elshazly, Pavan Kumar Hanumolu
2014	—	`conf`	A 4.25GHz-4.75GHz calibration-free fractional-N ring PLL using hybrid phase/current-mode phase interpolator with 13.2dB phase noise improvement. VLSIC Romesh Kumar Nandwana, Tejasvi Anand, Saurabh Saxena, Seong Joong Kim, Mrunmay Talegaonkar, Ahmed Elkholy, Woo-Seok Choi, Amr Elshazly, Pavan Kumar Hanumolu
2014	—	`conf`	A 4.4-5.4GHz digital fractional-N PLL using ΔΣ frequency-to-digital converter. VLSIC Mrunmay Talegaonkar, Tejasvi Anand, Ahmed Elkholy, Amr Elshazly, Romesh Kumar Nandwana, Saurabh Saxena, Brian Young, Woo-Seok Choi, Pavan Kumar Hanumolu
2014	J	`jnl`	A Reference-Less Clock and Data Recovery Circuit Using Phase-Rotating Phase-Locked Loop. IEEE J. Solid State Circuits Guanghua Shu, Saurabh Saxena, Woo-Seok Choi, Mrunmay Talegaonkar, Rajesh Inti, Amr Elshazly, Brian Young, Pavan Kumar Hanumolu
2011	J	`jnl`	250 Mbps-5 Gbps Wide-Range CDR With Digital Vernier Phase Shifting and Dual-Mode Control in 0.13 μ m CMOS. IEEE J. Solid State Circuits Sang-Yoon Lee, Hyung-Rok Lee, Young-Ho Kwak, Woo-Seok Choi, Byoung-Joo Yoo, Daeyun Shim, Chulwoo Kim, Deog-Kyoon Jeong
2008	C	`conf`	Automated generation of product use case scenarios in product line development. CIT Woo-Seok Choi, Sungwon Kang, Ho-Jin Choi, Jongmoon Baik