Woo-Rham Bae - RankMe

41 papers C 6Journal 21Unranked 14

Year	Rank	Type	Title / Venue / Authors
2021	—	`conf`	4.3 An Eight-Core 1.44GHz RISC-V Vector Machine in 16nm FinFET. ISSCC Colin Schmidt, John Charles Wright, Zhongkai Wang, Eric Chang, Albert J. Ou, Woo-Rham Bae, Sean Huang, Anita Flynn, Brian C. Richards, Krste Asanovic, Elad Alon, Borivoje Nikolic
2021	J	`jnl`	LAYGO: A Template-and-Grid-Based Layout Generation Engine for Advanced CMOS Technologies. IEEE Trans. Circuits Syst. I Regul. Pap. Jaeduk Han, Woo-Rham Bae, Eric Chang, Zhongkai Wang, Borivoje Nikolic, Elad Alon
2021	J	`jnl`	Today's computing challenges: opportunities for computer hardware design. PeerJ Comput. Sci. Woo-Rham Bae
2019	—	`conf`	A Generated 7GS/s 8b Time-Interleaved SAR ADC with 38.2dB SNDR at Nyquist in 16nm CMOS FinFET. CICC Jaeduk Han, Eric Chang, Stevo Bailey, Zhongkai Wang, Woo-Rham Bae, Angie Wang, Nathan Narevsky, Amy Whitcombe, Pengpeng Lu, Borivoje Nikolic, Elad Alon
2019	J	`jnl`	A Mixed-Signal RISC-V Signal Analysis SoC Generator With a 16-nm FinFET Instance. IEEE J. Solid State Circuits Steven Bailey, Paul Rigge, Jaeduk Han, Richard Lin, Eric Chang, Howard Mao, Zhongkai Wang, Chick Markley, Adam M. Izraelevitz, Angie Wang, Nathan Narevsky, Woo-Rham Bae, Steve Shauck, Sergio Montano, Justin Norsworthy, Munir Razzaque, Wen Hau Ma, Akalu Lentiro, Matthew Doerflein, Darin Heckendorn, Jim McGrath, Franco DeSeta, Ronen Shoham, Mike Stellfox, Mark Snowden, Joseph Cole, Dan Fuhrman, Brian C. Richards, Jonathan Bachrach, Elad Alon, Borivoje Nikolic
2019	J	`jnl`	A Real-Time, 1.89-GHz Bandwidth, 175-kHz Resolution Sparse Spectral Analysis RISC-V SoC in 16-nm FinFET. IEEE J. Solid State Circuits Angie Wang, Woo-Rham Bae, Jaeduk Han, Stevo Bailey, Orhan Ocal, Paul Rigge, Zhongkai Wang, Kannan Ramchandran, Elad Alon, Borivoje Nikolic
2019	J	`jnl`	Reference Spur Reduction Techniques for a Phase-Locked Loop. IEEE Access Han-Gon Ko, Woo-Rham Bae, Gyu-Seob Jeong, Deog-Kyoon Jeong
2018	J	`jnl`	A 2.5-5.6 GHz Subharmonically Injection-Locked All-Digital PLL With Dual-Edge Complementary Switched Injection. IEEE Trans. Circuits Syst. I Regul. Pap. Sung-Yong Cho, Sungwoo Kim, Min-Seong Choo, Han-Gon Ko, Jinhyung Lee, Woo-Rham Bae, Deog-Kyoon Jeong
2018	J	`jnl`	A 32 Gb/s, 201 mW, MZM/EAM Cascode Push-Pull CML Driver in 65 nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs Jeongho Hwang, Gyu-Seob Jeong, Woo-Rham Bae, Jun-Eun Park, Chang-Soo Yoon, Jungmin Yoon, Jiho Joo, Gyungock Kim, Deog-Kyoon Jeong
2018	J	`jnl`	A 6.7-11.2 Gb/s, 2.25 pJ/bit, Single-Loop Referenceless CDR With Multi-Phase, Oversampling PFD in 65-nm CMOS. IEEE J. Solid State Circuits Kwanseo Park, Woo-Rham Bae, Jinhyung Lee, Jeongho Hwang, Deog-Kyoon Jeong
2018	—	`conf`	A Generated Multirate Signal Analysis RISC-V SoC in 16nm FinFET. A-SSCC Stevo Bailey, Jaeduk Han, Paul Rigge, Richard Lin, Eric Chang, Howard Mao, Zhongkai Wang, Chick Markley, Adam M. Izraelevitz, Angie Wang, Nathan Narevsky, Woo-Rham Bae, Steve Shauck, Sergio Montano, Justin Norsworthy, Munir Razzaque, Wen Hau Ma, Akalu Lentiro, Matthew Doerflein, Darin Heckendorn, Jim McGrath, Franco DeSeta, Ronen Shoham, Mike Stellfox, Mark Snowden, Joseph Cole, Dan Fuhrman, Brian C. Richards, Jonathan Bachrach, Elad Alon, Borivoje Nikolic
2018	—	`conf`	A Real-Time, Analog/Digital Co-Designed 1.89-GHz Bandwidth, 175-kHz Resolution Sparse Spectral Analysis RISC-V SoC in 16-nm FinFET. ESSCIRC Angie Wang, Woo-Rham Bae, Jaeduk Han, Stevo Bailey, Paul Rigge, Orhan Ocal, Zhongkai Wang, Kannan Ramchandran, Elad Alon, Borivoje Nikolic
2018	J	`jnl`	A Supply-Scalable-Serializing Transmitter With Controllable Output Swing and Equalization for Next-Generation Standards. IEEE Trans. Ind. Electron. Woo-Rham Bae, Haram Ju, Kwanseo Park, Jaeduk Han, Deog-Kyoon Jeong
2018	J	`jnl`	A Variation-Tolerant, Sneak-Current-Compensated Readout Scheme for Cross-Point Memory Based on Two-Port Sensing Technique. IEEE Trans. Circuits Syst. II Express Briefs Woo-Rham Bae, Kyung Jean Yoon, Taeksang Song, Borivoje Nikolic
2018	—	`conf`	BAG2: A process-portable framework for generator-based AMS circuit design. CICC Eric Chang, Jaeduk Han, Woo-Rham Bae, Zhongkai Wang, Nathan Narevsky, Borivoje Nikolic, Elad Alon
2017	—	`conf`	A 27.1 mW, 7.5-to-11.1 Gb/s single-loop referenceless CDR with direct Up/dn control. CICC Kwanseo Park, Woo-Rham Bae, Deog-Kyoon Jeong
2017	J	`jnl`	A 28 Gb/s 1.6 pJ/b PAM-4 Transmitter Using Fractionally Spaced 3-Tap FFE and G IEEE Trans. Circuits Syst. II Express Briefs Haram Ju, Moon-Chul Choi, Gyu-Seob Jeong, Woo-Rham Bae, Deog-Kyoon Jeong
2017	J	`jnl`	Review of CMOS Integrated Circuit Technologies for High-Speed Photo-Detection. Sensors Gyu-Seob Jeong, Woo-Rham Bae, Deog-Kyoon Jeong
2017	J	`jnl`	Use of Phase Delay Analysis for Evaluating Wideband Circuits: An Alternative to Group Delay Analysis. IEEE Trans. Very Large Scale Integr. Syst. Woo-Rham Bae, Borivoje Nikolic, Deog-Kyoon Jeong
2016	J	`jnl`	A 0.36 pJ/bit, 0.025 mm IEEE Trans. Circuits Syst. I Regul. Pap. Woo-Rham Bae, Gyu-Seob Jeong, Kwanseo Park, Sung-Yong Cho, Yoonsoo Kim, Deog-Kyoon Jeong
2016	J	`jnl`	A 1-pJ/bit, 10-Gb/s/ch Forwarded-Clock Transmitter Using a Resistive Feedback Inverter-Based Driver in 65-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs Woo-Rham Bae, Gyu-Seob Jeong, Deog-Kyoon Jeong
2016	J	`jnl`	A 20 Gb/s 0.4 pJ/b Energy-Efficient Transmitter Driver Utilizing Constant- G IEEE J. Solid State Circuits Gyu-Seob Jeong, Sang-Hyeok Chu, Yoonsoo Kim, Sungchun Jang, Sungwoo Kim, Woo-Rham Bae, Sung-Yong Cho, Haram Ju, Deog-Kyoon Jeong
2016	—	`conf`	A 6-to-32 Gb/s voltage-mode transmitter with scalable supply, voltage swing, and pre-emphasis in 65-nm CMOS. A-SSCC Woo-Rham Bae, Haram Ju, Kwanseo Park, Deog-Kyoon Jeong
2016	J	`jnl`	A 7.6 mW, 414 fs RMS-Jitter 10 GHz Phase-Locked Loop for a 40 Gb/s Serial Link Transmitter Based on a Two-Stage Ring Oscillator in 65 nm CMOS. IEEE J. Solid State Circuits Woo-Rham Bae, Haram Ju, Kwanseo Park, Sung-Yong Cho, Deog-Kyoon Jeong
2016	C	`conf`	A 800-Mb/s 0.89-pJ/b reference-less optical receiver with pulse-position-modulation scheme. ISCAS Haram Ju, Woo-Rham Bae, Gyu-Seob Jeong, Deog-Kyoon Jeong
2016	C	`conf`	A fully integrated 1-pJ/bit 10-Gb/s/ch forwarded-clock transmitter with a resistive feedback inverter based driver in 65-nm CMOS. ISCAS Woo-Rham Bae, Gyu-Seob Jeong, Deog-Kyoon Jeong
2016	J	`jnl`	Design of Silicon Photonic Interconnect ICs in 65-nm CMOS Technology. IEEE Trans. Very Large Scale Integr. Syst. Woo-Rham Bae, Gyu-Seob Jeong, Yoonsoo Kim, Hankyu Chi, Deog-Kyoon Jeong
2015	C	`conf`	A 10 Gb/s hybrid PLL-based forwarded clock receiver in 65-nm CMOS. ISCAS Kwanseo Park, Woo-Rham Bae, Haram Ju, Jinhyung Lee, Gyu-Seob Jeong, Yoonsoo Kim, Deog-Kyoon Jeong
2015	—	`conf`	A 20 Gb/s 0.4 pJ/b energy-efficient transmitter driver architecture utilizing constant Gm. A-SSCC Gyu-Seob Jeong, Sang-Hyeok Chu, Yoonsoo Kim, Sungchun Jang, Sungwoo Kim, Woo-Rham Bae, Sung-Yong Cho, Haram Ju, Deog-Kyoon Jeong
2015	J	`jnl`	A 22 to 26.5 Gb/s Optical Receiver With All-Digital Clock and Data Recovery in a 65 nm CMOS Process. IEEE J. Solid State Circuits Sang-Hyeok Chu, Woo-Rham Bae, Gyu-Seob Jeong, Sungchun Jang, Sungwoo Kim, Jiho Joo, Gyungock Kim, Deog-Kyoon Jeong
2015	—	`conf`	A 5-GHz subharmonically injection-locked all-digital PLL with complementary switched injection. ESSCIRC Sung-Yong Cho, Sungwoo Kim, Min-Seong Choo, Jinhyung Lee, Han-Gon Ko, Sungchun Jang, Sang-Hyeok Chu, Woo-Rham Bae, Yoonsoo Kim, Deog-Kyoon Jeong
2015	—	`conf`	A 7.6 mW, 214-fs RMS jitter 10-GHz phase-locked loop for 40-Gb/s serial link transmitter based on two-stage ring oscillator in 65-nm CMOS. A-SSCC Woo-Rham Bae, Haram Ju, Kwanseo Park, Sung-Yong Cho, Deog-Kyoon Jeong
2015	C	`conf`	A low-power pulse position modulation transceiver. ISCAS Woo-Rham Bae, Chang-Soo Yoon, Deog-Kyoon Jeong
2015	J	`jnl`	A power-efficient 600-mV Int. J. Circuit Theory Appl. Woo-Rham Bae, Deog-Kyoon Jeong
2014	—	`conf`	A 0.36 pJ/bit, 12.5 Gb/s forwarded-clock receiver with a sample swapping scheme and a half-bit delay line. ESSCIRC Woo-Rham Bae, Gyu-Seob Jeong, Kwanseo Park, Sung-Yong Cho, Yoonsoo Kim, Deog-Kyoon Jeong
2014	C	`conf`	A 10-Gb/s 6-Vpp differential modulator driver in 65-nm CMOS. ISCAS Yoonsoo Kim, Woo-Rham Bae, Deog-Kyoon Jeong
2014	—	`conf`	A 26.5 Gb/s optical receiver with all-digital clock and data recovery in 65nm CMOS process. A-SSCC Sang-Hyeok Chu, Woo-Rham Bae, Gyu-Seob Jeong, Jiho Joo, Gyungock Kim, Deog-Kyoon Jeong
2014	C	`conf`	A design of an area-efficient 10-GHz phase-locked loop for source-synchronous, multi-channel links in 90-nm CMOS technology. DDECS Woo-Rham Bae, Deog-Kyoon Jeong, Byoung-Joo Yoo
2014	—	`conf`	A study on using pulse generators to design a ring-VCO based bang-bang PLL/CDR with a consistent loop bandwidth. ICEIC Woo-Rham Bae, Deog-Kyoon Jeong
2014	J	`jnl`	Linearization Technique for Binary Phase Detectors in a Collaborative Timing Recovery Circuit. IEEE Trans. Very Large Scale Integr. Syst. Byoung-Joo Yoo, Woo-Rham Bae, Jiho Han, Jaeha Kim, Deog-Kyoon Jeong
2012	—	`conf`	Design of CMOS 5 Gb/s 4-PAM transceiver frontend for low-power memory interface. ISOCC Woo-Rham Bae, Byoung-Joo Yoo, Deog-Kyoon Jeong