Wonsik Yu

13 papers Journal 7Unranked 6
YearRankTypeTitle / Venue / Authors
2024 — conf
A 45-fsrms Accumulated Jitter PLL Using Advanced Design Techniques for PCIe Gen6 Reference Clock Generation in 2 nm MBCFET Technology.
A-SSCC
Subhadeep Datta, Arnab Banerjee, Ayush Tripathi, Dongmin Kang, Leesunghyuck, Hasung Lim, Wonsik Yu, Kgj Vishnu, Chanyoung Jeong, Sumanth Chakkirala, Avneesh Singh Verma, Sachin Kashyap, Eg Jeevarathinam, Sunil Kumar Pandey, Jongjae Ryu, Sanjeeb Kumar Ghosh
2023 — conf
A 16GHz 33fs rms Integrated Jitter FLL-less Gear Shifting Reference Sampling PLL.
CICC
Jusung Lee, Youngwoo Jo, Wonsik Yu, Wooseok Kim, Michael Choi, Sanghune Park, Jongshin Shin
2022 — conf
Clock Generator with IS026262 ASIL-D Grade Safety Mechanism for SoC Clocking Application.
ISSCC
Dokyung Lim, Sounghun Shin, Seungmin Lee, Kihyun Kwon, Jeongmin An, Wonsik Yu, Chanyoung Jeong, Wooseok Kim, Michael Choi, Jongshin Shin
2019 J jnl
A Second-Order ΔΣ Time-to-Digital Converter Using Highly Digital Time-Domain Arithmetic Circuits.
IEEE Trans. Circuits Syst. II Express Briefs
Dongin Kim, KwangSeok Kim, Wonsik Yu, SeongHwan Cho
2015 J jnl
A 0.22 ps rms Integrated Noise 15 MHz Bandwidth Fourth-Order ΔΣ Time-to-Digital Converter Using Time-Domain Error-Feedback Filter.
IEEE J. Solid State Circuits
Wonsik Yu, KwangSeok Kim, SeongHwan Cho
2015 J jnl
A Hybrid-Domain Two-Step Time-to-Digital Converter Using a Switch-Based Time-to-Voltage Converter and SAR ADC.
IEEE Trans. Circuits Syst. II Express Briefs
Jungho Kim, Young-Hwa Kim, KwangSeok Kim, Wonsik Yu, SeongHwan Cho
2014 J jnl
A 148fs
IEEE Trans. Circuits Syst. I Regul. Pap.
Wonsik Yu, KwangSeok Kim, SeongHwan Cho
2014 J jnl
A 9 bit, 1.12 ps Resolution 2.5 b/Stage Pipelined Time-to-Digital Converter in 65 nm CMOS Using Time-Register.
IEEE J. Solid State Circuits
KwangSeok Kim, Wonsik Yu, SeongHwan Cho
2013 — conf
A 148fsrms integrated noise 4MHz bandwidth all-digital second-order ΔΣ time-to-digital converter using gated switched-ring oscillator.
CICC
Wonsik Yu, KwangSeok Kim, SeongHwan Cho
2013 J jnl
A 7 bit, 3.75 ps Resolution Two-Step Time-to-Digital Converter in 65 nm CMOS Using Pulse-Train Time Amplifier.
IEEE J. Solid State Circuits
KwangSeok Kim, Young-Hwa Kim, Wonsik Yu, SeongHwan Cho
2013 J jnl
A Time-Domain High-Order MASH ΔΣ ADC Using Voltage-Controlled Gated-Ring Oscillator.
IEEE Trans. Circuits Syst. I Regul. Pap.
Wonsik Yu, Jaewook Kim, KwangSeok Kim, SeongHwan Cho
2012 — conf
A 7b, 3.75ps resolution two-step time-to-digital converter in 65nm CMOS using pulse-train time amplifier.
VLSIC
KwangSeok Kim, Young-Hwa Kim, Wonsik Yu, SeongHwan Cho
2011 — conf
A digital-intensive receiver front-end using VCO-based ADC with an embedded 2nd-Order anti-aliasing Sinc filter in 90nm CMOS.
ISSCC
Jaewook Kim, Wonsik Yu, Hyun-Kyu Yu, SeongHwan Cho