Won-Young Lee

30 papers C 6Journal 12Unranked 12
YearRankTypeTitle / Venue / Authors
2025 J jnl
A 0.25 pJ/bit Data-Rate-Dependent Reconfigurable Receiver With Dual-Mode Divider for Low-Power DDR Memory Interfaces.
IEEE Access
Giryong Lee, Won-Young Lee
2025 J jnl
A 1.62-8.1-Gb/s Single-Loop Referenceless CDR With Fast Frequency Acquisition Technique for Embedded DisplayPort.
IEEE Trans. Circuits Syst. II Express Briefs
Hyun-Bin Lee, Won-Young Lee
2025 J jnl
A 25-Gb/s Energy-Efficient PAM-4 Receiver Utilizing a Pulse Amplitude Comparator and Modified Summation Method.
IEEE Trans. Circuits Syst. I Regul. Pap.
Young-Min Lee, Won-Young Lee
2025 C conf
An Energy-Efficient 21Gb/s Duobinary Transceiver for High-Speed Serial Interfaces.
ISCAS
Seul-Ki Han, Won-Young Lee
2024 J jnl
A 0.6-V 4-MS/s Asynchronous SAR ADC With 2-Bit Conversion/Cycle Time-Domain Comparator.
IEEE Trans. Circuits Syst. II Express Briefs
Sang-Hun Lee, Won-Young Lee
2024 — conf
A Reference Voltage Generator Using Level Tracking Scheme for Low-Swing PAM-3 Signaling.
ISOCC
Seul-Ki Han, Won-Young Lee
2024 C conf
A Wide-Range Reference-Less Digital Clock and Data Recovery for Harmonic-Lock-Free Frequency Acquisition.
ISCAS
Hyun-Bin Lee, Yoon Heo, Won-Young Lee
2024 — conf
Design of a Low-Jitter Digitally Controlled Oscillator With Supply Noise Compensation.
ICEIC
Min-Ji Kim, Won-Young Lee
2023 — conf
A Study on the Assistive System for Safe Elevator Get on of Wheelchair Users with Upper Limb Disability.
ICEIC
Daewe Kim, Won-Young Lee, Jinwoo Shin, Eung-Hyuk Lee
2023 — conf
An Anti-Harmonic-Lock Frequency Detector for Continuous-Rate Clock and Data Recovery.
ISOCC
Hyun-Bin Lee, Won-Young Lee
2022 — conf
A 1.0-V 12-Gb/s Two-FIR Tap DFE with Tap Weighting Adjustable Filters.
ICEIC
Giryong Lee, Won-Young Lee
2022 J jnl
A 10-Bit 400-KS/s Low Noise Asynchronous SAR ADC with Dual-Domain Comparator for Input-Referred Noise Reduction.
Sensors
Sang-Hun Lee, Won-Young Lee
2022 J jnl
A Single-Ended Transmitter With Low Switching Noise Injection and Quadrature Clock Correction Schemes for DRAM Interface.
IEEE Access
Dong-Wan Ko, Won-Young Lee
2022 — conf
A Wide Range Digitally Controlled Oscillator with Direct Proportional Loop Control.
ISOCC
Yoon Heo, Won-Young Lee
2021 — conf
A 0.6-V 400-KS/s Low Noise Asynchronous SAR ADC With Dual-Domain Comparison.
ISOCC
Sang-Hoon Lee, Won-Young Lee
2021 C conf
A Low EMI Transmitter for DRAM Interface with Quadrature Clock Corrector.
ISCAS
Dong-Wan Ko, Won-Young Lee
2020 — conf
A Fast Locking Duty Cycle Corrector with High Accuracy.
ISOCC
Eun-Young Jung, Won-Young Lee
2015 — conf
A 6.4Gb/s/pin at sub-1V supply voltage TX-interleaving technique for mobile DRAM interface.
VLSIC
Chang-Kyo Lee, Min-Su Ahn, Daesik Moon, Kiho Kim, Yoon-Joo Eom, Won-Young Lee, Jongmin Kim, Sanghyuk Yoon, Baekkyu Choi, Seokhong Kwon, Joon-Young Park, Seung-Jun Bae, Yong-Cheol Bae, Jung-Hwan Choi, Seong-Jin Jang, Gyo-Young Jin
2013 J jnl
A LOG-Induced SSN-Tolerant Transceiver for On-Chip Interconnects in COG-Packaged Source Driver IC for TFT-LCD.
IEEE Trans. Circuits Syst. II Express Briefs
Won-Young Lee, Jiehwan Oh, Lee-Sup Kim
2013 J jnl
A Unified Graphics and Vision Processor With a 0.89 µW/fps Pose Estimation Engine for Augmented Reality.
IEEE Trans. Very Large Scale Integr. Syst.
Jae-Sung Yoon, Jeong-Hyun Kim, Hyo-Eun Kim, Won-Young Lee, Seok-Hoon Kim, Kyusik Chung, Jun-Seok Park, Lee-Sup Kim
2013 — conf
A study on methods for improving the straightness of the intelligent walker to move on slope.
URAI
Won-Young Lee, Seung-Hyun Lee, Mun-Suck Jang, Eung-Hyuk Lee
2012 J jnl
A 5.4-Gb/s Clock and Data Recovery Circuit Using Seamless Loop Transition Scheme With Minimal Phase Noise Degradation.
IEEE Trans. Circuits Syst. I Regul. Pap.
Won-Young Lee, Lee-Sup Kim
2012 J jnl
A 5.4/2.7/1.62-Gb/s Receiver for DisplayPort Version 1.2 With Multi-Rate Operation Scheme.
IEEE Trans. Circuits Syst. I Regul. Pap.
Won-Young Lee, Kyu-Dong Hwang, Lee-Sup Kim
2012 J jnl
An Adaptive Equalizer With the Capacitance Multiplication for DisplayPort Main Link in 0.18-µm CMOS.
IEEE Trans. Very Large Scale Integr. Syst.
Won-Young Lee, Lee-Sup Kim
2011 C conf
A 5.4 Gb/s clock and data recovery circuit using the seamless loop transition scheme without phase noise degradation.
ISCAS
Won-Young Lee, Lee-Sup Kim
2011 J jnl
A Spread Spectrum Clock Generator for DisplayPort Main Link.
IEEE Trans. Circuits Syst. II Express Briefs
Won-Young Lee, Lee-Sup Kim
2010 — conf
A graphics and vision unified processor with 0.89µW/fps pose estimation engine for augmented reality.
ISSCC
Jae-Sung Yoon, Jeong-Hyun Kim, Hyo-Eun Kim, Won-Young Lee, Seok-Hoon Kim, Kyusik Chung, Jun-Seok Park, Lee-Sup Kim
2010 C conf
A high resolution metastability-independent two-step gated ring oscillator TDC with enhanced noise shaping.
ISCAS
Sang-Hye Chung, Kyu-Dong Hwang, Won-Young Lee, Lee-Sup Kim
2009 C conf
A Spread Spectrum Clock Generator with Spread Ratio Error Reduction Scheme for DisplayPort Main Link.
ISCAS
Won-Young Lee, Lee-Sup Kim
2007 — conf
Authenticated On-Demand Ad Hoc Routing Protocol without Pre-shared Key Distribution.
BLISS
Youngho Park, Won-Young Lee, Kyung Hyune Rhee