Won-Joo Yun

16 papers C 3Journal 4Unranked 9
YearRankTypeTitle / Venue / Authors
2017 J jnl
A 1.2 V 20 nm 307 GB/s HBM DRAM With At-Speed Wafer-Level IO Test Scheme and Adaptive Refresh Considering Temperature Distribution.
IEEE J. Solid State Circuits
Kyomin Sohn, Won-Joo Yun, Reum Oh, Chi-Sung Oh, Seong-Young Seo, Min-Sang Park, Dong-Hak Shin, Won-Chang Jung, Sang-Hoon Shin, Je-Min Ryu, Hye-Seung Yu, Jae-Hun Jung, Hyunui Lee, Seok-Yong Kang, Young-Soo Sohn, Jung-Hwan Choi, Yong-Cheol Bae, Seong-Jin Jang, Gyo-Young Jin
2016 — conf
18.2 A 1.2V 20nm 307GB/s HBM DRAM with at-speed wafer-level I/O test scheme and adaptive refresh considering temperature distribution.
ISSCC
Kyomin Sohn, Won-Joo Yun, Reum Oh, Chi-Sung Oh, Seong-Young Seo, Min-Sang Park, Dong-Hak Shin, Won-Chang Jung, Sang-Hoon Shin, Je-Min Ryu, Hye-Seung Yu, Jae-Hun Jung, Kyung-Woo Nam, Seouk-Kyu Choi, Jae-Wook Lee, Uksong Kang, Young-Soo Sohn, Jung-Hwan Choi, Chi-Wook Kim, Seong-Jin Jang, Gyo-Young Jin
2016 — conf
Design of non-contact 2Gb/s I/O test methods for high bandwidth memory (HBM).
A-SSCC
Hyunui Lee, Sukyong Kang, Hye-Seung Yu, Won-Joo Yun, Jae-Hun Jung, Sungoh Ahn, Wang-Soo Kim, Beomyong Kil, Yoo-Chang Sung, Sang-Hoon Shin, Yong-Sik Park, Yong-Hwan Kim, Kyung-Woo Nam, Indal Song, Kyomin Sohn, Yong-Cheol Bae, Jung-Hwan Choi, Seong-Jin Jang, Gyo-Young Jin
2015 — conf
17.7 A digital DLL with hybrid DCC using 2-step duty error extraction and 180° phase aligner for 2.67Gb/S/pin 16Gb 4-H stack DDR4 SDRAM with TSVs.
ISSCC
Won-Joo Yun, Indal Song, Hanki Jeoung, Hundai Choi, Seok-Ho Lee, Jun-Bae Kim, Chi-Wook Kim, Jung-Hwan Choi, Seong-Jin Jang, Joo-Sun Choi
2013 C conf
A 1.26mW/Gbps 8 locking cycles versatile all-digital CDR with TDC combined DLL.
ISCAS
Yuki Urano, Won-Joo Yun, Tadahiro Kuroda, Hiroki Ishikuro
2012 — conf
A 7Gb/s/link non-contact memory module for multi-drop bus system using energy-equipartitioned coupled transmission line.
ISSCC
Won-Joo Yun, Shinya Nakano, Wataru Mizuhara, Atsutake Kosuge, Noriyuki Miura, Hiroki Ishikuro, Tadahiro Kuroda
2011 — conf
A 0.6V noise rejectable all-digital CDR with free running TDC for a pulse-based inductive-coupling interface.
A-SSCC
Won-Joo Yun, Hiroki Ishikuro, Tadahiro Kuroda
2011 J jnl
A 3.57 Gb/s/pin Low Jitter All-Digital DLL With Dual DCC Circuit for GDDR3 DRAM in 54-nm CMOS Technology.
IEEE Trans. Very Large Scale Integr. Syst.
Won-Joo Yun, Hyun-Woo Lee, Dongsuk Shin, Suki Kim
2010 C conf
A 7.7mW/1.0ns/1.35V delay locked loop with racing mode and OA-DCC for DRAM interface.
ISCAS
Hyun-Woo Lee, Yong-Hoon Kim, Won-Joo Yun, Eun Young Park, Kang Youl Lee, Jaeil Kim, Kwang Hyun Kim, Jongho Jung, Kyung Whan Kim, Nam Gyu Rye, Kwan-Weon Kim, Jun Hyun Chun, Chulwoo Kim, Young-Jung Choi, Byong-Tae Chung, Joong Sik Kih
2009 — conf
A 1.6V 3.3Gb/s GDDR3 DRAM with dual-mode phase- and delay-locked loop using power-noise management with unregulated power supply in 54nm CMOS.
ISSCC
Hyun-Woo Lee, Won-Joo Yun, Young-Kyoung Choi, Hyang-Hwa Choi, Jong-Jin Lee, Ki-Han Kim, Shin-Deok Kang, Ji-Yeon Yang, Jae-Suck Kang, Hyeng-Ouk Lee, Dong-Uk Lee, Sujeong Sim, Young-Ju Kim, Won-Jun Choi, Keun-Soo Song, Sang-Hoon Shin, Hyung-Wook Moon, Seung-Wook Kwack, Jung-Woo Lee, Nak-Kyu Park, Kwan-Weon Kim, Young-Jung Choi, Jin-Hong Ahn, Byong-Tae Chung
2009 C conf
A Fast-lock Synchronous Multi-phase Clock Generator based on a Time-to-digital Converter.
ISCAS
Dongsuk Shin, Jabeom Koo, Won-Joo Yun, Young-Jung Choi, Chulwoo Kim
2009 J jnl
Coverage expandable current type code controlled DCC with TDC-based range selector.
IEICE Electron. Express
Won-Joo Yun, Hyun-Woo Lee, Dongsuk Shin, Young-Jung Choi, Suki Kim
2008 — conf
A 0.1-to-1.5GHz 4.2mW All-Digital DLL with Dual Duty-Cycle Correction Circuit and Update Gear Circuit for DRAM in 66nm CMOS Technology.
ISSCC
Won-Joo Yun, Hyun-Woo Lee, Dongsuk Shin, Shin-Deok Kang, Ji-Yeon Yang, Hyeng-Ouk Lee, Dong-Uk Lee, Sujeong Sim, Young-Ju Kim, Won-Jun Choi, Keun-Soo Song, Sang-Hoon Shin, Hyang-Hwa Choi, Hyung-Wook Moon, Seung-Wook Kwack, Jung-Woo Lee, Young-Kyoung Choi, Nak-Kyu Park, Kwan-Weon Kim, Young-Jung Choi, Jin-Hong Ahn, Ye Seok Yang
2008 — conf
A 0.17-1.4GHz low-jitter all digital DLL with TDC-based DCC using pulse width detection scheme.
ESSCIRC
Dongsuk Shin, Won-Joo Yun, Hyun-Woo Lee, Young-Jung Choi, Suki Kim, Chulwoo Kim
2008 J jnl
A 4-bit 2GSamples/s parallel Flash ADC using comb-type reference ladder.
IEICE Electron. Express
Won-Joo Yun, Dongsuk Shin, Suki Kim
2008 — conf
Multi-Slew-Rate Output Driver and Optimized Impedance-Calibration Circuit for 66nm 3.0Gb/s/pin DRAM Interface.
ISSCC
Dong-Uk Lee, Shin-Deok Kang, Nak-Kyu Park, Hyun-Woo Lee, Young-Kyoung Choi, Jung-Woo Lee, Seung-Wook Kwack, Hyeong-Ouk Lee, Won-Joo Yun, Sang-Hoon Shin, Kwan-Weon Kim, Young-Jung Choi, Ye Seok Yang