Wolfgang Roesner

12 papers A* 2A 2Journal 7Unranked 1
YearRankTypeTitle / Venue / Authors
2024 J jnl
Efficient Aspect Verification and Debugging of High-Performance Microprocessor Designs.
IEEE Des. Test
Arun Joseph, Pretty Mariam Jacob, Matthias Klein, Wolfgang Roesner
2019 J jnl
Verification at RTL Using Separation of Design Concerns.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Maya H. Safieddine, Fadi A. Zaraket, Rouwaida Kanj, Ali S. Elzein, Wolfgang Roesner
2015 A conf
Designer-level verification: an industrial experience story.
DATE
Stephen Bergman, Gabor Bobok, Walter Kowalski, Shlomit Koyfman, Shiri Moran, Ziv Nevo, Avigail Orni, Viresh Paruthi, Wolfgang Roesner, Gil Shurek, Vasantha Vuyyuru
2014 A* conf
Post-Silicon Validation of the IBM POWER8 Processor.
DAC
Amir Nahir, Manoj Dusanapudi, Shakti Kapoor, Kevin Reick, Wolfgang Roesner, Klaus-Dieter Schubert, Keith Sharp, Greg Wetli
2009 J jnl
Functional verification of the IBM System z10 processor chipset.
IBM J. Res. Dev.
Christopher A. Krygowski, Dean G. Bair, Rebecca M. Gott, Mark H. Decker, A. V. Giri, Christian Habermann, Matthias Heizmann, Stefan Letz, William J. Lewis, Steven M. Licker, H. Mallar, Edward C. McCain, Wolfgang Roesner, Nafiul Siddique, A. E. Seigler, Brian W. Thompto, Kai Weber, Ralf Winkelmann
2008 A* conf
ESL hand-off: fact or EDA fiction?
DAC
Hiroyuki Yagi, Wolfgang Roesner, Tim Kogel, Eshel Haritan, Hidekazu Tangi, Michael McNamara, Gary Smith, Nikil D. Dutt, Giovanni Mancini
2004 J jnl
Configurable system simulation model build comprising packaging design data.
IBM J. Res. Dev.
Hans-Werner Anderson, Hans Kriese, Wolfgang Roesner, Klaus-Dieter Schubert
2003 — conf
What Is beyond the RTL Horizon for Microprocessor and System Design?
CHARME
Wolfgang Roesner
2002 J jnl
Functional verification of the POWER4 microprocessor and POWER4 multiprocessor system.
IBM J. Res. Dev.
John M. Ludden, Wolfgang Roesner, Gerry M. Heiling, John R. Reysa, Jonathan R. Jackson, Bing-Lun Chu, Michael L. Behm, Jason Baumgartner, Richard D. Peterson, Jamee Abdulhafiz, William E. Bucy, John H. Klaus, Danny J. Klema, Tien N. Le, F. Danette Lewis, Philip E. Milling, Lawrence A. McConville, Bradley S. Nelson, Viresh Paruthi, Travis W. Pouarz, Audre D. Romonosky, Jeff Stuecheli, Kent D. Thompson, Dave W. Victor, Bruce Wile
2000 J jnl
EDA in IBM: past, present, and future.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
John A. Darringer, Evan E. Davidson, David J. Hathaway, Bernd Koenemann, Mark A. Lavin, Joseph K. Morrell, Khalid Rahmat, Wolfgang Roesner, Erich C. Schanzenbach, Gustavo E. Téllez, Louise Trevillyan
1988 J jnl
The logic design language and verification environment for the VLSI-/370.
Microprocess. Microprogramming
Wolfgang Roesner
1985 A conf
SESPATH: An ER Manipulation Language.
ER
Wolfgang Roesner