Wolfgang Kunz

160 papers A* 13A 30B 4C 17Misc 4Journal 32Unranked 57
YearRankTypeTitle / Venue / Authors
2026 — conf
PowerCourt: Formally Judging Benign-Looking Circuits in Multi-Tenant FPGA Environments.
LATS
Philipp Schmitz, Mohamed Shelkamy Ali, Dino Mehmedagic, Hassan Nassar, Jörg Henkel, Dominik Stoffel, Wolfgang Kunz
2025 A* conf
FastPath: A Hybrid Approach for Efficient Hardware Security Verification.
DAC
Lucas Deutschmann, Andres Meza, Dominik Stoffel, Wolfgang Kunz, Ryan Kastner
2025 — conf
HW/SW Formal Co-Verification of Rust-based Designs Using Hardware Abstraction Model.
ISVLSI
Sascha Neske, Bryan Olmos, Shuhang Zhang, Martin Kröning, Stefan Lankes, Wolfgang Kunz, Djones Lettnin
2025 — conf
Hey AI, Generate Me a Hardware Code! Agentic AI-based Hardware Design & Verification.
SBCCI
Deepak Narayan Gadde, Keerthan Kopparam Radhakrishna, Vaisakh Naduvodi Viswambharan, Aman Kumar, Djones Lettnin, Wolfgang Kunz, Sebastian Simon
2025 J jnl
Hey AI, Generate Me a Hardware Code! Agentic AI-based Hardware Design & Verification.
CoRR
Deepak Narayan Gadde, Keerthan Kopparam Radhakrishna, Vaisakh Naduvodi Viswambharan, Aman Kumar, Djones Lettnin, Wolfgang Kunz, Sebastian Simon
2025 A conf
Multi-Partner Project: Open-Source Design Tools for Co-Development of AI Algorithms and AI Chips: (Initial Stage).
DATE
Mehdi B. Tahoori, Jürgen Becker, Jörg Henkel, Wolfgang Kunz, Ulf Schlichtmann, Georg Sigl, Jürgen Teich, Norbert Wehn
2025 A conf
Okapi: Efficiently Safeguarding Speculative Data Accesses in Sandboxed Environments.
AsiaCCS
Philipp Schmitz, Tobias Jauch, Alex Wezel, Mohammad Rahmani Fadiheh, Thore Tiemann, Jonah Heller, Thomas Eisenbarth, Dominik Stoffel, Wolfgang Kunz
2025 B conf
Security Risks in AI Accelerators: Detecting RTL Vulnerabilities to Model Theft with Formal Verification.
ETS
Mohamed Shelkamy Ali, Lucas Deutschmann, Johannes Müller, Anna Lena Duque Antón, Mohammad Rahmani Fadiheh, Dominik Stoffel, Wolfgang Kunz
2025 Misc conf
Special Session - Hardware-Software Co-Design for Machine Learning Systems Made Open-Source.
CODES+ISSS
Mehdi B. Tahoori, Vincent Meyers, Mahboobe Sadeghipour Roodsari, Huashuangyang Xu, Jürgen Becker, Tanja Harbaum, Felix Frombach, Julian Höfer, Georgios Sotiropoulos, Jörg Henkel, Zeynep Demirdag, Heba Khdr, Hassan Nassar, Ulf Schlichtmann, Johannes Geier, Philipp van Kempen, Georg Sigl, Stefan Koegler, Matthias Probst, Jürgen Teich, Frank Hannig, Muhammad Sabih, Batuhan Sesli, Norbert Wehn, Lukas Steiner, Wolfgang Kunz, Mohamed Shelkamy Ali
2025 — conf
Synthesis-Aware Area Optimization for Safety Registers in Automotive SoCs.
ISVLSI
Shuhang Zhang, Bryan Olmos, Wolfgang Kunz, Djones Lettnin
2024 A conf
A Golden-Free Formal Method for Trojan Detection in Non-Interfering Accelerators.
DATE
Anna Lena Duque Antón, Johannes Müller, Lucas Deutschmann, Mohammad Rahmani Fadiheh, Dominik Stoffel, Wolfgang Kunz
2024 J jnl
A Scalable Formal Verification Methodology for Data-Oblivious Hardware.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Lucas Deutschmann, Johannes Müller, Mohammad Rahmani Fadiheh, Dominik Stoffel, Wolfgang Kunz
2024 C conf
Adaptable FWHW Formal Co-Verification of SoC RISC-V Components.
VLSI-SoC
Paulette Iskandar, Bryan Olmos, Wolfgang Kunz, Djones Lettnin
2024 — conf
An Automated Exhaustive Fault Analysis Technique guided by Processor Formal Verification Methods.
ISQED
Endri Kaja, Nicolas Gerlin, Bihan Zhao, Daniela Sanchez Lopera, Jad Al Halabi, Azam Sher Khan, Sebastian Prebeck, Dominik Stoffel, Wolfgang Kunz, Wolfgang Ecker
2024 — conf
An Automated and Effective Approach for SBST Generation Targeting RISC-V CPUs.
DFT
Endri Kaja, Nicolas Gerlin, Jad Al Halabi, Ares Tahiraga, Sebastian Prebeck, Dominik Stoffel, Wolfgang Kunz, Wolfgang Ecker
2024 — conf
Data-Oblivious and Performant: On Designing Security-Conscious Hardware.
LATS
Lucas Deutschmann, Yazan Kazhalawi, Jonathan Seckinger, Anna Lena Duque Antón, Johannes Müller, Mohammad Rahmani Fadiheh, Dominik Stoffel, Wolfgang Kunz
2024 — conf
Efficient Stimuli Generation using Reinforcement Learning in Design Verification.
SMACD
Deepak Narayan Gadde, Thomas Nalapat, Aman Kumar, Djones Lettnin, Wolfgang Kunz, Sebastian Simon
2024 J jnl
Efficient Stimuli Generation using Reinforcement Learning in Design Verification.
CoRR
Deepak Narayan Gadde, Thomas Nalapat, Aman Kumar, Djones Lettnin, Wolfgang Kunz, Sebastian Simon
2024 A* conf
MCU-Wide Timing Side Channels and Their Detection.
DAC
Johannes Müller, Anna Lena Duque Antón, Lucas Deutschmann, Dino Mehmedagic, Cristiano Rodrigues, Daniel Oliveira, Mohammad Rahmani Fadiheh, Keerthikumara Devarajegowda, Sandro Pinto, Dominik Stoffel, Wolfgang Kunz
2024 — conf
Special Session: A Mixed Simulation-, Emulation-, and Formal-Based Fault Analysis Methodology for RISC-V.
DFT
Endri Kaja, Nicolas Gerlin, Ares Tahiraga, Jad Al Halabi, Sebastian Prebeck, Dominik Stoffel, Wolfgang Kunz, Wolfgang Ecker
2024 A conf
VeriCHERI: Exhaustive Formal Security Verification of CHERI at the RTL.
ICCAD
Anna Lena Duque Antón, Johannes Müller, Philipp Schmitz, Tobias Jauch, Alex Wezel, Lucas Deutschmann, Mohammad Rahmani Fadiheh, Dominik Stoffel, Wolfgang Kunz
2024 J jnl
VeriCHERI: Exhaustive Formal Security Verification of CHERI at the RTL.
CoRR
Anna Lena Duque Antón, Johannes Müller, Philipp Schmitz, Tobias Jauch, Alex Wezel, Lucas Deutschmann, Mohammad Rahmani Fadiheh, Dominik Stoffel, Wolfgang Kunz
2023 J jnl
A Golden-Free Formal Method for Trojan Detection in Non-Interfering Accelerators.
CoRR
Anna Lena Duque Antón, Johannes Müller, Lucas Deutschmann, Mohammad Rahmani Fadiheh, Dominik Stoffel, Wolfgang Kunz
2023 J jnl
A New Security Threat in MCUs - SoC-wide timing side channels and how to find them.
CoRR
Johannes Müller, Anna Lena Duque Antón, Lucas Deutschmann, Dino Mehmedagic, Mohammad Rahmani Fadiheh, Dominik Stoffel, Wolfgang Kunz
2023 J jnl
A Scalable Formal Verification Methodology for Data-Oblivious Hardware.
CoRR
Lucas Deutschmann, Johannes Müller, Mohammad Rahmani Fadiheh, Dominik Stoffel, Wolfgang Kunz
2023 J jnl
An Exhaustive Approach to Detecting Transient Execution Side Channels in RTL Designs of Processors.
IEEE Trans. Computers
Mohammad Rahmani Fadiheh, Alex Wezel, Johannes Müller, Jörg Bormann, Sayak Ray, Jason M. Fung, Subhasish Mitra, Dominik Stoffel, Wolfgang Kunz
2023 A* conf
Design of Access Control Mechanisms in Systems-on-Chip with Formal Integrity Guarantees.
USENIX Security Symposium
Dino Mehmedagic, Mohammad Rahmani Fadiheh, Johannes Müller, Anna Lena Duque Antón, Dominik Stoffel, Wolfgang Kunz
2023 J jnl
Fault Attacks on Access Control in Processors: Threat, Formal Analysis and Microarchitectural Mitigation.
IEEE Access
Anna Lena Duque Antón, Johannes Müller, Mohammad Rahmani Fadiheh, Dominik Stoffel, Wolfgang Kunz
2023 J jnl
Okapi: A Lightweight Architecture for Secure Speculation Exploiting Locality of Memory Accesses.
CoRR
Philipp Schmitz, Tobias Jauch, Alex Wezel, Mohammad Rahmani Fadiheh, Thore Tiemann, Jonah Heller, Thomas Eisenbarth, Dominik Stoffel, Wolfgang Kunz
2023 A conf
Secure-by-Construction Design Methodology for CPUs: Implementing Secure Speculation on the RTL.
ICCAD
Tobias Jauch, Alex Wezel, Mohammad Rahmani Fadiheh, Philipp Schmitz, Sayak Ray, Jason M. Fung, Christopher W. Fletcher, Dominik Stoffel, Wolfgang Kunz
2023 — conf
UPEC-PN: Exhaustive constant time verification of low-level software using property checking.
MBMV
Philipp Schmitz, Johannes Mueller, Christian Bartsch, Dominik Stoffel, Wolfgang Kunz
2022 — conf
Compositional Fault Propagation Analysis in Embedded Systems using Abstract Interpretation.
MBMV
Christian Bartsch, Stephan Wilhelm, Daniel Kästner, Dominik Stoffel, Wolfgang Kunz
2022 C conf
Design of a Tightly-Coupled RISC-V Physical Memory Protection Unit for Online Error Detection.
VLSI-SoC
Nicolas Gerlin, Endri Kaja, Monideep Bora, Keerthikumara Devarajegowda, Dominik Stoffel, Wolfgang Kunz, Wolfgang Ecker
2022 C conf
Fast and Accurate Model-Driven FPGA-based System-Level Fault Emulation.
VLSI-SoC
Endri Kaja, Nicolas Gerlin, Monideep Bora, Gabriel Rutsch, Keerthikumara Devarajegowda, Dominik Stoffel, Wolfgang Kunz, Wolfgang Ecker
2022 C conf
Generation of Formal CPU Profiles for Embedded Systems.
VLSI-SoC
Stian Gerlach Sørensen, Christian Bartsch, Dominik Stoffel, Wolfgang Kunz
2022 — conf
MetaFS: Model-driven Fault Simulation Framework.
DFT
Endri Kaja, Nicolas Gerlin, Monideep Bora, Keerthikumara Devarajegowda, Dominik Stoffel, Wolfgang Kunz, Wolfgang Ecker
2022 A conf
The Scale4Edge RISC-V Ecosystem.
DATE
Wolfgang Ecker, Peer Adelt, Wolfgang Müller, Reinhold Heckmann, Milos Krstic, Vladimir Herdt, Rolf Drechsler, Gerhard Angst, Ralf Wimmer, Andreas Mauderer, Rafael Stahl, Karsten Emrich, Daniel Mueller-Gritschneder, Bernd Becker, Philipp Scholl, Eyck Jentzsch, Jan Schlamelcher, Kim Grüttner, Paul Palomero Bernardo, Oliver Bringmann, Mihaela Damian, Julian Oppermann, Andreas Koch, Jörg Bormann, Johannes Partzsch, Christian Mayr, Wolfgang Kunz
2022 A* conf
Towards a formally verified hardware root-of-trust for data-oblivious computing.
DAC
Lucas Deutschmann, Johannes Müller, Mohammad Rahmani Fadiheh, Dominik Stoffel, Wolfgang Kunz
2021 A* conf
A Formal Approach to Confidentiality Verification in SoCs at the Register Transfer Level.
DAC
Johannes Müller, Mohammad Rahmani Fadiheh, Anna Lena Duque Antón, Thomas Eisenbarth, Dominik Stoffel, Wolfgang Kunz
2021 J jnl
An Exhaustive Approach to Detecting Transient Execution Side Channels in RTL Designs of Processors.
CoRR
Mohammad Rahmani Fadiheh, Alex Wezel, Johannes Müller, Jörg Bormann, Sayak Ray, Jason M. Fung, Subhasish Mitra, Dominik Stoffel, Wolfgang Kunz
2021 A conf
Compositional Fault Propagation Analysis in Embedded Systems using Abstract Interpretation.
ITC
Christian Bartsch, Stephan Wilhelm, Daniel Kästner, Dominik Stoffel, Wolfgang Kunz
2021 J jnl
Effective Pre-Silicon Verification of Processor Cores by Breaking the Bounds of Symbolic Quick Error Detection.
CoRR
Karthik Ganesan, Florian Lonsing, Srinivasa Shashank Nuthakki, Eshan Singh, Mohammad Rahmani Fadiheh, Wolfgang Kunz, Dominik Stoffel, Clark W. Barrett, Subhasish Mitra
2021 A conf
Nano Security: From Nano-Electronics to Secure Systems.
DATE
Ilia Polian, Frank Altmann, Tolga Arul, Christian Boit, Ralf Brederlow, Lucas Davi, Rolf Drechsler, Nan Du, Thomas Eisenbarth, Tim Güneysu, Sascha Hermann, Matthias Hiller, Rainer Leupers, Farhad Merchant, Thomas Mussenbrock, Stefan Katzenbeisser, Akash Kumar, Wolfgang Kunz, Thomas Mikolajick, Vivek Pachauri, Jean-Pierre Seifert, Frank Sill Torres, Jens Trommer
2020 A* conf
A Formal Approach for Detecting Vulnerabilities to Transient Execution Attacks in Out-of-Order Processors.
DAC
Mohammad Rahmani Fadiheh, Johannes Müller, Raik Brinkmann, Subhasish Mitra, Dominik Stoffel, Wolfgang Kunz
2020 — conf
Area Estimation Framework for Digital Hardware Design using Machine Learning.
MBMV
Jens Froemmer, Yara Gowayed, Nico Bannow, Wolfgang Kunz, Christoph Grimm, Klaus Schneider
2020 C conf
Automatic State Space Analysis for Modeling Untrusted Embedded Device Drivers.
DSD
Thomas Fehmel, Viet-Tan Nguyen, Dominik Stoffel, Wolfgang Kunz
2020 J jnl
Efficient Binary-Level Coverage Analysis.
CoRR
M. Ammar Ben Khadra, Dominik Stoffel, Wolfgang Kunz
2020 — conf
Efficient binary-level coverage analysis.
ESEC/SIGSOFT FSE
M. Ammar Ben Khadra, Dominik Stoffel, Wolfgang Kunz
2020 A conf
Gap-free Processor Verification by S
DATE
Keerthikumara Devarajegowda, Mohammad Rahmani Fadiheh, Eshan Singh, Clark W. Barrett, Subhasish Mitra, Wolfgang Ecker, Dominik Stoffel, Wolfgang Kunz
2020 J jnl
Generation of Abstract Driver Models for IP Integration Verification.
IEEE Trans. Emerg. Top. Comput.
Thomas Fehmel, Dominik Stoffel, Wolfgang Kunz
2020 J jnl
Properties First - Correct-By-Construction RTL Design in System-Level Design Flows.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Tobias Ludwig, Joakim Urdahl, Dominik Stoffel, Wolfgang Kunz
2019 A* conf
ACCESS: HW/SW Co-Equivalence Checking for Firmware Optimization.
DAC
Michael Schwarz, Raphael Stahl, Daniel Müller-Gritschneder, Ulf Schlichtmann, Dominik Stoffel, Wolfgang Kunz
2019 — conf
ACCESS: HW/SW-Co-Equivalence Checking for Firmware Optimization.
MBMV
Michael Schwarz, Dominik Stoffel, Wolfgang Kunz
2019 J jnl
Exploiting Hardware Unobservability for Low-Power Design and Safety Analysis in Formal Verification-Driven Design Flows.
IEEE Trans. Very Large Scale Integr. Syst.
Shrinidhi Udupi, Joakim Urdahl, Dominik Stoffel, Wolfgang Kunz
2019 — conf
How to Keep 4-Eyes Principle in a Design and Property Generation Flow.
MBMV
Keerthikumara Devarajegowda, Wolfgang Ecker, Wolfgang Kunz
2019 A conf
Processor Hardware Security Vulnerabilities and their Detection by Unique Program Execution Checking.
DATE
Mohammad Rahmani Fadiheh, Dominik Stoffel, Clark W. Barrett, Subhasish Mitra, Wolfgang Kunz
2019 A conf
Symbolic QED Pre-silicon Verification for Automotive Microcontroller Cores: Industrial Case Study.
DATE
Eshan Singh, Keerthikumara Devarajegowda, Sebastian Simon, Ralf Schnieder, Karthik Ganesan, Mohammad Rahmani Fadiheh, Dominik Stoffel, Wolfgang Kunz, Clark W. Barrett, Wolfgang Ecker, Subhasish Mitra
2019 J jnl
Symbolic QED Pre-silicon Verification for Automotive Microcontroller Cores: Industrial Case Study.
CoRR
Eshan Singh, Keerthikumara Devarajegowda, Sebastian Simon, Ralf Schnieder, Karthik Ganesan, Mohammad Rahmani Fadiheh, Dominik Stoffel, Wolfgang Kunz, Clark W. Barrett, Wolfgang Ecker, Subhasish Mitra
2019 C conf
Systematic RISC-V based Firmware Design
FDL
Vladimir Herdt, Daniel Große, Rolf Drechsler, Christoph Gerum, Alexander Louis-Ferdinand Jung, Joscha Benz, Oliver Bringmann, Michael Schwarz, Dominik Stoffel, Wolfgang Kunz
2018 J jnl
Processor Hardware Security Vulnerabilities and their Detection by Unique Program Execution Checking.
CoRR
Mohammad Rahmani Fadiheh, Dominik Stoffel, Clark W. Barrett, Subhasish Mitra, Wolfgang Kunz
2018 A conf
Symbolic quick error detection using symbolic initial state for pre-silicon verification.
DATE
Mohammad Rahmani Fadiheh, Joakim Urdahl, Srinivasa Shashank Nuthakki, Subhasish Mitra, Clark W. Barrett, Dominik Stoffel, Wolfgang Kunz
2017 J jnl
A HW/SW Cross-Layer Approach for Determining Application-Redundant Hardware Faults in Embedded Systems.
J. Electron. Test.
Christian Bartsch, Carlos Villarraga, Dominik Stoffel, Wolfgang Kunz
2017 C conf
Cycle-accurate software modeling for RTL verification of embedded systems.
DDECS
Michael Schwarz, Carlos Villarraga, Dominik Stoffel, Wolfgang Kunz
2017 Misc conf
Dynamic Power Optimization Based on Formal Property Checking of Operations.
VLSID
Shrinidhi Udupi, Joakim Urdahl, Dominik Stoffel, Wolfgang Kunz
2017 — conf
Dynamic Power Optimization based on Formal Property Checking of Operations.
MBMV
Shrinidhi Udupi, Joakim Urdahl, Dominik Stoffel, Wolfgang Kunz
2017 Misc conf
Special session on early life failures.
VTS
Jyotirmoy V. Deshmukh, Wolfgang Kunz, Hans-Joachim Wunderlich, Sybille Hellebrand
2017 — conf
Speculative disassembly of binary code.
MBMV
M. Ammar Ben Khadra, Dominik Stoffel, Wolfgang Kunz
2017 B conf
goSAT: Floating-point satisfiability as global optimization.
FMCAD
M. Ammar Ben Khadra, Dominik Stoffel, Wolfgang Kunz
2016 — conf
A HW-dependent Software Model for Cross-Layer Fault Analysis in Embedded Systems.
MBMV
Christian Bartsch, Nico Rödel, Carlos Villarraga, Dominik Stoffel, Wolfgang Kunz
2016 — conf
A HW-dependent software model for cross-layer fault analysis in embedded systems.
LATS
Christian Bartsch, Nico Rödel, Carlos Villarraga, Dominik Stoffel, Wolfgang Kunz
2016 C conf
A computer-algebraic approach to formal verification of data-centric low-level software.
MEMOCODE
Oliver Marx, Carlos Villarraga, Dominik Stoffel, Wolfgang Kunz
2016 A conf
Properties first? a new design methodology for hardware, and its perspectives in safety analysis.
ICCAD
Joakim Urdahl, Shrinidhi Udupi, Tobias Ludwig, Dominik Stoffel, Wolfgang Kunz
2016 — conf
Safety across the HW/SW interface - Can formal methods meet the challenge?
ISIC
Christian Bartsch, Carlos Villarraga, Dominik Stoffel, Wolfgang Kunz
2016 Misc conf
Speculative disassembly of binary code.
CASES
M. Ammar Ben Khadra, Dominik Stoffel, Wolfgang Kunz
2016 — conf
The European Masters in Embedded Computing Systems (EMECS).
EWME
Mark Zwolinski, Wolfgang Kunz, Kjetil Svarstad, Andrew D. Brown
2015 — conf
Architectural System Modeling for Correct-by-Construction RTL Design.
MBMV
Joakim Urdahl, Dominik Stoffel, Wolfgang Kunz
2015 C conf
Architectural system modeling for correct-by-construction RTL design.
FDL
Joakim Urdahl, Dominik Stoffel, Wolfgang Kunz
2014 C conf
A property language for the specification of hardware-dependent embedded system software.
FDL
Binghao Bao, Carlos Villarraga, Bernard Schmidt, Dominik Stoffel, Wolfgang Kunz
2014 — conf
Coverage of compositional property sets under reactive constraints.
ISQED
Binghao Bao, Jörg Bormann, Markus Wedler, Dominik Stoffel, Wolfgang Kunz
2014 — conf
Efficient SAT/simulation-based model generation for low-level embedded software.
MBMV
Christian Bartsch, Carlos Villarraga, Bernard Schmidt, Dominik Stoffel, Wolfgang Kunz
2014 J jnl
Path Predicate Abstraction for Sound System-Level Models of RT-Level Circuit Designs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Joakim Urdahl, Dominik Stoffel, Wolfgang Kunz
2014 A conf
Software in a hardware view: New models for HW-dependent software in SoC verification and test.
ITC
Carlos Villarraga, Bernard Schmidt, Binghao Bao, Rakesh Raman, Christian Bartsch, Thomas Fehmel, Dominik Stoffel, Wolfgang Kunz
2014 — conf
T4B: Formal verification in system-on-chip design: Scientific foundations and practical methodology.
SoCC
Wolfgang Kunz, Dominik Stoffel, Joakim Urdahl
2013 — conf
A Hardware-Dependent Model for SAT-based Verification of Interrupt-Driven Low-level Embedded System Software.
MBMV
Bernard Schmidt, Carlos Villarraga, Thomas Fehmel, Dominik Stoffel, Wolfgang Kunz, Jörg Bormann
2013 J jnl
A New Formal Verification Approach for Hardware-dependent Embedded System Software.
IPSJ Trans. Syst. LSI Des. Methodol.
Bernard Schmidt, Carlos Villarraga, Thomas Fehmel, Jörg Bormann, Markus Wedler, Minh D. Nguyen, Dominik Stoffel, Wolfgang Kunz
2013 — conf
A computational model for SAT-based verification of hardware-dependent low-level embedded system software.
ASP-DAC
Bernard Schmidt, Carlos Villarraga, Jörg Bormann, Dominik Stoffel, Markus Wedler, Wolfgang Kunz
2013 C conf
An equivalence checker for hardware-dependent embedded system software.
MEMOCODE
Carlos Villarraga, Bernard Schmidt, Jörg Bormann, Christian Bartsch, Dominik Stoffel, Wolfgang Kunz
2013 — conf
Compositional Completeness over reactive Constraints.
MBMV
Binghao Bao, Jörg Bormann, Markus Wedler, Dominik Stoffel, Wolfgang Kunz
2013 — conf
Environmental Information System and Odour Monitoring based on Citizen and Technology Innovative Sensors.
EnviroInfo
Philippe Ledent, Bernard Stevenot, Julien Delva, Wolfgang Kunz, Anne-Claude Romain, Ulrich Uhrner, Philippe Valoggia, Yannick Arnaud, Arnaud De Groof, Virginie Hutsemekers, Giovanna Grosso, Laurence Johannsen
2013 — conf
Formal system-on-chip verification: An operation-based methodology and its perspectives in low power design.
PATMOS
Joakim Urdahl, Shrinidhi Udupi, Dominik Stoffel, Wolfgang Kunz
2013 — conf
Proof Logging for Computer Algebra based SMT Solving.
MBMV
Oliver Marx, Markus Wedler, Dominik Stoffel, Wolfgang Kunz, Alexander Dreyer
2013 A conf
Proof logging for computer algebra based SMT solving.
ICCAD
Oliver Marx, Markus Wedler, Dominik Stoffel, Wolfgang Kunz, Alexander Dreyer
2012 — conf
Formal Plausibility Checks for Environment Constraints.
FDL (Selected Papers)
Binghao Bao, Jörg Bormann, Markus Wedler, Dominik Stoffel, Wolfgang Kunz
2012 C conf
Formal plausibility checks for environment constraints.
FDL
Binghao Bao, Jörg Bormann, Markus Wedler, Dominik Stoffel, Wolfgang Kunz
2012 A* conf
System verification of concurrent RTL modules by compositional path predicate abstraction.
DAC
Joakim Urdahl, Dominik Stoffel, Markus Wedler, Wolfgang Kunz
2011 — conf
Formal Hardware/Software Co-Verification by Interval Property Checking with Abstraction.
MBMV
Minh D. Nguyen, Markus Wedler, Bernard Schmidt, Dominik Stoffel, Wolfgang Kunz
2011 A* conf
Formal hardware/software co-verification by interval property checking with abstraction.
DAC
Minh D. Nguyen, Markus Wedler, Dominik Stoffel, Wolfgang Kunz
2011 — conf
STABLE: A new QF-BV SMT Solver for hard Verification Problems combining Boolean Reasoning with Computer Algebra.
MBMV
Evgeny Pavlenko, Markus Wedler, Dominik Stoffel, Wolfgang Kunz, Alexander Dreyer, Frank Seelisch, Gert-Martin Greuel
2011 A conf
STABLE: A new QF-BV SMT solver for hard verification problems combining Boolean reasoning with computer algebra.
DATE
Evgeny Pavlenko, Markus Wedler, Dominik Stoffel, Wolfgang Kunz, Alexander Dreyer, Frank Seelisch, Gert-Martin Greuel
2011 C conf
Validation of channel decoding ASIPs a case study.
International Symposium on Rapid System Prototyping
Christian Brehm, Norbert Wehn, Sacha Loitz, Wolfgang Kunz
2010 A* conf
Analyzing
DAC
Max Thalmaier, Minh D. Nguyen, Markus Wedler, Dominik Stoffel, Jörg Bormann, Wolfgang Kunz
2010 — conf
Analyzing k-step induction to compute invariants for SAT-based property checking.
MBMV
Max Thalmaier, Minh D. Nguyen, Markus Wedler, Dominik Stoffel, Wolfgang Kunz
2010 C conf
Complete Verification of Weakly Programmable IPs against Their Operational ISA Model.
FDL
Sacha Loitz, Markus Wedler, Dominik Stoffel, Christian Brehm, Norbert Wehn, Wolfgang Kunz
2010 B conf
Path predicate abstraction by complete interval property checking.
FMCAD
Joakim Urdahl, Dominik Stoffel, Jörg Bormann, Markus Wedler, Wolfgang Kunz
2009 — conf
A Re-Use Methodology for SoC Protocol Compliance Verification.
MBMV
Minh D. Nguyen, Max Thalmaier, Markus Wedler, Dominik Stoffel, Wolfgang Kunz
2009 C conf
A re-use methodology for formal SoC protocol compliance verification.
FDL
Minh D. Nguyen, Max Thalmaier, Markus Wedler, Dominik Stoffel, Wolfgang Kunz, Jörg Bormann
2009 — conf
Solving hard instances in QF-BV combining Boolean reasoning with computer algebra.
Algorithms and Applications for Next Generation SAT Solvers
Markus Wedler, Evgeny Pavlenko, Alexander Dreyer, Frank Seelisch, Dominik Stoffel, Gert-Martin Greuel, Wolfgang Kunz
2008 — conf
A New Verification Technique for Custom-Designed Components at the Arithmetic Bit Level.
FDL (Selected Papers)
Evgeny Pavlenko, Markus Wedler, Dominik Stoffel, Wolfgang Kunz, Oliver Wienand, Evgeny Karibaev
2008 A* conf
An Algebraic Approach for Proving Data Correctness in Arithmetic Data Paths.
CAV
Oliver Wienand, Markus Wedler, Dominik Stoffel, Wolfgang Kunz, Gert-Martin Greuel
2008 C conf
Modeling of Custom-Designed Arithmetic Components for ABL Normalization.
FDL
Evgeny Pavlenko, Markus Wedler, Dominik Stoffel, Wolfgang Kunz, Oliver Wienand, Evgeny Karibaev
2008 — conf
Modeling of Custom-Designed Arithmetic Components for ABL Normalization.
MBMV
Evgeny Pavlenko, Markus Wedler, Dominik Stoffel, Wolfgang Kunz, Oliver Wienand, Evgeny Karibaev
2008 — conf
Proving Functional Correctness of Weakly Programmable IPs - A Case Study with Formal Property Checking.
SASP
Sacha Loitz, Markus Wedler, Christian Brehm, Timo Vogt, Norbert Wehn, Wolfgang Kunz
2008 J jnl
Unbounded Protocol Compliance Verification Using Interval Property Checking With Invariants.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Minh D. Nguyen, Max Thalmaier, Markus Wedler, Jörg Bormann, Dominik Stoffel, Wolfgang Kunz
2008 — conf
Verifying full-custom multipliers by Boolean equivalence checking and an arithmetic bit level proof.
ASP-DAC
Udo Krautz, Markus Wedler, Wolfgang Kunz, Kai Weber, Christian Jacobi, Matthias Pflanz
2007 J jnl
A Normalization Method for Arithmetic Data-Path Verification.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Markus Wedler, Dominik Stoffel, Raik Brinkmann, Wolfgang Kunz
2007 — conf
Arithmetic Constraints in SAT-based Property Checking.
MBMV
Evgeny Pavlenko, Markus Wedler, Dominik Stoffel, Wolfgang Kunz
2007 — conf
Methoden zur Verifikation von Kommunikationsstrukturen.
MBMV
Martin Braun, Minh D. Nguyen, Hans Eveking, Martin Schickel, Wolfgang Kunz
2006 — conf
A case study on applying bounded model checking to analog circuit verification.
MBMV
Alexander Jesser, Markus Wedler, Lars Hedrich, Wolfgang Kunz
2005 — conf
Enhancing BMC-based Protocol Verification Using Transition-By-Transition FSM Traversal.
GI Jahrestagung (1)
Minh D. Nguyen, Dominik Stoffel, Wolfgang Kunz
2005 A* conf
Normalization at the arithmetic bit level.
DAC
Markus Wedler, Dominik Stoffel, Wolfgang Kunz
2005 A conf
Transition-by-transition FSM traversal for reachability analysis in bounded model checking.
ICCAD
Minh D. Nguyen, Dominik Stoffel, Markus Wedler, Wolfgang Kunz
2004 A conf
Arithmetic Reasoning in DPLL-Based SAT Solving.
DATE
Markus Wedler, Dominik Stoffel, Wolfgang Kunz
2004 J jnl
Equivalence checking of arithmetic circuits on the arithmetic bit level.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Dominik Stoffel, Wolfgang Kunz
2004 — conf
Exploiting state encoding for invariant generation in induction-based property checking.
ASP-DAC
Markus Wedler, Dominik Stoffel, Wolfgang Kunz
2004 C conf
Layout Driven Optimization of Datapath Circuits using Arithmetic Reasoning.
ICCD
Ingmar Neumann, Dominik Stoffel, Kolja Sulimma, Michel R. C. M. Berkelaar, Wolfgang Kunz
2004 — conf
Layout Driven Optimization of Datapath Circuits using Arithmetic Reasoning.
MBMV
Ingmar Neumann, Dominik Stoffel, Kolja Sulimma, Michel R. C. M. Berkelaar, Wolfgang Kunz
2004 — ed.
Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), Kaiserslautern, Germany, February 24-25, 2004
MBMV
Dominik Stoffel, Wolfgang Kunz
2004 J jnl
Structural FSM traversal.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Dominik Stoffel, Markus Wedler, Peter Warkentin, Wolfgang Kunz
2003 J jnl
Layout driven retiming using the coupled edge timing model.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Ingmar Neumann, Wolfgang Kunz
2003 — conf
Towards the impact of state encoding on induction-based property checking.
MBMV
Markus Wedler, Dominik Stoffel, Wolfgang Kunz
2003 A conf
Using RTL Statespace Information and State Encoding for Induction Based Property Checking.
DATE
Markus Wedler, Dominik Stoffel, Wolfgang Kunz
2002 — conf
Accelerating Retiming Under the Coupled-Edge Timing Model.
ISVLSI
Ingmar Neumann, Kolja Sulimma, Wolfgang Kunz
2002 A conf
Improving Placement under the Constant Delay Model.
DATE
Kolja Sulimma, Wolfgang Kunz, Ingmar Neumann, Lukas P. P. P. van Ginneken
2002 — conf
Improving Placement under the Constant Delay Model.
MBMV
Kolja Sulimma, Ingmar Neumann, Lukas P. P. P. van Ginneken, Wolfgang Kunz
2002 — conf
Improving Structural FSM Traversal by Constraint-Satisfying Logic Simulation.
ISVLSI
Markus Wedler, Dominik Stoffel, Wolfgang Kunz
2002 A conf
SAT and ATPG: Boolean engines for formal hardware verification.
ICCAD
Armin Biere, Wolfgang Kunz
2001 — conf
An exact algorithm for solving difficult detailed routing problems.
ISPD
Kolja Sulimma, Wolfgang Kunz
2001 — conf
Cycle time optimization by timing driven placement with simultaneous netlist transformations.
ISCAS (5)
Hendrik Hartje, Ingmar Neumann, Dominik Stoffel, Wolfgang Kunz
2001 — conf
Performance Optimization during Placement by Retiming.
MBMV (2)
Ingmar Neumann, Wolfgang Kunz
2001 A conf
Placement Driven Retiming with a Coupled Edge Timing Model.
ICCAD
Ingmar Neumann, Wolfgang Kunz
2001 — conf
Tight coupling of timing-driven placement and retiming.
ISCAS (5)
Ingmar Neumann, Wolfgang Kunz
2001 A conf
Verification of Integer Multipliers on the Arithmetic Bit Level.
ICCAD
Dominik Stoffel, Wolfgang Kunz
2001 J jnl
Äquivalenzvergleich mit strukturellen Methoden (Equivalence Checking using Structural Methods).
Informationstechnik Tech. Inform.
Wolfgang Kunz, Dominik Stoffel
1999 B conf
Accelerating Boolean Implications with FPGAs.
FPL
Kolja Sulimma, Dominik Stoffel, Wolfgang Kunz
1999 A conf
Cell replication and redundancy elimination during placement for cycle time optimization.
ICCAD
Ingmar Neumann, Dominik Stoffel, Hendrik Hartje, Wolfgang Kunz
1998 J jnl
LOT: Logic Optimization with Testability. New transformations for logic synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Mitrajit Chatterjee, Dhiraj K. Pradhan, Wolfgang Kunz
1997 — conf
AND/OR reasoning graphs for determining prime implicants in multi-level combinational networks.
ASP-DAC
Dominik Stoffel, Wolfgang Kunz, Stefan Gerber
1997 J jnl
Logic optimization and equivalence checking by implication analysis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Wolfgang Kunz, Dominik Stoffel, Prem R. Menon
1997 — book
Reasoning in Boolean Networks - Logic Synthesis and Verification Using Testing Techniques.
Wolfgang Kunz, Dominik Stoffel
1997 A conf
Record & play: a structural fixed point iteration for sequential circuit verification.
ICCAD
Dominik Stoffel, Wolfgang Kunz
1996 J jnl
A novel framework for logic verification in a synthesis environment.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Wolfgang Kunz, Dhiraj K. Pradhan, Sudhakar M. Reddy
1996 A conf
Gate-level synthesis for low-power using new transformations.
ISLPED
Dhiraj K. Pradhan, Mitrajit Chatterjee, Madhu V. Swarna, Wolfgang Kunz
1995 A conf
LOT: logic optimization with testability-new transformations using recursive learning.
ICCAD
Mitrajit Chatterjee, Dhiraj K. Pradhan, Wolfgang Kunz
1995 A* conf
Novel Verification Framework Combining Structural and OBDD Methods in a Synthesis Environment.
DAC
Subodh M. Reddy, Wolfgang Kunz, Dhiraj K. Pradhan
1994 A conf
Multi-level logic optimization by implication analysis.
ICCAD
Wolfgang Kunz, Prem R. Menon
1994 J jnl
Recursive learning: a new implication technique for efficient solutions to CAD problems-test, verification, and optimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Wolfgang Kunz, Dhiraj K. Pradhan
1993 J jnl
Accelerated dynamic learning for test pattern generation in combinational circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Wolfgang Kunz, Dhiraj K. Pradhan
1993 A conf
HANNIBAL: an efficient tool for logic verification based on recursive learning.
ICCAD
Wolfgang Kunz
1992 A conf
Recursive Learning: An Attractive Alternative to the Decision Tree for Test Genration in Digital Circuits.
ITC
Wolfgang Kunz, Dhiraj K. Pradhan
1992 — —
Rekursives Lernen: eine präzise Implikationsprozedur und ihre Anwendung auf die Testmustergenerierung in digitalen Schaltungen.
Wolfgang Kunz