| Year | Rank | Type | Title / Venue / Authors |
|---|---|---|---|
| 2009 | Misc | conf |
CODES+ISSS
|
| 2008 | — | — |
|
| 2007 | C | conf |
FDL
|
| 2007 | Misc | conf |
CODES+ISSS
|
| 2007 | C | conf |
FDL
|
| 2007 | J | jnl |
CoRR
|
| 2007 | C | conf |
FDL
|
| 2006 | C | conf |
FDL
|
| 2006 | A* | conf |
DAC
|
| 2006 | A | conf |
TRAIN: a virtual transaction layer architecture for TLM-based HW/SW codesign of synthesizable MPSoC.
DATE
|
| 2005 | — | conf |
FPT
|
| 2005 | A | conf |
DATE
|