Wolfgang Günther

56 papers A* 2A 5C 5Misc 3Journal 14Unranked 26
YearRankTypeTitle / Venue / Authors
2006 J jnl
Orthogonal Hypergraph Drawing for Improved Visibility.
J. Graph Algorithms Appl.
Thomas Eschbach, Wolfgang Günther, Bernd Becker
2005 J jnl
Combining ordered best-first search with branch and bound for exact BDD minimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Rüdiger Ebendt, Wolfgang Günther, Rolf Drechsler
2005 Misc conf
Orthogonal Circuit Visualization Improved by Merging the Placement and Routing Phases.
VLSI Design
Thomas Eschbach, Wolfgang Günther, Bernd Becker
2004 — conf
Combining ordered best-first search with branch and bound for exact BDD minimization.
ASP-DAC
Rüdiger Ebendt, Wolfgang Günther, Rolf Drechsler
2004 — conf
Efficient (Non-)Reachability Analysis of Counterexamples.
MBMV
Rolf Drechsler, Wolfgang Günther, Burkhard Stubert
2004 — conf
Minimization of the expected path length in BDDs based on local changes.
ASP-DAC
Rüdiger Ebendt, Wolfgang Günther, Rolf Drechsler
2004 — conf
Orthogonal hypergraph routing for improved visibility.
ACM Great Lakes Symposium on VLSI
Thomas Eschbach, Wolfgang Günther, Bernd Becker
2004 — conf
Some Common Synthesis-Simulation-Mismatches.
MBMV
Wolfgang Günther, Stefan Höreth
2003 J jnl
An improved branch and bound algorithm for exact BDD minimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Rüdiger Ebendt, Wolfgang Günther, Rolf Drechsler
2003 A conf
Combination of Lower Bounds in Exact BDD Minimization.
DATE
Rüdiger Ebendt, Wolfgang Günther, Rolf Drechsler
2003 — conf
Cross Reduction for Orthogonal Circuit Visualization.
VLSI
Thomas Eschbach, Wolfgang Günther, Bernd Becker
2003 J jnl
Efficient Minimization and Manipulation of Linearly Transformed Binary Decision Diagrams.
IEEE Trans. Computers
Wolfgang Günther, Rolf Drechsler
2003 J jnl
Pattern-based verification of connections to intellectual property cores.
Integr.
Ilia Polian, Wolfgang Günther, Bernd Becker
2003 J jnl
Recursive bi-partitioning of netlists for large number of partitions.
J. Syst. Archit.
Rolf Drechsler, Wolfgang Günther, Thomas Eschbach, Lothar Linhard, Gerhard Angst
2003 — conf
The Case for 2-POF.
MBMV
Ilia Polian, Wolfgang Günther, Bernd Becker
2002 A conf
Crossing Reduction by Windows Optimization.
GD
Thomas Eschbach, Wolfgang Günther, Rolf Drechsler, Bernd Becker
2002 J jnl
Logic Circuit Equivalence Checking Using Haar Spectral Coefficients and Partial BDDs.
VLSI Design
Mitchell A. Thornton, Rolf Drechsler, Wolfgang Günther
2002 J jnl
Minimization of Word-Level Decision Diagrams.
Integr.
Rolf Drechsler, Wolfgang Günther, Stefan Höreth
2002 J jnl
Minimization of free BDDs.
Integr.
Wolfgang Günther, Rolf Drechsler
2002 C conf
Recursive Bi-Partitioning of Netlists for Large Number of Partitions.
DSD
Rolf Drechsler, Wolfgang Günther, Thomas Eschbach, Lothar Linhard, Gerhard Angst
2001 — conf
Application of linearly transformed BDDs in sequential verification.
ASP-DAC
Wolfgang Günther, Andreas Hett, Bernd Becker
2001 — conf
Efficient Pattern-Based Verification of Connections to IP Cores .
Asian Test Symposium
Ilia Polian, Wolfgang Günther, Bernd Becker
2001 — conf
Efficient Pattern-Based Verification of Connections to Intellectual Property Cores.
MBMV (1)
Ilia Polian, Wolfgang Günther, Bernd Becker
2001 C conf
Greedy_IIP: Partitioning Large Graphs by Greedy Iterative Improvement.
DSD
Bernd Becker, Thomas Eschbach, Rolf Drechsler, Wolfgang Günther
2001 J jnl
History-based dynamic BDD minimization.
Integr.
Rolf Drechsler, Wolfgang Günther
2001 Misc conf
Implementation of Read- k-times BDDs on Top of Standard BDD Packages.
VLSI Design
Wolfgang Günther, Rolf Drechsler
2001 C conf
Level Assignment for Displaying Combinational Logic.
DSD
Rolf Drechsler, Wolfgang Günther, Lothar Linhard, Gerhard Angst
2001 — —
Minimierung von Entscheidungsdiagrammen und Anwendungen im Schaltkreisentwurf.
Wolfgang Günther
2001 Misc conf
Performance Driven Optimization for MUX based FPGAs.
VLSI Design
Wolfgang Günther, Rolf Drechsler
2001 — conf
Selection of Efficient Re-Ordering Heuristics for MDD Construction.
ISMVL
Frank Schmiedle, Wolfgang Günther, Rolf Drechsler
2001 J jnl
Using lower bounds during dynamic BDD minimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Rolf Drechsler, Wolfgang Günther, Fabio Somenzi
2000 — conf
A Method for Approximate Equivalence Checking.
ISMVL
Mitchell A. Thornton, Rolf Drechsler, Wolfgang Günther
2000 — conf
ACTion: Combining Logic Synthesis and Technology Mapping for MUX Based FPGAs.
EUROMICRO
Wolfgang Günther, Rolf Drechsler
2000 J jnl
ACTion: Combining logic synthesis and technology mapping for MUX-based FPGAs.
J. Syst. Archit.
Wolfgang Günther, Rolf Drechsler
2000 — conf
Dynamic Re-Encoding During MDD Minimization.
ISMVL
Frank Schmiedle, Wolfgang Günther, Rolf Drechsler
2000 C conf
Efficient Dynamic Minimization of Word-Level DDs Based on Lower Bound Computation.
ICCD
Wolfgang Günther, Rolf Drechsler, Stefan Höreth
2000 A conf
Evolutionary Synthesis of Multiplexor Circuits under Hardware Constraints.
GECCO
Rolf Drechsler, Wolfgang Günther
2000 J jnl
Fast exact minimization of BDD's.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Rolf Drechsler, Nicole Drechsler, Wolfgang Günther
2000 A conf
Improving EAs for Sequencing Problems.
GECCO
Wolfgang Günther, Rolf Drechsler
2000 — conf
Lower Bound Sifting for MDDs.
ISMVL
Dragan Jankovic, Wolfgang Günther, Rolf Drechsler
2000 J jnl
On the computational power of linearly transformed BDDs.
Inf. Process. Lett.
Wolfgang Günther, Rolf Drechsler
2000 C conf
Optimization of sequential verification by history-based dynamic minimization of BDDs.
ISCAS
Rolf Drechsler, Wolfgang Günther
2000 — conf
Testability of Circuits Derived from Lattice Diagrams.
EUROMICRO
Rolf Drechsler, Wolfgang Günther, Bernd Becker
2000 — conf
Testability of Circuits Derived from Lattice Diagrams.
LATW
Rolf Drechsler, Wolfgang Günther, Bernd Becker
2000 — conf
Verification of Designs Containing Black Boxes.
EUROMICRO
Wolfgang Günther, Nicole Drechsler, Rolf Drechsler, Bernd Becker
2000 — conf
Verification of Designs Containing Black Boxes.
MBMV
Wolfgang Günther, Nicole Drechsler, Rolf Drechsler, Bernd Becker
1999 — conf
Creating hard problem instances in logic synthesis using exact minimization.
ISCAS (6)
Wolfgang Günther, Rolf Drechsler
1999 — conf
Efficient Graph Coloring by Evolutionary Algorithms.
Fuzzy Days
Nicole Drechsler, Wolfgang Günther, Rolf Drechsler
1999 A conf
Efficient manipulation algorithms for linearly transformed BDDs.
ICCAD
Wolfgang Günther, Rolf Drechsler
1999 — conf
Generation of Optimal Universal Logic Modules.
EUROMICRO
Rolf Drechsler, Wolfgang Günther
1999 — conf
History-Based Dynamic Minimization During BDD Construction.
VLSI
Rolf Drechsler, Wolfgang Günther
1999 — conf
Minimization of BDDs using linear transformations based on evolutionary techniques.
ISCAS (1)
Wolfgang Günther, Rolf Drechsler
1999 — conf
Minimization of Free BDDs.
ASP-DAC
Wolfgang Günther, Rolf Drechsler
1999 A* conf
Using Lower Bounds During Dynamic BDD Minimization.
DAC
Rolf Drechsler, Wolfgang Günther
1998 A* conf
Fast Exact Minimization of BDDs.
DAC
Rolf Drechsler, Nicole Drechsler, Wolfgang Günther
1998 — conf
Linear Transformations and Exact Minimization of BDDs.
Great Lakes Symposium on VLSI
Wolfgang Günther, Rolf Drechsler