Wolfgang Ecker

159 papers A* 8A 21C 32Misc 6Journal 17Unranked 74

Year	Rank	Type	Title / Venue / Authors
2025	C	`conf`	Energy-Efficient Neural Network Inference through Golomb-Rice Compression of Activations for Edge Devices. DDECS Mounika Vaddeboina, Alper Yilmazer, Wolfgang Ecker
2025	—	`conf`	Execute Your Darlings: Dynamic Execution of High-Level Formal Specifications for Validation and Early Prototyping. RAPIDO@HiPEAC Robert Kunzelmann, Zeyad Tahoun, Wolfgang Ecker
2025	J	`jnl`	Exploring Hardware-Efficient Architectures of Golomb-Rice Decoder for TinyML Applications. J. Circuits Syst. Comput. Mounika Vaddeboina, Alper Yilmazer, Wolfgang Ecker
2025	Misc	`conf`	FPUGen: A FrameWork to Generate Custom Floating Point FMA Accelerators on FPGAs. VLSID Himanshu Rai, Aishwarya Sridhar, Wolfgang Ecker, Nanditha Rao
2025	C	`conf`	Implementation of Dynamic SISD-SIMD Integer Dividers. DDECS Gianluca Radi, Ares Tahiraga, Robert Kunzelmann, Ties Jan Henderikus Kluter, Wolfgang Ecker
2025	C	`conf`	Leveraging Model-Driven Architecture for Efficient Custom Instruction Utilization in Embedded Systems in C and Rust. FDL Raphael Kunz, Mayuri Bhadra, Lijun Chen, Stephanie Ecker, Wolfgang Ecker
2025	—	`conf`	Moving from RTL- to Handshake-based IP-Design: A RISC-V Case Study. MECO Natalie Simson, Paritosh Kumar Sinha, Wolfgang Ecker
2025	A	`conf`	Multi-Partner Project: Advancing the EDA Tools Landscape for the European RISC-V Ecosystem in TRISTAN. DATE Fatma Jebali, Caaliph Andriamisaina, Mathieu Jan, Wolfgang Ecker, Florian Egert, Bernhard Fischer, Alessio Burrello, Daniele Jahier Pagliari, Sara Vinco, Giuseppe Tagliavini, Ingo Feldner, Andreas Mauderer, Axel Sauer, Arnór Kristmundsson, Alexander Schober, Téo Bernier, Matti Käyrä, Ulf Schlichtmann, Rocco Jonack
2025	—	`conf`	Optimizing Software Self-Test Pattern Generation for Specific Components. DFT Jad Al Halabi, Melis Cetinkaya, Endri Kaja, Mounika Vaddeboina, Wolfgang Ecker
2025	—	`conf`	Target-Aware Automated RTL Generation for RISC-V SoC Designs: A Model-Driven Approach. ICECS Mohamed Badawy, Jiulong Wang, Paritosh Kumar Sinha, Wolfgang Ecker
2025	—	`conf`	Unifying IP Specification Through Formal Hardware Function Sets: An Industrial Case Study. MCSoC Robert Kunzelmann, Maximilian Berger, Vinod Bangalore Ganesh, Rachana R. Pai, Wolfgang Ecker
2024	A	`conf`	A Scalable RISC-V Hardware Platform for Intelligent Sensor Processing. DATE Paul Palomero Bernardo, Patrick Schmid, Oliver Bringmann, Mohammed Iftekhar, Babak Sadiye, Wolfgang Müller, Andreas Koch, Eyck Jentzsch, Axel Sauer, Ingo Feldner, Wolfgang Ecker
2024	—	`conf`	An Automated Exhaustive Fault Analysis Technique guided by Processor Formal Verification Methods. ISQED Endri Kaja, Nicolas Gerlin, Bihan Zhao, Daniela Sanchez Lopera, Jad Al Halabi, Azam Sher Khan, Sebastian Prebeck, Dominik Stoffel, Wolfgang Kunz, Wolfgang Ecker
2024	—	`conf`	An Automated and Effective Approach for SBST Generation Targeting RISC-V CPUs. DFT Endri Kaja, Nicolas Gerlin, Jad Al Halabi, Ares Tahiraga, Sebastian Prebeck, Dominik Stoffel, Wolfgang Kunz, Wolfgang Ecker
2024	—	`conf`	Automated Intrinsic Support for ISA Extensions: Enhancing Software Generation for RISC-V and Beyond. NorCAS Mayuri Bhadra, Stephanie Ecker, Daniel Albert, Ravindra Ramaiah, Sebastian Prebeck, Wolfgang Ecker
2024	—	`conf`	Fake Timer: An Engine for Accurate Timing Estimation in Register Transfer Level Designs. ISQED Daniela Sanchez Lopera, Robert Kunzelmann, Endri Kaja, Wolfgang Ecker
2024	—	`conf`	Leveraging Large Language Models for the Automated Documentation of Hardware Designs. MECO Saruni Fernando, Robert Kunzelmann, Daniela Sanchez Lopera, Jad Al Halabi, Wolfgang Ecker
2024	C	`conf`	Optimizing Data Compression: Enhanced Golomb-Rice Encoding with Parallel Decoding Strategies for TinyML Models. DSD Mounika Vaddeboina, Alper Yilmayer, Wolfgang Ecker
2024	C	`conf`	PaGoRi:A Scalable Parallel Golomb-Rice Decoder. DDECS Mounika Vaddeboina, Endri Kaja, Alper Yilmazer, Uttal Ghosh, Wolfgang Ecker
2024	—	`conf`	Special Session: A Mixed Simulation-, Emulation-, and Formal-Based Fault Analysis Methodology for RISC-V. DFT Endri Kaja, Nicolas Gerlin, Ares Tahiraga, Jad Al Halabi, Sebastian Prebeck, Dominik Stoffel, Wolfgang Kunz, Wolfgang Ecker
2024	J	`jnl`	The Argument for Meta-Modeling-Based Approaches to Hardware Generation Languages. CoRR Johannes Schreiner, Daniel Gerl, Robert Kunzelmann, Paritosh Kumar Sinha, Wolfgang Ecker
2023	J	`jnl`	A Comprehensive Survey on Electronic Design Automation and Graph Neural Networks: Theory and Applications. ACM Trans. Design Autom. Electr. Syst. Daniela Sánchez, Lorenzo Servadei, Gamze Naz Kiprit, Robert Wille, Wolfgang Ecker
2023	C	`conf`	Bits, Flips and RISCs. DDECS Nicolas Gerlin, Endri Kaja, Fabian Vargas, Li Lu, Anselm Breitenreiter, Junchao Chen, Markus Ulbricht, Maribel Gomez, Ares Tahiraga, Sebastian Prebeck, Eyck Jentzsch, Milos Krstic, Wolfgang Ecker
2023	J	`jnl`	Deep Reinforcement Learning for Optimization at Early Design Stages. IEEE Des. Test Lorenzo Servadei, Jin Hwa Lee, José Antonio Arjona-Medina, Michael Werner, Sepp Hochreiter, Wolfgang Ecker, Robert Wille
2023	—	`conf`	Effective Processor Model Generation from Instruction Set Simulator to Hardware Design. NorCAS Johannes Kappes, Robert Kunzelmann, Karsten Emrich, Conrad Foik, Daniel Mueller-Gritschneder, Wolfgang Ecker
2023	—	`conf`	FPGA-Implementation Techniques to Efficiently Test Application Readiness of Mixed-Signal Products. VLSI-SoC (Selected Papers) Gabriel Rutsch, Konrad Maier, Wolfgang Ecker
2023	C	`conf`	FPGA-implementation techniques to efficiently test application readiness of mixed-signal products. VLSI-SoC Gabriel Rutsch, Konrad Maier, Wolfgang Ecker
2023	A*	`conf`	G-QED: Generalized QED Pre-silicon Verification beyond Non-Interfering Hardware Accelerators. DAC Saranyu Chattopadhyay, Keerthikumara Devarajegowda, Bihan Zhao, Florian Lonsing, Brandon A. D'Agostino, Ioanna Vavelidou, Vijay Deep Bhatt, Sebastian Prebeck, Wolfgang Ecker, Caroline Trippel, Clark W. Barrett, Subhasish Mitra
2023	—	`conf`	Generator IP-reuse and Automated Infrastructure Generation for Model-based Full-Chip Generation. MBMV Johannes Schreiner, Vasundhara Raje Gontia, Sebastian Prebeck, Wolfgang Ecker
2023	—	`conf`	Modelling Peripheral Designs using FSM-like Notation for Complete Property Set Generation. MCSoC Endri Kaja, Nicolas Gerlin, Robert Kunzelmann, Keerthikumara Devarajegowda, Wolfgang Ecker
2023	C	`conf`	Parallel Golomb-Rice Decoder with 8-bit Unary Decoding for Weight Compression in TinyML Applications. DSD Mounika Vaddeboina, Endri Kaja, Alper Yilmayer, Sebastian Prebeck, Wolfgang Ecker
2023	Misc	`conf`	Special Session: Machine Learning for Embedded System Design. CODES+ISSS Erika S. Alcorta, Andreas Gerstlauer, Chenhui Deng, Qi Sun, Zhiru Zhang, Ceyu Xu, Lisa Wu Wills, Daniela Sanchez Lopera, Wolfgang Ecker, Siddharth Garg, Jiang Hu
2023	—	`conf`	Using Graph Neural Networks for Timing Estimations of RTL Intermediate Representations. MLCAD Daniela Sanchez Lopera, Ishwor Subedi, Wolfgang Ecker
2022	—	`conf`	A Scalable, Configurable and Programmable Vector Dot-Product Unit for Edge AI. MBMV Sebastian Prebeck, Sathya Ashok, Mounika Vaddeboina, Keerthikumara Devarajegowda, Wolfgang Ecker
2022	—	`conf`	A Smart HW-Accelerator for Non-uniform Linear Interpolation of ML-Activation Functions. SAMOS Sebastian Siegfried Prebeck, Wafic Lawand, Mounika Vaddeboina, Wolfgang Ecker
2022	C	`conf`	A framework that enables systematic analysis of mixed-signal applications on FPGA. RSP Gabriel Rutsch, Maximilian Groebner, Anthony Sanders, Konrad Maier, Wolfgang Ecker
2022	J	`jnl`	Accurate and Robust Malware Detection: Running XGBoost on Runtime Data From Performance Counters. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Rana Elnaggar, Lorenzo Servadei, Shubham Mathur, Robert Wille, Wolfgang Ecker, Krishnendu Chakrabarty
2022	J	`jnl`	An Open-Source Framework for FPGA Emulation of Analog/Mixed-Signal Integrated Circuit Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Steven Herbst, Gabriel Rutsch, Wolfgang Ecker, Mark Horowitz
2022	A	`conf`	Applying GNNs to Timing Estimation at RTL. ICCAD Daniela Sanchez Lopera, Wolfgang Ecker
2022	C	`conf`	Design of a Tightly-Coupled RISC-V Physical Memory Protection Unit for Online Error Detection. VLSI-SoC Nicolas Gerlin, Endri Kaja, Monideep Bora, Keerthikumara Devarajegowda, Dominik Stoffel, Wolfgang Kunz, Wolfgang Ecker
2022	J	`jnl`	Early RTL delay prediction using neural networks. Microprocess. Microsystems Daniela Sanchez Lopera, Lorenzo Servadei, Sebastian Siegfried Prebeck, Wolfgang Ecker
2022	C	`conf`	Fast and Accurate Model-Driven FPGA-based System-Level Fault Emulation. VLSI-SoC Endri Kaja, Nicolas Gerlin, Monideep Bora, Gabriel Rutsch, Keerthikumara Devarajegowda, Dominik Stoffel, Wolfgang Kunz, Wolfgang Ecker
2022	—	`conf`	Industrial Experience with Open-Source EDA Tools. MLCAD Christian Lück, Daniela Sanchez Lopera, Sven Wenzek, Wolfgang Ecker
2022	J	`jnl`	MetFI: Model-driven Fault Simulation Framework. CoRR Endri Kaja, Nicolas Gerlin, Luis Rivas, Monideep Bora, Keerthikumara Devarajegowda, Wolfgang Ecker
2022	—	`conf`	MetaFS: Model-driven Fault Simulation Framework. DFT Endri Kaja, Nicolas Gerlin, Monideep Bora, Keerthikumara Devarajegowda, Dominik Stoffel, Wolfgang Kunz, Wolfgang Ecker
2022	A	`conf`	The Scale4Edge RISC-V Ecosystem. DATE Wolfgang Ecker, Peer Adelt, Wolfgang Müller, Reinhold Heckmann, Milos Krstic, Vladimir Herdt, Rolf Drechsler, Gerhard Angst, Ralf Wimmer, Andreas Mauderer, Rafael Stahl, Karsten Emrich, Daniel Mueller-Gritschneder, Bernd Becker, Philipp Scholl, Eyck Jentzsch, Jan Schlamelcher, Kim Grüttner, Paul Palomero Bernardo, Oliver Bringmann, Mihaela Damian, Julian Oppermann, Andreas Koch, Jörg Bormann, Johannes Partzsch, Christian Mayr, Wolfgang Kunz
2021	—	`conf`	A Survey of Graph Neural Networks for Electronic Design Automation. MLCAD Daniela Sanchez Lopera, Lorenzo Servadei, Gamze Naz Kiprit, Souvik Hazra, Robert Wille, Wolfgang Ecker
2021	C	`conf`	Aspect-Oriented Design Automation with Model Transformation. VLSI-SoC Zhao Han, Deyan Wang, Gabriel Rutsch, Bowen Li, Sebastian Siegfried Prebeck, Daniela Sanchez Lopera, Keerthikumara Devarajegowda, Wolfgang Ecker
2021	Misc	`conf`	Automated HW/SW co-design for edge AI: state, challenges and steps ahead. CODES+ISSS Oliver Bringmann, Wolfgang Ecker, Ingo Feldner, Adrian Frischknecht, Christoph Gerum, Timo Hämäläinen, Muhammad Abdullah Hanif, Michael J. Klaiber, Daniel Mueller-Gritschneder, Paul Palomero Bernardo, Sebastian Siegfried Prebeck, Muhammad Shafique
2021	—	`conf`	Extending Verilator to Enable Fault Simulation. MBMV Endri Kaja, Nicolas Ojeda Leon, Michael Werner, Bogdan-Andrei Tabacaru, Keerthikumara Devarajegowda, Wolfgang Ecker
2021	A*	`conf`	ISA Modeling with Trace Notation for Context Free Property Generation. DAC Keerthikumara Devarajegowda, Endri Kaja, Sebastian Siegfried Prebeck, Wolfgang Ecker
2021	—	`conf`	On Self-Verifying DSL Generation for Embedded Systems Automation. MBMV Zhao Han, Shahzaib Qazi, Michael Werner, Keerthikumara Devarajegowda, Wolfgang Ecker
2021	—	`conf`	RTL Delay Prediction Using Neural Networks. NorCAS Daniela Sanchez Lopera, Lorenzo Servadei, Vishwa Priyanka Kasi, Sebastian Siegfried Prebeck, Wolfgang Ecker
2021	—	`conf`	Towards Fault Simulation at Mixed Register-Transfer/Gate-Level Models. DFT Endri Kaja, Nicolas Gerlin, Mounika Vaddeboina, Luis Rivas, Sebastian Siegfried Prebeck, Zhao Han, Keerthikumara Devarajegowda, Wolfgang Ecker
2021	—	`conf`	Transformative Hardware Design Following the Model-Driven Architecture Vision. VLSI-SoC (Selected Papers) Zhao Han, Gabriel Rutsch, Deyan Wang, Bowen Li, Sebastian Siegfried Prebeck, Daniela Sanchez Lopera, Keerthikumara Devarajegowda, Wolfgang Ecker
2020	J	`jnl`	Accurate Cost Estimation of Memory Systems Utilizing Machine Learning and Solutions from Computer Vision for Design Automation. IEEE Trans. Computers Lorenzo Servadei, Edoardo Mosca, Elena Zennaro, Keerthikumara Devarajegowda, Michael Werner, Wolfgang Ecker, Robert Wille
2020	—	`conf`	Automatic compiler optimization on embedded software through k-means clustering. MLCAD Michael Werner, Lorenzo Servadei, Robert Wille, Wolfgang Ecker
2020	—	`conf`	Cost Estimation for Configurable Model-Driven SoC Designs Using Machine Learning. ACM Great Lakes Symposium on VLSI Lorenzo Servadei, Edoardo Mosca, Keerthikumara Devarajegowda, Michael Werner, Wolfgang Ecker, Robert Wille
2020	—	`conf`	Cost Optimization at Early Stages of Design Using Deep Reinforcement Learning. MLCAD Lorenzo Servadei, Jiapeng Zheng, Jose A. Arjona-Medina, Michael Werner, Volkan Esen, Sepp Hochreiter, Wolfgang Ecker, Robert Wille
2020	A	`conf`	Gap-free Processor Verification by S DATE Keerthikumara Devarajegowda, Mohammad Rahmani Fadiheh, Eshan Singh, Clark W. Barrett, Subhasish Mitra, Wolfgang Ecker, Dominik Stoffel, Wolfgang Kunz
2020	C	`conf`	Kamel: IP-XACT compatible intermediate meta-model for IP generation. DSD Antti Rautakoura, Matti Käyrä, Timo D. Hämäläinen, Wolfgang Ecker, Esko Pekkarinen, Mikko Teuho
2020	C	`conf`	Optimized HW/FW Generation from an Abstract Register Interface Model. DSD Michael Werner, Igli Zeraliu, Zhao Han, Sebastian Siegfried Prebeck, Lorenzo Servadei, Wolfgang Ecker
2020	—	`conf`	SoC Design Automation with ML - It's Time for Research. MLCAD Vijay Deep Bhatt, Wolfgang Ecker, Volkan Esen, Zhao Han, Daniela Sanchez Lopera, Rituj Patel, Lorenzo Servadei, Sahil Singla, Sven Wenzek, Vijaydeep Yadav, Elena Zennaro
2019	A	`conf`	Accurate Cost Estimation of Memory Systems Inspired by Machine Learning for Computer Vision. DATE Lorenzo Servadei, Elena Zennaro, Keerthikumara Devarajegowda, Martin Manzinger, Wolfgang Ecker, Robert Wille
2019	A	`conf`	Embedded Systems' Automation following OMG's Model Driven Architecture Vision. DATE Wolfgang Ecker, Keerthikumara Devarajegowda, Michael Werner, Zhao Han, Lorenzo Servadei
2019	C	`conf`	Formal Verification Methodology in an Industrial Setup. DSD Lorenzo Servadei, Zhao Han, Michael Werner, Wolfgang Ecker, Keerthikumara Devarajegowda
2019	—	`conf`	How to Keep 4-Eyes Principle in a Design and Property Generation Flow. MBMV Keerthikumara Devarajegowda, Wolfgang Ecker, Wolfgang Kunz
2019	A*	`conf`	Increasing Soft Error Resilience by Software Transformation. DAC Michael Werner, Keerthikumara Devarajegowda, Moomen Chaari, Wolfgang Ecker
2019	A	`conf`	Symbolic QED Pre-silicon Verification for Automotive Microcontroller Cores: Industrial Case Study. DATE Eshan Singh, Keerthikumara Devarajegowda, Sebastian Simon, Ralf Schnieder, Karthik Ganesan, Mohammad Rahmani Fadiheh, Dominik Stoffel, Wolfgang Kunz, Clark W. Barrett, Wolfgang Ecker, Subhasish Mitra
2019	J	`jnl`	Symbolic QED Pre-silicon Verification for Automotive Microcontroller Cores: Industrial Case Study. CoRR Eshan Singh, Keerthikumara Devarajegowda, Sebastian Simon, Ralf Schnieder, Karthik Ganesan, Mohammad Rahmani Fadiheh, Dominik Stoffel, Wolfgang Kunz, Clark W. Barrett, Wolfgang Ecker, Subhasish Mitra
2019	—	`conf`	Towards a Python-Based One Language Ecosystem for Embedded Systems Automation. NORCAS Zhao Han, Keerthikumara Devarajegowda, Michael Werner, Wolfgang Ecker
2019	J	`jnl`	Using Machine Learning for predicting area and Firmware metrics of hardware designs from abstract specifications. Microprocess. Microsystems Lorenzo Servadei, Elena Zennaro, Tobias Fritz, Keerthikumara Devarajegowda, Wolfgang Ecker, Robert Wille
2018	C	`conf`	A Machine Learning Approach for Area Prediction of Hardware Designs from Abstract Specifications. DSD Elena Zennaro, Lorenzo Servadei, Keerthikumara Devarajegowda, Wolfgang Ecker
2018	—	`conf`	Analog fault simulation automation at schematic level with random sampling techniques. DTIS Liang Wu, Mohammad Khizer Hussain, Saed Abughannam, Wolfgang Müller, Christoph Scheytt, Wolfgang Ecker
2018	C	`conf`	Meta-model Based Automation of Properties for Pre-Silicon Verification. VLSI-SoC Keerthikumara Devarajegowda, Wolfgang Ecker
2018	—	`conf`	Quality Assessment of Generated Hardware Designs Using Statistical Analysis and Machine Learning. CIMA@ICTAI Lorenzo Servadei, Elena Zennaro, Keerthikumara Devarajegowda, Wolfgang Ecker, Robert Wille
2017	—	`ch.`	Metamodeling and Code Generation in the Hardware/Software Interface Domain. Handbook of Hardware/Software Codesign Wolfgang Ecker, Johannes Schreiner
2017	—	`conf`	On generation of properties from specification. HLDVT Keerthikumara Devarajegowda, Wolfgang Ecker
2017	A	`conf`	Python based framework for HDSLs with an underlying formal semantics: (Invited paper). ICCAD Keerthikumara Devarajegowda, Johannes Schreiner, Rainer Findenig, Wolfgang Ecker
2017	C	`conf`	The extendable translating instruction set simulator (ETISS) interlinked with an MDA framework for fast RISC prototyping. RSP Daniel Mueller-Gritschneder, Keerthikumara Devarajegowda, Martin Dittrich, Wolfgang Ecker, Marc Greim, Ulf Schlichtmann
2016	C	`conf`	Automatically comparing analog behavior using Earth Mover's Distance. VLSI-SoC Alexander W. Rath, Sebastian Simon, Volkan Esen, Wolfgang Ecker
2016	—	`conf`	Design centric modeling of digital hardware. HLDVT Johannes Schreiner, Rainer Findenig, Wolfgang Ecker
2016	—	`conf`	Digital Hardware Design Based on Metamodels and Model Transformations. VLSI-SoC (Selected Papers) Johannes Schreiner, Wolfgang Ecker
2016	—	`conf`	Earth Mover's Distance as a Comparison Metric for Analog Behavior. VLSI-SoC (Selected Papers) Alexander W. Rath, Sebastian Simon, Volkan Esen, Wolfgang Ecker
2016	C	`conf`	Efficient Checkpointing-Based Safety-Verification Flow Using Compiled-Code Simulation. DSD Bogdan-Andrei Tabacaru, Moomen Chaari, Wolfgang Ecker, Thomas Kruse, Cristiano Novello
2016	C	`conf`	Efficient handling of the fault space in functional safety analysis utilizing formal methods. VLSI-SoC Alessandro Bernardini, Wolfgang Ecker, Ulf Schlichtmann
2016	C	`conf`	Fault-effect analysis on system-level hardware modeling using virtual prototypes. FDL Bogdan-Andrei Tabacaru, Moomen Chaari, Wolfgang Ecker, Thomas Kruse, Cristiano Novello
2016	—	`conf`	Gate-Level-Accurate Fault-Effect Analysis at Virtual-Prototype Speed. SAFECOMP Workshops Bogdan-Andrei Tabacaru, Moomen Chaari, Wolfgang Ecker, Thomas Kruse, Cristiano Novello
2016	C	`conf`	Introducing Model-of-Things (MoT) and Model-of-Design (MoD) for simpler and more efficient hardware generators. VLSI-SoC Wolfgang Ecker, Johannes Schreiner
2016	C	`conf`	Speeding up safety verification by fault abstraction and simulation to transaction level. VLSI-SoC Bogdan-Andrei Tabacaru, Moomen Chaari, Wolfgang Ecker, Thomas Kruse, Cristiano Novello
2016	—	`conf`	Transformation of Failure Propagation Models into Fault Trees for Safety Evaluation Purposes. DSN Workshops Moomen Chaari, Wolfgang Ecker, Thomas Kruse, Cristiano Novello, Bogdan-Andrei Tabacaru
2016	A	`conf`	Where formal verification can help in functional safety analysis. ICCAD Alessandro Bernardini, Wolfgang Ecker, Ulf Schlichtmann
2015	A*	`conf`	A model-based and simulation-assisted FMEDA approach for safety-relevant E/E systems. DAC Moomen Chaari, Wolfgang Ecker, Cristiano Novello, Bogdan-Andrei Tabacaru, Thomas Kruse
2015	A	`conf`	The next generation of virtual prototyping: ultra-fast yet accurate simulation of HW/SW systems. DATE Oliver Bringmann, Wolfgang Ecker, Andreas Gerstlauer, Ajay Goyal, Daniel Mueller-Gritschneder, Prasanth Sasidharan, Simranjit Singh
2014	—	`conf`	A transaction-oriented UVM-based library for verification of analog behavior. ASP-DAC Alexander W. Rath, Volkan Esen, Wolfgang Ecker
2014	A*	`conf`	Metasynthesis for Designing Automotive SoCs. DAC Wolfgang Ecker, Michael Velten, Leily Zafari, Ajay Goyal
2014	A*	`conf`	Safety Evaluation of Automotive Electronics Using Virtual Prototypes: State of the Art and Research Challenges. DAC Jan-Hendrik Oetjens, Nico Bannow, Markus Becker, Oliver Bringmann, Andreas Burger, Moomen Chaari, Samarjit Chakraborty, Rolf Drechsler, Wolfgang Ecker, Kim Grüttner, Thomas Kruse, Christoph Kuznik, Hoang Minh Le, Andreas Mauderer, Wolfgang Müller, Daniel Müller-Gritschneder, Frank Poppen, Hendrik Post, Sebastian Reiter, Wolfgang Rosenstiel, S. Roth, Ulf Schlichtmann, Andreas von Schwerin, Bogdan-Andrei Tabacaru, Alexander Viehl
2014	A	`conf`	The metamodeling approach to system level synthesis. DATE Wolfgang Ecker, Michael Velten, Leily Zafari, Ajay Goyal
2013	—	`conf`	Comparison of analog transactions using statistics. ISSoC Alexander W. Rath, Volkan Esen, Wolfgang Ecker
2013	—	`conf`	The semantic of the power intent format UPF: Consistent power modeling from system level to implementation. PATMOS Juergen Karmann, Wolfgang Ecker
2013	—	`conf`	Transaction-Level Modeling and Refinement Using State Charts. EUROCAST (1) Rainer Findenig, Thomas Leitner, Wolfgang Ecker
2012	—	`conf`	Single-source hardware modeling of different abstraction levels with State Charts. HLDVT Rainer Findenig, Thomas Leitner, Wolfgang Ecker
2012	Misc	`conf`	SystemC as completing pillar in industrial OVM based verification environments. CODES+ISSS Wolfgang Ecker, Volkan Esen, Michael Velten, Tudor Timisescu
2012	Misc	`conf`	Testbenches for advanced TLM verification. CODES+ISSS Wolfgang Müller, Wolfgang Ecker
2012	Misc	`conf`	The system verification methodology for advanced TLM verification. CODES+ISSS Marcio Ferreira da Silva Oliveira, Christoph Kuznik, Hoang Minh Le, Daniel Große, Finn Haedicke, Wolfgang Müller, Rolf Drechsler, Wolfgang Ecker, Volkan Esen
2011	—	`conf`	Analog transaction level modeling. HLDVT Alexander W. Rath, Volkan Esen, Wolfgang Ecker
2010	—	`conf`	Fast and accurate UML State Chart modeling using TLM HLDVT Rainer Findenig, Thomas Leitner, Michael Velten, Wolfgang Ecker
2010	—	`conf`	Model reduction techniques for the formal verification of hardware dependent software. HLDVT Wolfgang Ecker, Volkan Esen, Rainer Findenig, Thomas Steininger, Michael Velten
2010	A	`conf`	Panel Session - Who Is Closing the embedded software design gap? DATE Wolfgang Ecker, Pierre Bricaud, Rainer Dömer, Yossi Veller, Stefan Heinen, Jürgen Mössinger, Andreas von Schwerin
2010	—	`conf`	State chart refinement validation from approximately timed to cycle callable models. SoC Rainer Findenig, Wolfgang Ecker
2010	A	`conf`	TLM+ modeling of embedded HW/SW systems. DATE Wolfgang Ecker, Volkan Esen, Robert Schwencker, Thomas Steininger, Michael Velten
2009	—	`conf`	Using a dataflow abstracted virtual prototype for HdS-design. ASP-DAC Wolfgang Ecker, Stefan Heinen, Michael Velten
2008	A	`conf`	Industrial IP Integration Flows based on IP-XACT Standards. DATE Wido Kruijtzer, Pieter van der Wolf, Erwin A. de Kock, Jan Stuyt, Wolfgang Ecker, Albrecht Mayer, Serge Hustin, Christophe Amerijckx, Serge De Paoli, Emmanuel Vaumorin
2007	A	`conf`	Interactive presentation: Impact of description language, abstraction layer, and value representation on simulation performance. DATE Wolfgang Ecker, Volkan Esen, Lars Schönberg, Thomas Steininger, Michael Velten, Michael Hull
2007	A	`conf`	Interactive presentation: Implementation of a transaction level assertion framework in SystemC. DATE Wolfgang Ecker, Volkan Esen, Thomas Steininger, Michael Velten, Michael Hull
2007	—	`conf`	Requirements and Concepts for Transaction Level Assertion Refinement. IESS Wolfgang Ecker, Volkan Esen, Thomas Steininger, Michael Velten
2006	C	`conf`	Case Study on Transaction Level Modeling. FDL Wolfgang Ecker, Volkan Esen, Thomas Steininger, Michael Velten
2006	C	`conf`	Execution semantics and formalisms for multi-abstraction TLM assertions. MEMOCODE Wolfgang Ecker, Volkan Esen, Michael Hull
2006	C	`conf`	IP Library For Temporal SystemC Assertions. FDL Wolfgang Ecker, Volkan Esen, Thomas Steininger, Michael Velten, Jacob Smit
2006	C	`conf`	Requirements and Concepts for Transaction Level Assertions. ICCD Wolfgang Ecker, Volkan Esen, Michael Hull, Thomas Steininger, Michael Velten
2006	—	`conf`	Specification Language for Transaction Level Assertions. HLDVT Wolfgang Ecker, Volkan Esen, Thomas Steininger, Michael Velten, Michael Hull
2005	—	`conf`	Evolution of Paradigm Shifts in the Automated Design Process of Digital Circuits. GI Jahrestagung (1) Wolfgang Ecker, Lothar Schrader
2004	J	`jnl`	A Layered Adaptive Verification Platform for Simulation, Test, and Emulation. IEEE Des. Test Comput. Martin Zambaldi, Wolfgang Ecker, Renate Henftling, Matthias Bauer
2004	—	`conf`	Ein orthogonales Schema für die Klassifikation der Modellierungsabstraktion von digitalen Systemen. MBMV Martin Zambaldi, Wolfgang Ecker
2004	C	`conf`	Extending the RASSP model for Verification. FDL Martin Zambaldi, Wolfgang Ecker
2004	A	`conf`	How to Bridge the Gap Between Simulationand Test. ITC Martin Zambaldi, Wolfgang Ecker
2004	C	`conf`	Memory Models for the Formal Verification of Assembler Code Using Bounded Model Checking. ISORC Wolfgang Ecker, Volkan Esen, Thomas Steininger, Martin Zambaldi
2004	C	`conf`	SystemVerilog: Interface Based Design. FDL Peter Jensen, Wolfgang Ecker, Thomas Kruse, Martin Zambaldi
2004	C	`conf`	The Formal Simulation Semantics of SystemVerilog. FDL Martin Zambaldi, Wolfgang Ecker, Thomas Kruse, Wolfgang Müller
2003	A	`conf`	An Approach for Mixed Coarse-Granular and Fine-Granular Re-Configurable Architectures. IPDPS Renate Henftling, Wolfgang Ecker, Andreas Zinn, Martin Zambaldi, Matthias Bauer
2003	—	`conf`	An Enhanced Environment for Multi-Level Simulation. MBMV Martin Zambaldi, Matthias Bauer, Wolfgang Ecker, Renate Henftling, Andreas Zinn
2003	—	`conf`	Incremental Design: A VHDL based Case Study. MBMV Fanny Garnier, Wolfgang Ecker
2003	A	`conf`	Platform-Based Testbench Generation. DATE Renate Henftling, Andreas Zinn, Matthias Bauer, Wolfgang Ecker, Martin Zambaldi
2003	A*	`conf`	Re-use-centric architecture for a fully accelerated testbench environment. DAC Renate Henftling, Andreas Zinn, Matthias Bauer, Martin Zambaldi, Wolfgang Ecker
2002	J	`jnl`	Verifikation und Wiederverwendung (Verification and Re-Use). Informationstechnik Tech. Inform. Matthias Bauer, Wolfgang Ecker, Renate Henftling, Martin Zambaldi, Andreas Zinn
2001	—	`conf`	Hardware-basierter Hardware-Entwurf. MBMV (1) Wolfgang Ecker
2000	—	`conf`	A JAVA-Based Mixed-Signal Design Environment. SBCCI Jochen Mades, Thomas Schneider, Manfred Glesner, André Windisch, Wolfgang Ecker
2000	—	`conf`	An Open VHDL-AMS Simulation Framework. BMAS Thomas Schneider, Jochen Mades, Manfred Glesner, André Windisch, Wolfgang Ecker
2000	J	`jnl`	Eine flexible Simulationsumgebung für System-On-Chip Design (A Flexible Simulation Environment for System-On-Chip Design). Informationstechnik Tech. Inform. André Windisch, Thomas Schneider, Jochen Mades, Dieter Monjau, Manfred Glesner, Carsten Hammer, Wolfgang Ecker
2000	—	`conf`	Graphische Spezifikation und Analyse funktionaler Testabläufe mit MSCs der UML. MBMV Matthias Bauer, Wolfgang Ecker, Andreas Zinn
2000	—	`conf`	VXML: VHDL Hardware Design Representation in XML. MBMV Wolfgang Ecker, Mike Heuchling, Jochen Mades, Thomas Schneider, André Windisch, Ke Yang
1999	—	`conf`	A Method for Accelerating Test Environments. EUROMICRO Matthias Bauer, Wolfgang Ecker, Renate Henftling, Andreas Zinn
1999	—	`conf`	A scalable multithreaded compiler front-end. PARCO André Windisch, Thomas Schneider, Ke Yang, Jochen Mades, Wolfgang Ecker
1998	J	`jnl`	Reuse-Potentiale im Hardware-Entwurf. Informationstechnik Tech. Inform. Wolfgang Ecker, Yvonne Fritzsch, Viktor Preis
1997	A*	`conf`	Hardware/Software Co-Simulation in a VHDL-Based Test Bench Approach. DAC Matthias Bauer, Wolfgang Ecker
1997	—	`conf`	The Shall-Prototype-Test Development model. ECBS Michael Mrva, Mike Heuchling, Wolfgang Ecker
1996	—	`conf`	Stepwise refinement of behavioral VHDL specifications by separation of synchronization and functionality. EURO-DAC Claus Schneider, Wolfgang Ecker
1996	J	`jnl`	VHDL synthesis description portability: The need for Level synthesis subsets. J. Syst. Archit. Manfred Selz, Wolfgang Ecker, Eugenio Villar
1996	J	`jnl`	Verification methods for VHDL RTL-subroutines. J. Syst. Archit. Wolfgang Ecker
1995	—	`conf`	A classification of design steps and their verification. EURO-DAC Wolfgang Ecker
1995	—	`conf`	Semi-dynamic scheduling of synchronization-mechanisms. EURO-DAC Wolfgang Ecker
1995	—	`conf`	VHDL-based communication and synchronization synthesis. EURO-DAC Wolfgang Ecker, Manfred Huber
1994	—	`conf`	Protocol merging: a VHDL-based method for clock cycle minimizing and protocol preserving scheduling of IO-operations. EURO-DAC Wolfgang Ecker, Manfred Glesner, Andreas Vombach
1993	A	`conf`	State look ahead technique for cycle optimization of interacting finite state Moore machines. ICCAD Wolfgang Ecker, Michael Hofmeister
1993	—	`conf`	System-Level Specification and Design Using VHDL: A Case Study. CHDL Wolfgang Ecker, Sabine März
1993	—	`conf`	Using VHDL for HW/SW co-specification. EURO-DAC Wolfgang Ecker
1992	—	`conf`	Subtype concept of VHDL for synthesis constraints. EURO-DAC Wolfgang Ecker, Sabine März
1992	—	`conf`	The design cube: a new model for VHDL designflow representation. EURO-DAC Wolfgang Ecker, Michael Hofmeister
1992	—	`conf`	Towards a common RT-level subset of VHDL. EURO-DAC Wolfgang Ecker