Wojciech Maly - RankMe

99 papers A* 8A 33C 5Misc 4Journal 26Unranked 23

Year	Rank	Type	Title / Venue / Authors
2013	—	`conf`	Designing VeSFET-based ICs with CMOS-oriented EDA infrastructure. ISPD Xiang Qiu, Malgorzata Marek-Sadowska, Wojciech Maly
2012	—	`conf`	Vertical Slit Field Effect Transistor in ultra-low power applications. ISQED Xiang Qiu, Malgorzata Marek-Sadowska, Wojciech Maly
2011	J	`jnl`	On Cell Layout-Performance Relationships in VeSFET-Based, High-Density Regular Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yi-Wei Lin, Malgorzata Marek-Sadowska, Wojciech Maly
2011	—	`conf`	Vertical slit transistor based integrated circuits (veSTICs): feasibility study. ISPD Wojciech Maly
2010	Misc	`conf`	Evaluating yield and testing impact of sub-wavelength lithography. VTS Wing Chiu Tam, R. D. (Shawn) Blanton, Wojciech Maly
2010	J	`jnl`	Layout Generator for Transistor-Level High-Density Regular Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yi-Wei Lin, Malgorzata Marek-Sadowska, Wojciech Maly
2010	—	`conf`	Performance study of VeSFET-based, high-density regular circuits. ISPD Yi-Wei Lin, Malgorzata Marek-Sadowska, Wojciech Maly
2009	C	`conf`	Adder Circuits with Transistors using Independently Controlled Gates. ISCAS Marcus Weis, Andrzej Pfitzner, Dominik Kasprowicz, Rainer Emling, Wojciech Maly, Doris Schmitt-Landsiedel
2009	—	`conf`	Transistor-level layout of high-density regular circuits. ISPD Yi-Wei Lin, Malgorzata Marek-Sadowska, Wojciech Maly
2009	—	`conf`	Vertical slit transistor based integrated circuits (VeSTICs) paradigm. ISPD Wojciech Maly
2008	C	`conf`	Is there always performance overhead for regular fabric? ICCD Yi-Wei Lin, Malgorzata Marek-Sadowska, Wojciech Maly, Andrzej Pfitzner, Dominik Kasprowicz
2008	A	`conf`	More Moore: foolish, feasible, or fundamentally different? ICCAD Rob Aitken, Jerry Bautista, Wojciech Maly, Jan M. Rabaey
2007	A*	`conf`	OPC-Free and Minimally Irregular IC Design Style. DAC Wojciech Maly, Yi-Wei Lin, Malgorzata Marek-Sadowska
2006	J	`jnl`	Extracting Defect Density and Size Distributions from Product ICs. IEEE Des. Test Comput. Jeffrey E. Nelson, Thomas Zanon, Jason G. Brown, Osei Poku, R. D. (Shawn) Blanton, Wojciech Maly, Brady Benware, Chris Schuermyer
2006	A	`conf`	Extraction of defect density and size distributions from wafer sort test results. DATE Jeffrey E. Nelson, Thomas Zanon, Rao Desineni, Jason G. Brown, N. Patil, Wojciech Maly, R. D. (Shawn) Blanton
2004	—	`conf`	2.5D system integration: a design driven system implementation schema. ASP-DAC Yangdong Steve Deng, Wojciech Maly
2004	A	`conf`	Benchmarking Diagnosis Algorithms With a Diverse Set of IC Deformations. ITC Thomas J. Vogels, Thomas Zanon, Rao Desineni, R. D. (Shawn) Blanton, Wojciech Maly, Jason G. Brown, Jeffrey E. Nelson, Y. Fei, X. Huang, Padmini Gopalakrishnan, Mahim Mishra, Vyacheslav Rovner, S. Tiwary
2003	A	`conf`	Deformations of IC Structure in Test and Yield Learning. ITC Wojciech Maly, Anne E. Gattiker, Thomas Zanon, Thomas J. Vogels, R. D. (Shawn) Blanton, Thomas M. Storey
2003	C	`conf`	Physical Design of the "2.5D" Stacked System. ICCD Yangdong Deng, Wojciech Maly
2003	A	`conf`	Progressive Bridge Identification. ITC Thomas J. Vogels, Wojciech Maly, R. D. (Shawn) Blanton
2002	A	`conf`	Fault Tuples in Diagnosis of Deep-Submicron Circuits. ITC Ronald D. Blanton, John T. Chen, Rao Desineni, Kumar N. Dwarakanath, Wojciech Maly, Thomas J. Vogels
2002	J	`jnl`	Modeling the Economics of Testing: A DFT Perspective. IEEE Des. Test Comput. Pranab K. Nag, Anne E. Gattiker, Sichao Wei, Ronald D. Blanton, Wojciech Maly
2001	Misc	`conf`	Enabling Embedded Memory Diagnosis via Test Response Compression. VTS John T. Chen, Wojciech Maly, Janusz Rajski, Omar Kebichi, Jitendra Khare
2001	A*	`conf`	IC Design in High-Cost Nanometer-Technologies Era. DAC Wojciech Maly
2001	—	`conf`	Interconnect characteristics of 2.5-D system integration scheme. ISPD Yangdong Deng, Wojciech Maly
2001	J	`jnl`	Limitations and challenges of computer-aided design technology for CMOS VLSI. Proc. IEEE Randal E. Bryant, Kwang-Ting Cheng, Andrew B. Kahng, Kurt Keutzer, Wojciech Maly, A. Richard Newton, Lawrence T. Pileggi, Jan M. Rabaey, Alberto L. Sangiovanni-Vincentelli
2001	—	`conf`	Quality of Design from an IC Manufacturing Perspective. ISQED Wojciech Maly
2001	A	`conf`	Test response compression and bitmap encoding for embedded memories in manufacturing process monitoring. ITC John T. Chen, Jitendra Khare, Ken Walker, Saghir A. Shaikh, Janusz Rajski, Wojciech Maly
2000	—	`conf`	Cost based tradeoff analysis of standard cell designs. SLIP Peng Li, Pranab K. Nag, Wojciech Maly
1999	J	`jnl`	A DRC-based algorithm for extraction of critical areas for opens in large VLSI circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Witold A. Pleskacz, Charles H. Ouyang, Wojciech Maly
1999	J	`jnl`	An algorithm for determining repetitive patterns in very large IC layouts. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Mariusz Niewczas, Wojciech Maly, Andrzej J. Strojwas
1998	—	`conf`	A pattern matching algorithm for verification and analysis of very large IC layouts. ISPD Mariusz Niewczas, Wojciech Maly, Andrzej J. Strojwas
1998	A	`conf`	Current signatures: application [to CMOS]. ITC Anne E. Gattiker, Wojciech Maly
1998	A	`conf`	Design-Manufacturing Interface: Part I - Vision. DATE Wojciech Maly, Pranab K. Nag, Hans T. Heineken, Jitendra Khare
1998	A	`conf`	Design-Manufacturing Interface: Part II - Applications. DATE Wojciech Maly, Pranab K. Nag, Charles H. Ouyang, Hans T. Heineken, Jitendra Khare, P. Simon
1998	—	`conf`	Moore's law and physical design of ICs. ISPD Wojciech Maly
1998	A	`conf`	Performance - Manufacturability Tradeoffs in IC Design. DATE Hans T. Heineken, Wojciech Maly
1998	A	`conf`	Toward understanding "Iddq-only" fails. ITC Anne E. Gattiker, Wojciech Maly
1997	J	`jnl`	Behavior and testability preservation under the retiming transformation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Aiman H. El-Maleh, Thomas E. Marchok, Janusz Rajski, Wojciech Maly
1997	A*	`conf`	CAD at the Design-Manufacturing Interface. DAC Hans T. Heineken, Jitendra Khare, Wojciech Maly, Pranab K. Nag, Charles H. Ouyang, Witold A. Pleskacz
1997	A	`conf`	Current Signatures: Application. ITC Anne E. Gattiker, Wojciech Maly
1997	—	`conf`	Detection of Yield Trends. DFT Witold A. Pleskacz, Wojciech Maly, Hans T. Heineken
1997	—	`conf`	Improved Yield Model for Submicron Domain. DFT Witold A. Pleskacz, Wojciech Maly
1997	J	`jnl`	Smart Substrate MCMs. J. Electron. Test. Anne E. Gattiker, Wojciech Maly
1997	A	`conf`	So What Is an Optimal Test Mix? A Discussion of the SEMATECH Methods Experiment. ITC Phil Nigh, Wayne M. Needham, Kenneth M. Butler, Peter C. Maxwell, Robert C. Aitken, Wojciech Maly
1997	A	`conf`	To DFT or Not to DFT? ITC Sichao Wei, Pranab K. Nag, Ronald D. Blanton, Anne E. Gattiker, Wojciech Maly
1996	J	`jnl`	A complexity analysis of sequential ATPG. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Thomas E. Marchok, Aiman H. El-Maleh, Wojciech Maly, Janusz Rajski
1996	Misc	`conf`	Current signatures [VLSI circuit testing]. VTS Anne E. Gattiker, Wojciech Maly
1996	A	`conf`	Design for manufacturability in submicron domain. ICCAD Wojciech Maly, Hans T. Heineken, Jitendra Khare, Pranab K. Nag
1996	—	`conf`	Detection of an antenna effect in VLSI designs. DFT Wojciech Maly, Charles H. Ouyang, Subhendra Ghosh, Sury Maturi
1996	—	`conf`	Extraction of critical areas for opens in large VLSI circuits. DFT Charles H. Ouyang, Witold A. Pleskacz, Wojciech Maly
1996	—	`conf`	Fatal Fault Probability Prediction for Array Based Designs. DFT Dinesh D. Gaitonde, Wojciech Maly, D. M. H. Walker
1996	Misc	`conf`	Fault characterization of standard cell libraries using inductive contamination. VTS Jitendra Khare, Wojciech Maly, Nathan Tiday
1996	A	`conf`	I ITC Thomas W. Williams, Robert H. Dennard, Rohit Kapur, M. Ray Mercer, Wojciech Maly
1996	—	`conf`	Iddq Testing for High Performance CMOS - The Next Ten Years. ED&TC Thomas W. Williams, Rohit Kapur, M. Ray Mercer, Robert H. Dennard, Wojciech Maly
1996	A	`conf`	Interconnect yield model for manufacturability prediction in synthesis of standard cell based designs. ICCAD Hans T. Heineken, Wojciech Maly
1996	C	`conf`	Modeling the Difficulty of Sequential Automatic Test Pattern Generation. ICCD Thomas E. Marchok, Wojciech Maly
1996	A	`conf`	New and Not-So-New Test Challenges of the Next Decade. ITC Wojciech Maly
1996	J	`jnl`	The future of IC design, testing, and manufacturing. IEEE Des. Test Comput. Wojciech Maly
1995	—	`conf`	AFFCCA: a tool for critical area analysis with circular defects and lithography deformed layout. DFT Igor Bubel, Wojciech Maly, Thomas Waas, Pranab K. Nag, Hans Hartmann, Doris Schmitt-Landsiedel, Susanne Griep
1995	—	`conf`	Accurate yield estimation of circuits with redundancy. DFT Dinesh D. Gaitonde, D. M. H. Walker, Wojciech Maly
1995	—	`conf`	Complexity of sequential ATPG. ED&TC Thomas E. Marchok, Aiman El-Maleh, Wojciech Maly, Janusz Rajski
1995	—	`conf`	Hierarchical extraction of critical area for shorts in very large ICs. DFT Pranab K. Nag, Wojciech Maly
1995	A	`conf`	Inductive Contamination Analysis (ICA) with SRAM Application. ITC Jitendra Khare, Wojciech Maly
1995	A*	`conf`	On Test Set Preservation of Retimed Circuits. DAC Aiman H. El-Maleh, Thomas E. Marchok, Janusz Rajski, Wojciech Maly
1995	J	`jnl`	Testability Implications of Performance-Driven Logic Synthesis. IEEE Des. Test Comput. Thomas E. Marchok, Aiman H. El-Maleh, Janusz Rajski, Wojciech Maly
1994	A*	`conf`	Cost of Silicon Viewed from VLSI Design Perspective. DAC Wojciech Maly
1994	A	`conf`	Feasibility Study of Smart Substrate Multichip Modules. ITC Anne E. Gattiker, Wojciech Maly
1994	A	`conf`	Integration of Design, Manufacturing and Testing. ITC Wojciech Maly
1994	J	`jnl`	Smart-Substrate Multichip-Module Systems. IEEE Des. Test Comput. Wojciech Maly, Derek B. I. Feltham, Anne E. Gattiker, Mark D. Hobaugh, Kenneth Backus, Michael E. Thomas
1993	J	`jnl`	Accurate estimation of defect-related yield loss in reconfigurable VLSI circuits. IEEE J. Solid State Circuits Jitendra Khare, Derek B. I. Feltham, Wojciech Maly
1993	J	`jnl`	Failure Analysis of High-Density CMOS SRAMs: Using Realistic Defect Modeling and I/Sub DDQ/ Testing. IEEE Des. Test Comput. Samir Naik, Frank Agricola, Wojciech Maly
1992	J	`jnl`	Built-in current testing. IEEE J. Solid State Circuits Wojciech Maly, Marek J. Patyra
1992	—	`conf`	Design for testability view on placement and routing. EURO-DAC Derek B. I. Feltham, Jitendra Khare, Wojciech Maly
1992	J	`jnl`	Design of ICs applying built-in current testing. J. Electron. Test. Wojciech Maly, Marek J. Patyra
1992	J	`jnl`	Prospects for WSI: A Manufacturing Perspective. Computer Wojciech Maly
1991	A	`conf`	Fault Modeling for the Testing of Mixed Integrated Circuits. ITC Anne Meixner, Wojciech Maly
1991	A	`conf`	Improving the Quality of Test Education. ITC Wojciech Maly
1991	J	`jnl`	Physically realistic fault models for analog CMOS neural networks. IEEE J. Solid State Circuits Derek B. I. Feltham, Wojciech Maly
1991	A	`conf`	Stuck Fault and Current Testing Comparison Using CMOS Chip Test. ITC Thomas M. Storey, Wojciech Maly, John Andrews, Myron Miske
1991	A*	`conf`	What is Design for Manufacturability (DFM)? (Panel Abstract). DAC Wojciech Maly
1990	A	`conf`	CMOS Bridging Fault Detection. ITC Thomas M. Storey, Wojciech Maly
1990	A	`conf`	CMOS bridging fault detection. ITC Thomas M. Storey, Wojciech Maly
1990	J	`jnl`	Computer-aided design for VLSI circuit manufacturability. Proc. IEEE Wojciech Maly
1990	A	`conf`	Current testing. ITC Wojciech Maly
1990	J	`jnl`	Test Generation for Current Testing (CMOS ICs). IEEE Des. Test Comput. Phil Nigh, Wojciech Maly
1989	A	`conf`	Layout-driven test generation. ICCAD Phil Nigh, Wojciech Maly
1989	A	`conf`	Process Monitoring Oriented IC Testing. ITC Wojciech Maly, Samir B. Naik
1988	A	`conf`	Built-in current testing-feasibility study. ICCAD Wojciech Maly, Phil Nigh
1988	C	`conf`	Current sensing for built-in testing of CMOS circuits. ICCD Derek B. I. Feltham, Phil Nigh, L. Richard Carley, Wojciech Maly
1988	A	`conf`	Testing oriented analysis of CMOS ICs with opens. ICCAD Wojciech Maly, Pranab K. Nag, Phil Nigh
1987	A*	`conf`	Realistic Fault Modeling for VLSI Testing. DAC Wojciech Maly
1986	A*	`conf`	Optimal order of the VLSI IC testing sequence. DAC Wojciech Maly
1986	J	`jnl`	VLSI Yield Prediction and Estimation: A Unified Framework. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Wojciech Maly, Andrzej J. Strojwas, Stephen W. Director
1985	J	`jnl`	Inductive Fault Analysis of MOS Integrated Circuits. IEEE Des. Test John Paul Shen, Wojciech Maly, F. Joel Ferguson
1985	J	`jnl`	Modeling of Lithography Related Yield Losses for CAD of VLSI Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Wojciech Maly
1985	J	`jnl`	Tolerance Assignment for IC Selection Tests. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Wojciech Maly, Zygmunt Pizlo
1984	A	`conf`	Systematic Characterization of Physical Defects for Fault Analysis of MOS IC Cells. ITC Wojciech Maly, F. Joel Ferguson, John Paul Shen
1982	J	`jnl`	Statistical Simulation of the IC Manufacturing Process. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Wojciech Maly, Andrzej J. Strojwas