Witold A. Pleskacz

89 papers A* 1A 1B 1C 34Journal 10Unranked 42

Year	Rank	Type	Title / Venue / Authors
2025	—	`conf`	Implementation of a PLL Loop Circuit for Frequency Synthesis in 65 nm CMOS Technology. MIXDES Magdalena Tyminska, Maciej Kucharski, Witold A. Pleskacz
2025	—	`conf`	SHA-256 Hash Generator in Verilog HDL. MIXDES Bartosz Rulka, Pawel Pienczuk, Witold A. Pleskacz
2024	—	`conf`	Bridge Circuit Converting Atomic Transactions Between AMBA AXI4 and AMBA AXI5 Standards. MIXDES Jakub Misztal, Mateusz Korona, Witold A. Pleskacz
2024	—	`conf`	Implementation of Hardware Trace Buffer Module for RISC-V Processor Core. MIXDES Bohdan Shveida, Krzysztof Marcinek, Witold A. Pleskacz
2024	C	`conf`	The Impact of Well-Edge Proximity Effect on PMOS Threshold Voltage in Various Submicron CMOS Technologies. DDECS Marika Grochowska, Witold A. Pleskacz
2023	—	`conf`	Dual TDL Based Phase Difference Detector Architecture. MIXDES Andrzej A. Wojciechowski, Krzysztof Marcinek, Witold A. Pleskacz
2022	—	`conf`	Clock Signal Phase Alignment System for Daisy Chained Integrated Circuits. MIXDES Andrzej A. Wojciechowski, Krzysztof Marcinek, Witold A. Pleskacz
2022	—	`conf`	DC/DC Buck Converter Soft-Start Methods. MIXDES Adam Borkowski, Krzysztof Siwiec, Witold A. Pleskacz
2021	—	`conf`	Class AB Operational Amplifier in CMOS 55 nm Technology. MIXDES Pawel Pienczuk, Witold A. Pleskacz, Mateusz Teodorowski
2020	C	`conf`	CMOS Differential Amplifier as a Physically Unclonable Function. DDECS Szymon Reszewicz, Krzysztof Siwiec, Witold A. Pleskacz
2020	J	`jnl`	Erratum: Borejko, T., et al. NaviSoC: High-Accuracy Low-Power GNSS SoC with an Integrated Application Processor. Sensors 2020, 20, 1069. Sensors Tomasz Borejko, Krzysztof Marcinek, Krzysztof Siwiec, Pawel Narczyk, Adam Borkowski, Igor Butryn, Arkadiusz W. Luczyk, Daniel Pietron, Maciej Plasota, Szymon Reszewicz, Lukasz Wiechowski, Witold A. Pleskacz
2020	J	`jnl`	GNSS-ISE: Instruction Set Extension for GNSS Baseband Processing. Sensors Krzysztof Marcinek, Witold A. Pleskacz
2020	J	`jnl`	NaviSoC: High-Accuracy Low-Power GNSS SoC with an Integrated Application Processor. Sensors Tomasz Borejko, Krzysztof Marcinek, Krzysztof Siwiec, Pawel Narczyk, Adam Borkowski, Igor Butryn, Arkadiusz W. Luczyk, Daniel Pietron, Maciej Plasota, Szymon Reszewicz, Lukasz Wiechowski, Witold A. Pleskacz
2019	—	`conf`	Configurable MBIST Processor for Embedded Memories Testing. MIXDES Andrzej A. Wojciechowski, Krzysztof Marcinek, Witold A. Pleskacz
2019	—	`conf`	DC/DC Buck Converter with Build-in Tuned Sawtooth Wave Generator Using CMOS Technology. MIXDES Adam Borkowski, Tomasz Borejko, Witold A. Pleskacz
2019	—	`conf`	Design and Verification Environment for RISC-V Processor Cores. MIXDES Adrian Oleksiak, Sebastian Cieslak, Krzysztof Marcinek, Witold A. Pleskacz
2019	C	`conf`	Design of a True Random Number Generator Based on Low Power Oscillator with Increased Jitter. DDECS Mariusz Derlecki, Krzysztof Siwiec, Pawel Narczyk, Witold A. Pleskacz
2019	—	`conf`	Implementation and Comparison of SPA and DPA Countermeasures for Elliptic Curve Point Multiplication. MIXDES Lukasz Ostrowski, Krzysztof Marcinek, Witold A. Pleskacz
2019	A	`conf`	International Symposium on Design and Diagnostics of Electronic Circuits and Systems. ITC Zoran Stamenkovic, Alberto Bosio, György Cserey, Ondrej Novák, Witold A. Pleskacz, Lukás Sekanina, Andreas Steininger, Goran Stojanovic, Viera Stopjaková
2019	—	`conf`	Retargeting the MIPS-II CPU Core to the RISC-V Architecture. MIXDES Sebastian Cieslak, Adrian Oleksiak, Krzysztof Marcinek, Witold A. Pleskacz
2018	C	`conf`	2.4 GHz LC-VCO with Improved Robustness against PVT Using FD-SOI Body Biasing Technique. DDECS Szymon Reszewicz, Krzysztof Siwiec, Witold A. Pleskacz
2018	—	`conf`	Design of a Wideband Low Noise Amplifier for a FMCW Synthetic Aperture Radar in 130 nm SiGe BiCMOS Technology. MIXDES Daniel Pietron, Igor Butryn, Lukasz Wiechowski, Witold A. Pleskacz
2018	J	`jnl`	Foreword to the special issue on 20th IEEE international symposium on design and diagnostics of electronic circuits and systems (DDECS2017). Microelectron. Reliab. Zoran Stamenkovic, Ondrej Novák, Witold A. Pleskacz
2018	—	`conf`	Ka Band Digitally Controlled Oscillator for FMCW Radar in 130 nm SiGe BiCMOS Technology. MIXDES Igor Butryn, Lukasz Wiechowski, Daniel Pietron, Witold A. Pleskacz
2017	C	`conf`	Analog front-end for precise human body temperature measurement. DDECS Pawel Narczyk, Krzysztof Siwiec, Witold A. Pleskacz
2017	—	`conf`	EIA/TIA-485 transceiver in standard 130 nm CMOS technology. MIXDES Michal Wysocki, Krzysztof Siwiec, Witold A. Pleskacz
2017	—	`conf`	Importance of on-chip inductor modeling in radio frequency integrated circuits. MIXDES Daniel Pietron, Tomasz Borejko, Krzysztof Siwiec, Witold A. Pleskacz
2017	—	`conf`	Principal component analysis of accelerations in human dynamic movements: A sample set length effect study. MIXDES Arkadiusz W. Luczyk, Konrad Neneman, Witold A. Pleskacz
2017	—	`conf`	Temperature calibration technique based on on-chip resistor. MIXDES Pawel Narczyk, Krzysztof Siwiec, Witold A. Pleskacz
2016	—	`conf`	A low sampling frequency switched capacitor low-pass filter for wireless receivers. MIXDES Jakub Kopanski, Lukasz Wiechowski, Krzysztof Siwiec, Witold A. Pleskacz
2016	—	`conf`	Architecture and design of a Bluetooth Low Energy Controller. MIXDES Pawel Wiecha, Marek Cieplucha, Patryk Kloczko, Witold A. Pleskacz
2016	C	`conf`	BioSoC: Highly integrated System-on-Chip for health monitoring. DDECS Krzysztof Siwiec, Krzysztof Marcinek, Piotr Boguszewicz, Tomasz Borejko, Aleh Halauko, Adam Jarosz, Jakub Kopanski, Ewa Kurjata-Pfitzner, Pawel Narczyk, Maciej Plasota, Andrzej Wielgus, Witold A. Pleskacz
2016	—	`conf`	Dedicated chip for pulse oximetry measurements. EWDTS Cezary Kolacinski, Jerzy Wasowski, Andrzej Szymanski, Adam Jarosz, Ewa Kurjata-Pfitzner, Tomasz Borejko, Krzysztof Siwiec, Witold A. Pleskacz
2016	C	`conf`	Integer-N phase locked loop for bluetooth receiver in CMOS 130 nm technology. DDECS Igor Butryn, Krzysztof Siwiec, Jakub Kopanski, Witold A. Pleskacz
2016	—	`conf`	Monitoring of dynamic movements using acceleration measurements. MIXDES Konrad Neneman, Arkadiusz W. Luczyk, Witold A. Pleskacz
2016	—	`conf`	New architecture of the object-oriented functional coverage mechanism for digital verification. IVSW Marek Cieplucha, Witold A. Pleskacz
2016	C	`conf`	Precision human body temperature measurement based on thermistor sensor. DDECS Pawel Narczyk, Krzysztof Siwiec, Witold A. Pleskacz
2016	—	`conf`	The integrated transmitter and receiver modules for pulse oximeter system. MIXDES Cezary Kolacinski, Andrzej Szymanski, Adam Jarosz, Ewa Kurjata-Pfitzner, Jerzy Wasowski, Tomasz Borejko, Krzysztof Siwiec, Witold A. Pleskacz
2015	C	`ed.`	18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2015, Belgrade, Serbia, April 22-24, 2015 DDECS Zoran Stamenkovic, Witold A. Pleskacz, Jaan Raik, Heinrich Theodor Vierhaus
2015	—	`conf`	A CMOS system-on-chip for physiological parameters acquisition, processing and monitoring. MIXDES Krzysztof Siwiec, Krzysztof Marcinek, Tomasz Borejko, Adam Jarosz, Jakub Kopanski, Ewa Kurjata-Pfitzner, Pawel Narczyk, Maciej Plasota, Andrzej Wielgus, Witold A. Pleskacz
2015	C	`conf`	A Low Ripple Current Mode Voltage Doubler. DDECS Andrzej Grodzicki, Witold A. Pleskacz
2015	—	`conf`	IF polyphase filter design and calibration with back-gate biasing in 28 nm FD-SOI technology. MIXDES Mariusz Derlecki, Tomasz Borejko, Witold A. Pleskacz
2015	C	`conf`	Implementation of the ADELITE Microcontroller for Biomedical Applications. DDECS Krzysztof Marcinek, Maciej Plasota, Andrzej Wielgus, Witold A. Pleskacz
2015	—	`conf`	Low voltage LNA implementations in 28 nm FD-SOI technology for GNSS applications. MIXDES Aleh Halauko, Tomasz Borejko, Witold A. Pleskacz
2015	C	`conf`	UVM-based Verification of Bluetooth Low Energy Controller. DDECS Maciej Moskala, Patryk Kloczko, Marek Cieplucha, Witold A. Pleskacz
2014	—	`conf`	Implementation of the Bluetooth receiver RF front-end in the CMOS-RF 130 nm technology. MIXDES Daniel Pietron, Krzysztof Siwiec, Jakub Kopanski, Witold A. Pleskacz
2014	C	`conf`	Multistage low ripple charge pump. DDECS Andrzej Grodzicki, Witold A. Pleskacz
2014	—	`conf`	Simulink model of GFSK demodulator based on time-to-digital converter. MIXDES Lukasz Wiechowski, Krzysztof Siwiec, Jakub Kopanski, Witold A. Pleskacz
2013	J	`jnl`	ELEON3LP - Superscalar and low-power enhancements of single issue general purpose processor model. Microprocess. Microsystems Krzysztof Marcinek, Witold A. Pleskacz
2013	C	`conf`	Intermediate frequency filter calibration method for radio frequency receivers in modern CMOS technologies. DDECS Krzysztof Siwiec, Aleksander Koter, Witold A. Pleskacz
2012	C	`conf`	AGATE - towards designing a low-power chip multithreading processor for mobile software defined radio systems. DDECS Krzysztof Marcinek, Witold A. Pleskacz
2012	C	`ed.`	IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2012, Tallinn, Estonia, April 18-20, 2012 DDECS Jaan Raik, Viera Stopjaková, Heinrich Theodor Vierhaus, Witold A. Pleskacz, Raimund Ubar, Helena Kruus, Maksim Jenihhin
2012	C	`conf`	LC-VCO design automation tool for nanometer CMOS technology. DDECS Krzysztof Siwiec, Tomasz Borejko, Witold A. Pleskacz
2011	C	`conf`	A 5Gb/s equalizer for USB 3.0 receiver in 65 nm CMOS technology. DDECS Jakub Kopanski, Witold A. Pleskacz, Dariusz Pienkowski
2011	C	`conf`	A resistorless current reference source for 65 nm CMOS technology with low sensitivity to process, supply voltage and temperature variations. DDECS Michal Lukaszewicz, Tomasz Borejko, Witold A. Pleskacz
2011	C	`conf`	CAD tool for PLL Design. DDECS Krzysztof Siwiec, Tomasz Borejko, Witold A. Pleskacz
2011	C	`conf`	PVT tolerant LC-VCO in 90 nm CMOS technology for GPS/Galileo applications. DDECS Krzysztof Siwiec, Tomasz Borejko, Witold A. Pleskacz
2010	C	`conf`	A comparison of low voltage LNA architectures designed for multistandard GNSS in two 90 nm CMOS technologies. DDECS Jacek Gradzki, Tomasz Borejko, Witold A. Pleskacz
2009	C	`conf`	Enhanced LEON3 core for superscalar processing. DDECS Krzysztof Marcinek, Arkadiusz W. Luczyk, Witold A. Pleskacz
2009	C	`conf`	Low voltage LNA implementations in 90 nm CMOS technology for multistandard GNSS. DDECS Jacek Gradzki, Tomasz Borejko, Witold A. Pleskacz
2009	C	`conf`	MDCT / IMDCT low power implementations in 90 nm CMOS technology for MP3 audio. DDECS Peter Malík, Michal Ufnal, Arkadiusz W. Luczyk, Marcel Baláz, Witold A. Pleskacz
2008	C	`conf`	A Resistorless Voltage Reference Source for 90 nm CMOS Technology with Low Sensitivity to Process and Temperature Variations. DDECS Tomasz Borejko, Witold A. Pleskacz
2008	C	`conf`	Built-In Current Monitor for IDDQ Testing in CMOS 90 nm Technology. DDECS Marcin J. Beresinski, Tomasz Borejko, Witold A. Pleskacz, Viera Stopjaková
2008	—	`conf`	Characterization of CMOS sequential standard cells for defect based voltage testing. EWDTS Andrzej Wielgus, Witold A. Pleskacz
2008	C	`conf`	Controllable Local Clock Signal Generator for Deep Submicron GALS Architectures. DDECS Artur L. Sobczyk, Arkadiusz W. Luczyk, Witold A. Pleskacz
2008	J	`jnl`	DefSim: A Remote Laboratory for Studying Physical Defects in CMOS Digital Circuits. IEEE Trans. Ind. Electron. Witold A. Pleskacz, Viera Stopjaková, Tomasz Borejko, Artur Jutman, Andrzej Walkanis
2008	C	`conf`	Hierarchical Analysis of Short Defects between Metal Lines in CMOS IC. DSD Witold A. Pleskacz, Maksim Jenihhin, Jaan Raik, Michal Rakowski, Raimund Ubar, Wieslaw Kuzmicz
2008	C	`conf`	Various MDCT implementations in 0.35µm CMOS. DDECS Peter Malík, Marcel Baláz, Martin Simlastík, Arkadiusz W. Luczyk, Witold A. Pleskacz
2007	C	`conf`	ESD Failures of Integrated Circuits and Their Diagnostics Using Transmission Line Pulsing. DDECS Zbigniew Piatek, Jerzy F. Kolodziejski, Witold A. Pleskacz
2007	C	`conf`	Layout to Logic Defect Analysis for Hierarchical Test Generation. DDECS Maksim Jenihhin, Jaan Raik, Raimund Ubar, Witold A. Pleskacz, Michal Rakowski
2007	C	`conf`	Power Dissipation in Basic Global Clock Distribution Networks. DDECS Artur L. Sobczyk, Arkadiusz W. Luczyk, Witold A. Pleskacz
2006	—	`conf`	DefSim: CMOS Defects on Chip for Research and Education. LATW Witold A. Pleskacz, Tomasz Borejko, Andrzej Walkanis, Viera Stopjaková, Artur Jutman, Raimund Ubar
2005	B	`conf`	DOT: new deterministic defect-oriented ATPG tool. ETS Jaan Raik, Raimund Ubar, Joachim Sudbrock, Wieslaw Kuzmicz, Witold A. Pleskacz
2005	C	`conf`	Defect-Oriented Test- and Layout-Generation for Standard-Cell ASIC Designs. DSD Joachim Sudbrock, Jaan Raik, Raimund Ubar, Wieslaw Kuzmicz, Witold A. Pleskacz
2003	J	`jnl`	Improvement of integrated circuit testing reliability by using the defect based approach. Microelectron. Reliab. Dominik Kasprowicz, Witold A. Pleskacz
2002	—	`conf`	CMOS Standard Cells Characterization for IDDQ Testing. DFT Witold A. Pleskacz, Tomasz Borejko, Wieslaw Kuzmicz
2002	J	`jnl`	Hierarchical test generation for combinational circuits with real defects coverage. Microelectron. Reliab. T. Cibáková, Mária Fischerová, Elena Gramatová, Wieslaw Kuzmicz, Witold A. Pleskacz, Jaan Raik, Raimund Ubar
2001	—	`conf`	CMOS Standard Cells Characterization for Defect Based Testing. DFT Witold A. Pleskacz, Dominik Kasprowicz, Tomasz Oleszczak, Wieslaw Kuzmicz
2001	—	`conf`	Defect-Oriented Fault Simulation and Test Generation in Digital Circuits. ISQED Wieslaw Kuzmicz, Witold A. Pleskacz, Jaan Raik, Raimund Ubar
2001	J	`jnl`	Probabilistic analysis of CMOS physical defects in VLSI circuits for test coverage improvement. Microelectron. Reliab. Mykola Blyzniuk, Irena Kazymyra, Wieslaw Kuzmicz, Witold A. Pleskacz, Jaan Raik, Raimund Ubar
2000	—	`conf`	Graphical user interface of FIESTA - software for faults identification and estimation of testability of VLSI circuits. CCU Mykola Blyzniuk, Taras Panchak, Wieslaw Kuzmicz, Witold A. Pleskacz
2000	—	`conf`	Hierarchical defect-oriented fault simulation for digital circuits. ETW Mykola Blyzniuk, T. Cibáková, Elena Gramatová, Wieslaw Kuzmicz, M. Lobur, Witold A. Pleskacz, Jaan Raik, Raimund Ubar
1999	J	`jnl`	A DRC-based algorithm for extraction of critical areas for opens in large VLSI circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Witold A. Pleskacz, Charles H. Ouyang, Wojciech Maly
1999	—	`conf`	Yield Estimation of VLSI Circuits with Downscaled Layouts. DFT Witold A. Pleskacz
1997	A*	`conf`	CAD at the Design-Manufacturing Interface. DAC Hans T. Heineken, Jitendra Khare, Wojciech Maly, Pranab K. Nag, Charles H. Ouyang, Witold A. Pleskacz
1997	—	`conf`	Detection of Yield Trends. DFT Witold A. Pleskacz, Wojciech Maly, Hans T. Heineken
1997	—	`conf`	Improved Yield Model for Submicron Domain. DFT Witold A. Pleskacz, Wojciech Maly
1996	—	`conf`	Extraction of critical areas for opens in large VLSI circuits. DFT Charles H. Ouyang, Witold A. Pleskacz, Wojciech Maly
1995	—	`conf`	SENSAT-a practical tool for estimation of the IC layout sensitivity to spot defects. ED&TC Witold A. Pleskacz, Wieslaw Kuzmicz