Wing-Kai Chow

22 papers A* 3A 3Journal 7Unranked 9
YearRankTypeTitle / Venue / Authors
2022 J jnl
Pin-Accessible Legalization for Mixed-Cell-Height Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Haocheng Li, Wing-Kai Chow, Gengjie Chen, Bei Yu, Evangeline F. Y. Young
2019 — conf
ISPD 2019 Initial Detailed Routing Contest and Benchmark with Advanced Routing Rules.
ISPD
Wen-Hao Liu, Stefanus Mantik, Wing-Kai Chow, Yixiao Ding, Amin Farshidi, Gracieli Posser
2018 — conf
ISPD 2018 Initial Detailed Routing Contest and Benchmarks.
ISPD
Stefanus Mantik, Gracieli Posser, Wing-Kai Chow, Yixiao Ding, Wen-Hao Liu
2018 — conf
Prim-Dijkstra Revisited: Achieving Superior Timing-driven Routing Trees.
ISPD
Charles J. Alpert, Wing-Kai Chow, Kwangsoo Han, Andrew B. Kahng, Zhuo Li, Derong Liu, Sriram Venkatesh
2018 J jnl
RippleFPGA: Routability-Driven Simultaneous Packing and Placement for Modern FPGAs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Gengjie Chen, Chak-Wa Pui, Wing-Kai Chow, Ka-Chun Lam, Jian Kuang, Evangeline F. Y. Young, Bei Yu
2018 A* conf
Routability-driven and fence-aware legalization for mixed-cell-height circuits.
DAC
Haocheng Li, Wing-Kai Chow, Gengjie Chen, Evangeline F. Y. Young, Bei Yu
2017 — conf
Fence-aware detailed-routability driven placement.
SLIP
Wing-Kai Chow, Jian Kuang, Peishan Tu, Evangeline F. Y. Young
2017 — conf
Timing driven routing tree construction.
SLIP
Peishan Tu, Wing-Kai Chow, Evangeline F. Y. Young
2016 A* conf
Legalization algorithm for multiple-row height standard cell design.
DAC
Wing-Kai Chow, Chak-Wa Pui, Evangeline F. Y. Young
2016 J jnl
Placement: From Wirelength to Detailed Routability.
IPSJ Trans. Syst. LSI Des. Methodol.
Wing-Kai Chow, Evangeline F. Y. Young
2016 A conf
RippleFPGA: a routability-driven placement for large-scale heterogeneous FPGAs.
ICCAD
Chak-Wa Pui, Gengjie Chen, Wing-Kai Chow, Ka-Chun Lam, Jian Kuang, Peishan Tu, Hang Zhang, Evangeline F. Y. Young, Bei Yu
2016 J jnl
Triple Patterning Lithography Aware Optimization and Detailed Placement Algorithms for Standard Cell-Based Designs.
IEEE Trans. Very Large Scale Integr. Syst.
Jian Kuang, Wing-Kai Chow, Evangeline F. Y. Young
2015 A conf
A robust approach for process variation aware mask optimization.
DATE
Jian Kuang, Wing-Kai Chow, Evangeline F. Y. Young
2014 — conf
Cell density-driven detailed placement with displacement constraint.
ISPD
Wing-Kai Chow, Jian Kuang, Xu He, Wenzan Cai, Evangeline F. Y. Young
2014 J jnl
Obstacle-avoiding rectilinear Steiner tree construction in sequential and parallel approach.
Integr.
Wing-Kai Chow, Liang Li, Evangeline F. Y. Young, Chiu-Wing Sham
2014 A conf
Triple patterning lithography aware optimization for standard cell based design.
ICCAD
Jian Kuang, Wing-Kai Chow, Evangeline F. Y. Young
2013 A* conf
Ripple 2.0: high quality routability-driven placement via global router integration.
DAC
Xu He, Tao Huang, Wing-Kai Chow, Jian Kuang, Ka-Chun Lam, Wenzan Cai, Evangeline F. Y. Young
2013 — conf
SRP: simultaneous routing and placement for congestion refinement.
ISPD
Xu He, Wing-Kai Chow, Evangeline F. Y. Young
2012 J jnl
A new clock network synthesizer for modern VLSI designs.
Integr.
Jingwei Lu, Wing-Kai Chow, Chiu-Wing Sham
2012 J jnl
Fast Power- and Slew-Aware Gated Clock Tree Synthesis.
IEEE Trans. Very Large Scale Integr. Syst.
Jingwei Lu, Wing-Kai Chow, Chiu-Wing Sham
2010 — conf
A dual-MST approach for clock network synthesis.
ASP-DAC
Jingwei Lu, Wing-Kai Chow, Chiu-Wing Sham, Evangeline F. Y. Young
2010 — conf
Clock Network Synthesis with Concurrent Gate Insertion.
PATMOS
Jingwei Lu, Wing-Kai Chow, Chiu-Wing Sham