Win-San Khwa

57 papers A* 2A 2Journal 23Unranked 30
YearRankTypeTitle / Venue / Authors
2026 — conf
30.5 A 16nm 72kb 120.5TFLOPS/W Versatile-Format Dual-Representation Gain-Cell CIM Macro for General Purpose AI Tasks.
ISSCC
Jen-Chun Tien, Win-San Khwa, Le-Jung Hsieh, Tsung-Han Lou, Jyun-Cheng Bai, Yu-Sheng Kao, Ting-Hao Hsu, Mai Tseng, Hung-Hsi Hsu, Yao-Kai Yeh, De-Qi You, Ashwin Sanjay Lele, Brian Crafton, Bo Zhang, Ping-Sheng Wu, Ya-Tang Yang, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang
2026 — conf
A 22nm 96Mb 50.6-to-90.2TFLOPS/W Non-Linear MLC ReRAM CIM Macro with High-Retention for Mamba/Transformer/CNN.
ISSCC
Hung-Hsi Hsu, Win-San Khwa, Yao-Kai Yeh, Chih-Ling Wu, Chang-Yuan Chen, Yen-Che Huang, Yen-hua Lin, Cheng-Feng Chang, Yen-Tung Shao, Jen-Chun Tien, De-Qi You, Ping-Sheng Wu, Bo Zhang, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang
2026 J jnl
A Microscaling Multi-Mode Gain-Cell Computing-in-Memory Macro for Advanced AI Edge Device.
IEEE J. Solid State Circuits
Jen-Chun Tien, Ping-Chun Wu, Win-San Khwa, Ashwin Sanjay Lele, Jian-Wei Su, Chiao-Yen Cheng, Jun-Ming Hsu, Yu-Chen Chen, Le-Jung Hsieh, Jyun-Cheng Bai, Yu-Sheng Kao, Tsung-Han Lou, Jui-Jen Wu, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang
2026 J jnl
A μ-NMC-Δ-IMC Heterogeneous STT-MRAM Compute-in-Memory Macro Using Δ-Clamping Bit Reduction for Noise-Tolerant Bayesian Neural Networks.
IEEE J. Solid State Circuits
De-Qi You, Win-San Khwa, Bo Zhang, Fang-Yi Chen, Andrew Lee, Yu-Cheng Hung, Yi-Ming Li, Yu-Hui Wang, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang
2026 J jnl
SATA: Sparsity-Aware Scheduling for Selective Token Attention.
CoRR
Zhenkun Fan, Zishen Wan, Che-Kai Liu, Ashwin Sanjay Lele, Win-San Khwa, Bo Zhang, Meng-Fan Chang, Arijit Raychowdhury
2025 — conf
14.1 A 22nm 104.5TOPS/W µ-NMC-Δ-IMC Heterogeneous STT-MRAM CIM Macro for Noise-Tolerant Bayesian Neural Networks.
ISSCC
De-Qi You, Win-San Khwa, Bo Zhang, Fang-Yi Chen, Andrew Lee, Yu-Cheng Hung, Yi-Ming Li, Yu-Hui Wang, Chung-Chuan Lo, Ren-Shuo Liu, Kea-Tiong Tang, Chih-Cheng Hsieh, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang
2025 — conf
14.2 A 16nm 216kb, 188.4TOPS/W and 133.5TFLOPS/W Microscaling Multi-Mode Gain-Cell CIM Macro Edge-AI Devices.
ISSCC
Win-San Khwa, Ping-Chun Wu, Jian-Wei Su, Chiao-Yen Cheng, Jun-Ming Hsu, Yu-Chen Chen, Le-Jung Hsieh, Jyun-Cheng Bai, Yu-Sheng Kao, Tsung-Han Lou, Ashwin Sanjay Lele, Jui-Jen Wu, Jen-Chun Tien, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang
2025 — conf
2.9 STEP: An 8K-60fps Space-Time Resolution-Enhancement Neural-Network Processor for Next-Generation Display and Streaming.
ISSCC
Kai-Ping Lin, Tong Wu, Chang-Pao Lin, Po-Wei Chen, Zhi-Jun Zhang, Win-San Khwa, Meng-Fan Chang, Chao-Tsung Huang
2025 J jnl
A 22 nm Floating-Point ReRAM Compute-in-Memory Macro Using Residue-Shared ADC for AI Edge Device.
IEEE J. Solid State Circuits
Hung-Hsi Hsu, Tai-Hao Wen, Win-San Khwa, Wei-Hsing Huang, Zhao-En Ke, Yu-Hsiang Chin, Hua-Jin Wen, Yu-Chen Chang, Wei-Ting Hsu, Ashwin Sanjay Lele, Bo Zhang, Ping-Sheng Wu, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Shih-Hsih Teng, Chung-Cheng Chou, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang
2025 J jnl
An Edge Accelerator With 5 MB of 0.256-pJ/bit Embedded RRAM and a Localization Solver for Bristle Robot Surveillance.
IEEE J. Solid State Circuits
Samuel D. Spetalnick, Ashwin Sanjay Lele, Brian Crafton, Muya Chang, Sigang Ryu, Jong-Hyeok Yoon, Zhijian Hao, Azadeh Ansari, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury
2025 J jnl
An Integer-Floating-Point Dual-Mode Gain-Cell Computing-in-Memory Macro for Advanced AI Edge Chips.
IEEE J. Solid State Circuits
Ping-Chun Wu, Win-San Khwa, Jui-Jen Wu, Jian-Wei Su, Chuan-Jia Jhang, Ho-Yu Chen, Zhao-En Ke, Ting-Chien Chiu, Jun-Ming Hsu, Chiao-Yen Cheng, Yu-Chen Chen, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang
2025 J jnl
Enhancing DCIM Efficiency with Multi-Storage-Row Architecture for Edge AI Workloads.
IEEE Comput. Archit. Lett.
Xiaoyu Sun, Haruki Mori, Wei-Chang Zhao, Je-Min Hung, Hidehiro Fujiwara, Brian Crafton, Bo Zhang, Win-San Khwa, Yu-Der Chih, Tsung-Yung Jonathan Chang, Kerem Akarvardar
2025 A* conf
Finding the Pareto Frontier of Low-Precision Data Formats and MAC Architecture for LLM Inference.
DAC
Brian Crafton, Xiaochen Peng, Xiaoyu Sun, Ashwin Sanjay Lele, Bo Zhang, Win-San Khwa, Kerem Akarvardar
2025 J jnl
MINOTAUR: A Posit-Based 0.42-0.50-TOPS/W Edge Transformer Inference and Training Accelerator.
IEEE J. Solid State Circuits
Kartik Prabhu, Robert M. Radway, Jeffrey Yu, Kai Bartolone, Massimo Giordano, Fabian Peddinghaus, Yonatan Urman, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Subhasish Mitra, Priyanka Raina
2024 — conf
30.1 A 40nm VLIW Edge Accelerator with 5MB of 0.256pJ/b RRAM and a Localization Solver for Bristle Robot Surveillance.
ISSCC
Samuel D. Spetalnick, Ashwin Sanjay Lele, Brian Crafton, Muya Chang, Sigang Ryu, Jong-Hyeok Yoon, Zhijian Hao, Azadeh Ansari, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury
2024 — conf
34.2 A 16nm 96Kb Integer/Floating-Point Dual-Mode-Gain-Cell-Computing-in-Memory Macro Achieving 73.3-163.3TOPS/W and 33.2-91.2TFLOPS/W for AI-Edge Devices.
ISSCC
Win-San Khwa, Ping-Chun Wu, Jui-Jen Wu, Jian-Wei Su, Ho-Yu Chen, Zhao-En Ke, Ting-Chien Chiu, Jun-Ming Hsu, Chiao-Yen Cheng, Yu-Chen Chen, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang
2024 — conf
34.8 A 22nm 16Mb Floating-Point ReRAM Compute-in-Memory Macro with 31.2TFLOPS/W for AI Edge Devices.
ISSCC
Tai-Hao Wen, Hung-Hsi Hsu, Win-San Khwa, Wei-Hsing Huang, Zhao-En Ke, Yu-Hsiang Chin, Hua-Jin Wen, Yu-Chen Chang, Wei-Ting Hsu, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Shih-Hsih Teng, Chung-Cheng Chou, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang
2024 J jnl
A 22 nm 10.03-237.99 TOPS/W Time-Digital-Hybrid SRAM Compute-in-Memory AI Accelerator for GNN Edge Device Applications.
IEEE Trans. Circuits Syst. Artif. Intell.
Chuan-Jia Jhang, Win-San Khwa, Ping-Chun Wu, Ashwin Sanjay Lele, Ping-Sheng Wu, Chao-En Ke, Ting-Chien Chiu, Yu-Cheng Hung, Wei-Ting Hsu, Jun-Ming Hsu, Chiao-Yen Cheng, Yu-Chen Chen, Jui-Jen Wu, Meng-Fan Chang
2024 — conf
A 22nm Nonvolatile AI-Edge Processor with 21.4TFLOPS/W using 47.25Mb Lossless-Compressed-Computing STT-MRAM Near-Memory-Compute Macro.
VLSI Technology and Circuits
De-Qi You, Win-San Khwa, Jui-Jen Wu, Chuan-Jia Jhang, Guan-Yi Lin, Po-Jung Chen, Ting-Chien Chiu, Fang-Yi Chen, Andrew Lee, Yu-Cheng Hung, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang
2024 J jnl
A Heterogeneous RRAM In-Memory and SRAM Near-Memory SoC for Fused Frame and Event-Based Target Identification and Tracking.
IEEE J. Solid State Circuits
Ashwin Sanjay Lele, Muya Chang, Samuel D. Spetalnick, Brian Crafton, Shota Konno, Zishen Wan, Ashwin Bhat, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury
2024 J jnl
A Nonvolatile AI-Edge Processor With SLC-MLC Hybrid ReRAM Compute-in-Memory Macro Using Current-Voltage-Hybrid Readout Scheme.
IEEE J. Solid State Circuits
Hung-Hsi Hsu, Tai-Hao Wen, Wei-Hsing Huang, Win-San Khwa, Yun-Chen Lo, Chuan-Jia Jhang, Yu-Hsiang Chin, Yu-Chiao Chen, Chung-Chuan Lo, Ren-Shuo Liu, Kea-Tiong Tang, Chih-Cheng Hsieh, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang
2024 J jnl
An 8b-Precision 8-Mb STT-MRAM Near-Memory-Compute Macro Using Weight-Feature and Input-Sparsity Aware Schemes for Energy-Efficient Edge AI Devices.
IEEE J. Solid State Circuits
De-Qi You, Yen-Cheng Chiu, Win-San Khwa, Chung-Yuan Li, Fang-Ling Hsieh, Yu-An Chien, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang
2024 J jnl
EMBER: Efficient Multiple-Bits-Per-Cell Embedded RRAM Macro for High-Density Digital Storage.
IEEE J. Solid State Circuits
Akash Levy, Luke R. Upton, Michael D. Scott, Dennis Rich, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Subhasish Mitra, Boris Murmann, Priyanka Raina
2024 J jnl
Estimating Power, Performance, and Area for On-Sensor Deployment of AR/VR Workloads Using an Analytical Framework.
ACM Trans. Design Autom. Electr. Syst.
Xiaoyu Sun, Xiaochen Peng, Sai Qian Zhang, Jorge Gomez, Win-San Khwa, Syed Shakib Sarwar, Ziyun Li, Weidong Cao, Zhao Wang, Chiao Liu, Meng-Fan Chang, Barbara De Salvo, Kerem Akarvardar, H.-S. Philip Wong
2024 — conf
MINOTAUR: An Edge Transformer Inference and Training Accelerator with 12 MBytes On-Chip Resistive RAM and Fine-Grained Spatiotemporal Power Gating.
VLSI Technology and Circuits
Kartik Prabhu, Robert M. Radway, Y. Jeffrey, Kai Bartolone, Massimo Giordano, Fabian Peddinghaus, Yonatan Urman, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Subhasish Mitra, Priyanka Raina
2024 J jnl
Neural Architecture Search of Hybrid Models for NPU-CIM Heterogeneous AR/VR Devices.
CoRR
Yiwei Zhao, Ziyun Li, Win-San Khwa, Xiaoyu Sun, Sai Qian Zhang, Syed Shakib Sarwar, Kleber Hugo Stangherlin, Yi-Lun Lu, Jorge Tomás Gómez, Jae-sun Seo, Phillip B. Gibbons, Barbara De Salvo, Chiao Liu
2024 A conf
Non-volatile Memory Technologies for Edge AI Applications.
ICCAD
Xiaoyu Sun, Win-San Khwa, Xiaochen Peng, Meng-Fan Chang, Kerem Akarvardar
2023 J jnl
8-b Precision 8-Mb ReRAM Compute-in-Memory Macro Using Direct-Current-Free Time-Domain Readout Scheme for AI Edge Devices.
IEEE J. Solid State Circuits
Je-Min Hung, Tai-Hao Wen, Yen-Hsiang Huang, Sheng-Po Huang, Fu-Chun Chang, Chin-I Su, Win-San Khwa, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang
2023 — conf
A 2.38 MCells/mm
VLSI Technology and Circuits
Samuel D. Spetalnick, Muya Chang, Shota Konno, Brian Crafton, Ashwin Sanjay Lele, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury
2023 — conf
A 22nm 8Mb STT-MRAM Near-Memory-Computing Macro with 8b-Precision and 46.4-160.1TOPS/W for Edge-AI Devices.
ISSCC
Yen-Cheng Chiu, Win-San Khwa, Chung-Yuan Li, Fang-Ling Hsieh, Yu-An Chien, Guan-Yi Lin, Po-Jung Chen, Tsen-Hsiang Pan, De-Qi You, Fang-Yi Chen, Andrew Lee, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang
2023 — conf
A 28nm Nonvolatile AI Edge Processor using 4Mb Analog-Based Near-Memory-Compute ReRAM with 27.2 TOPS/W for Tiny AI Edge Devices.
VLSI Technology and Circuits
Tai-Hao Wen, Je-Min Hung, Hung-Hsi Hsu, Yuan Wu, Fu-Chun Chang, Chung-Yuan Li, Chih-Han Chien, Chin-I Su, Win-San Khwa, Jui-Jen Wu, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Mon-Shu Ho, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang
2023 — conf
A 73.53TOPS/W 14.74TOPS Heterogeneous RRAM In-Memory and SRAM Near-Memory SoC for Hybrid Frame and Event-Based Target Tracking.
ISSCC
Muya Chang, Ashwin Sanjay Lele, Samuel D. Spetalnick, Brian Crafton, Shota Konno, Zishen Wan, Ashwin Bhat, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury
2023 A conf
A Fully-Integrated Energy-Scalable Transformer Accelerator Supporting Adaptive Model Configuration and Word Elimination for Language Understanding on Edge Devices.
ISLPED
Zexi Ji, Hanrui Wang, Miaorong Wang, Win-San Khwa, Meng-Fan Chang, Song Han, Anantha P. Chandrakasan
2023 — conf
A Nonvolatile Al-Edge Processor with 4MB SLC-MLC Hybrid-Mode ReRAM Compute-in-Memory Macro and 51.4-251TOPS/W.
ISSCC
Wei-Hsing Huang, Tai-Hao Wen, Je-Min Hung, Win-San Khwa, Yun-Chen Lo, Chuan-Jia Jhang, Hung-Hsi Hsu, Yu-Hsiang Chin, Yu-Chiao Chen, Chung-Chuan Lo, Ren-Shuo Liu, Kea-Tiong Tang, Chih-Cheng Hsieh, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang
2023 — conf
EMBER: A 100 MHz, 0.86 mm
ESSCIRC
Luke R. Upton, Akash Levy, Michael D. Scott, Dennis Rich, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Subhasish Mitra, Priyanka Raina, Boris Murmann
2022 — conf
A 22nm 4Mb STT-MRAM Data-Encrypted Near-Memory Computation Macro with a 192GB/s Read-and-Decryption Bandwidth and 25.1-55.1TOPS/W 8b MAC for AI Operations.
ISSCC
Yen-Cheng Chiu, Chia-Sheng Yang, Shih-Hsih Teng, Hsiao-Yu Huang, Fu-Chun Chang, Yuan Wu, Yu-An Chien, Fang-Ling Hsieh, Chung-Yuan Li, Guan-Yi Lin, Po-Jung Chen, Tsen-Hsiang Pan, Chung-Chuan Lo, Win-San Khwa, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Chieh-Pu Lo, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang
2022 J jnl
A 40-nm 118.44-TOPS/W Voltage-Sensing Compute-in-Memory RRAM Macro With Write Verification and Multi-Bit Encoding.
IEEE J. Solid State Circuits
Jong-Hyeok Yoon, Muya Chang, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury
2022 — conf
A 40-nm, 2M-Cell, 8b-Precision, Hybrid SLC-MLC PCM Computing-in-Memory Macro with 20.5 - 65.0TOPS/W for Tiny-Al Edge Devices.
ISSCC
Win-San Khwa, Yen-Cheng Chiu, Chuan-Jia Jhang, Sheng-Po Huang, Chun-Ying Lee, Tai-Hao Wen, Fu-Chun Chang, Shao-Ming Yu, Tung-Yin Lee, Meng-Fan Chang
2022 J jnl
A 40-nm, 64-Kb, 56.67 TOPS/W Voltage-Sensing Computing-In-Memory/Digital RRAM Macro Supporting Iterative Write With Verification and Online Read-Disturb Detection.
IEEE J. Solid State Circuits
Jong-Hyeok Yoon, Muya Chang, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury
2022 — conf
A 40nm 60.64TOPS/W ECC-Capable Compute-in-Memory/Digital 2.25MB/768KB RRAM/SRAM System with Embedded Cortex M3 Microprocessor for Edge Recommendation Systems.
ISSCC
Muya Chang, Samuel D. Spetalnick, Brian Crafton, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury
2022 — conf
A 40nm 64kb 26.56TOPS/W 2.37Mb/mm
ISSCC
Samuel D. Spetalnick, Muya Chang, Brian Crafton, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury
2022 — conf
An 8-Mb DC-Current-Free Binary-to-8b Precision ReRAM Nonvolatile Computing-in-Memory Macro using Time-Space-Readout with 1286.4-21.6TOPS/W for Edge-AI Devices.
ISSCC
Je-Min Hung, Yen-Hsiang Huang, Sheng-Po Huang, Fu-Chun Chang, Tai-Hao Wen, Chin-I Su, Win-San Khwa, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang
2022 J jnl
CHIMERA: A 0.92-TOPS, 2.2-TOPS/W Edge AI Accelerator With 2-MByte On-Chip Foundry Resistive RAM for Efficient Training and Inference.
IEEE J. Solid State Circuits
Kartik Prabhu, Albert Gural, Zainab F. Khan, Robert M. Radway, Massimo Giordano, Kalhan Koul, Rohan Doshi, John W. Kustin, Timothy Liu, Gregorio B. Lopes, Victor Turbiner, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Guénolé Lallement, Boris Murmann, Subhasish Mitra, Priyanka Raina
2022 J jnl
High-density analog image storage in an analog-valued non-volatile memory array.
Neuromorph. Comput. Eng.
Xin Zheng, Ryan Zarcone, Akash Levy, Win-San Khwa, Priyanka Raina, Bruno A. Olshausen, H.-S. Philip Wong
2021 — conf
29.1 A 40nm 64Kb 56.67TOPS/W Read-Disturb-Tolerant Compute-in-Memory/Digital RRAM Macro with Active-Feedback-Based Read and In-Situ Write Verification.
ISSCC
Jong-Hyeok Yoon, Muya Chang, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury
2021 — conf
A 22nm 4Mb 8b-Precision ReRAM Computing-in-Memory Macro with 11.91 to 195.7TOPS/W for Tiny AI Edge Devices.
ISSCC
Cheng-Xin Xue, Je-Min Hung, Hui-Yao Kao, Yen-Hsiang Huang, Sheng-Po Huang, Fu-Chun Chang, Peng Chen, Ta-Wei Liu, Chuan-Jia Jhang, Chin-I Su, Win-San Khwa, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang
2021 — conf
A 40nm 100Kb 118.44TOPS/W Ternary-weight Computein-Memory RRAM Macro with Voltage-sensing Read and Write Verification for reliable multi-bit RRAM operation.
CICC
Jong-Hyeok Yoon, Muya Chang, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury
2021 J jnl
A 7-nm Compute-in-Memory SRAM Macro Supporting Multi-Bit Input, Weight and Output and Achieving 351 TOPS/W and 372.4 GOPS.
IEEE J. Solid State Circuits
Mahmut E. Sinangil, Burak Erbagci, Rawan Naous, Kerem Akarvardar, Dar Sun, Win-San Khwa, Hung-Jen Liao, Yih Wang, Jonathan Chang
2021 — conf
CHIMERA: A 0.92 TOPS, 2.2 TOPS/W Edge AI Accelerator with 2 MByte On-Chip Foundry Resistive RAM for Efficient Training and Inference.
VLSI Circuits
Massimo Giordano, Kartik Prabhu, Kalhan Koul, Robert M. Radway, Albert Gural, Rohan Doshi, Zainab F. Khan, John W. Kustin, Timothy Liu, Gregorio B. Lopes, Victor Turbiner, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Guénolé Lallement, Boris Murmann, Subhasish Mitra, Priyanka Raina
2020 — conf
15.3 A 351TOPS/W and 372.4GOPS Compute-in-Memory SRAM Macro in 7nm FinFET CMOS for Machine-Learning Applications.
ISSCC
Qing Dong, Mahmut E. Sinangil, Burak Erbagci, Dar Sun, Win-San Khwa, Hung-Jen Liao, Yih Wang, Jonathan Chang
2019 — conf
A 5.1pJ/Neuron 127.3us/Inference RNN-based Speech Recognition Processor using 16 Computing-in-Memory SRAM Macros in 65nm CMOS.
VLSI Circuits
Ruiqi Guo, Yonggang Liu, Shixuan Zheng, Ssu-Yen Wu, Peng Ouyang, Win-San Khwa, Xi Chen, Jia-Jing Chen, Xiudong Li, Leibo Liu, Meng-Fan Chang, Shaojun Wei, Shouyi Yin
2019 J jnl
A Dual-Split 6T SRAM-Based Computing-in-Memory Unit-Macro With Fully Parallel Product-Sum Operation for Binarized DNN Edge Processors.
IEEE Trans. Circuits Syst. I Regul. Pap.
Xin Si, Win-San Khwa, Jia-Jing Chen, Jia-Fang Li, Xiaoyu Sun, Rui Liu, Shimeng Yu, Hiroyuki Yamauchi, Qiang Li, Meng-Fan Chang
2018 — conf
A 65nm 4Kb algorithm-dependent computing-in-memory SRAM unit-macro with 2.3ns and 55.8TOPS/W fully parallel product-sum operation for binary DNN edge processors.
ISSCC
Win-San Khwa, Jia-Jing Chen, Jia-Fang Li, Xin Si, En-Yu Yang, Xiaoyu Sun, Rui Liu, Pai-Yu Chen, Qiang Li, Shimeng Yu, Meng-Fan Chang
2018 A* conf
Parallelizing SRAM arrays with customized bit-cell for binary neural networks.
DAC
Rui Liu, Xiaochen Peng, Xiaoyu Sun, Win-San Khwa, Xin Si, Jia-Jing Chen, Jia-Fang Li, Meng-Fan Chang, Shimeng Yu
2017 J jnl
A Resistance Drift Compensation Scheme to Reduce MLC PCM Raw BER by Over 100× for Storage Class Memory Applications.
IEEE J. Solid State Circuits
Win-San Khwa, Meng-Fan Chang, Jau-Yi Wu, Ming-Hsiu Lee, Tzu-Hsiang Su, Keng-Hao Yang, Tien-Fu Chen, Tien-Yen Wang, Hsiang-Pang Li, Matthew J. BrightSky, Sangbum Kim, Hsiang-Lam Lung, Chung Lam
2017 — conf
Circuit design for beyond von Neumann applications using emerging memory: From nonvolatile logics to neuromorphic computing.
ISQED
Wei-Hao Chen, Win-San Khwa, Jun-Yi Li, Wei-Yu Lin, Huan-Ting Lin, Yongpan Liu, Yu Wang, Huaqiang Wu, Huazhong Yang, Meng-Fan Chang
2016 — conf
7.3 A resistance-drift compensation scheme to reduce MLC PCM raw BER by over 100× for storage-class memory applications.
ISSCC
Win-San Khwa, Meng-Fan Chang, Jau-Yi Wu, Ming-Hsiu Lee, Tzu-Hsiang Su, Keng-Hao Yang, Tien-Fu Chen, Tien-Yen Wang, Hsiang-Pang Li, Matthew BrightSky, Sangbum Kim, Hsiang-Lam Lung, Chung Lam