William W. Walker

26 papers A 1C 1Misc 1Journal 12Unranked 11
YearRankTypeTitle / Venue / Authors
2013 — conf
A 32Gb/s wireline receiver with a low-frequency equalizer, CTLE and 2-tap DFE in 28nm CMOS.
ISSCC
Samir Parikh, Tony Kao, Yasuo Hidaka, Jian Jiang, Asako Toda, Scott McLeod, William W. Walker, Yoichi Koyanagi, Toshiyuki Shibuya, Jun Yamada
2011 — conf
A 4-channel 10.3Gb/s transceiver with adaptive phase equalizer for 4-to-41dB loss PCB channel.
ISSCC
Yasuo Hidaka, Takeshi Horie, Yoichi Koyanagi, Takashi Miyoshi, Hideki Osone, Samir Parikh, Subodh M. Reddy, Toshiyuki Shibuya, Yasushi Umezawa, William W. Walker
2010 J jnl
A 3 Watt 39.8-44.6 Gb/s Dual-Mode SFI5.2 SerDes Chip Set in 65 nm CMOS.
IEEE J. Solid State Circuits
Nikola Nedovic, Anders Kristensson, Samir Parikh, Subodh M. Reddy, Scott McLeod, Nestoras Tzartzanis, Kouichi Kanda, Takuji Yamamoto, Satoshi Matsubara, Masaya Kibune, Yoshiyasu Doi, Satoshi Ide, Yukito Tsunoda, Tetsuji Yamabana, Takayuki Shibasaki, Yasumoto Tomita, Takayuki Hamada, Mariko Sugawara, Tadashi Ikeuchi, Naoki Kuwata, Hirotaka Tamura, Junji Ogawa, William W. Walker
2009 J jnl
A Single-40 Gb/s Dual-20 Gb/s Serializer IC With SFI-5.2 Interface in 65 nm CMOS.
IEEE J. Solid State Circuits
Kouichi Kanda, Hirotaka Tamura, Takuji Yamamoto, Satoshi Matsubara, Masaya Kibune, Yoshiyasu Doi, Takayuki Shibasaki, Nestoras Tzartzanis, Anders Kristensson, Samir Parikh, Satoshi Ide, Yukito Tsunoda, Tetsuji Yamabana, Mariko Sugawara, Naoki Kuwata, Tadashi Ikeuchi, Junji Ogawa, William W. Walker
2009 — conf
A single-40Gb/s dual-20Gb/s serializer IC with SFI-5.2 interface in 65nm CMOS.
ISSCC
Kouichi Kanda, Hirotaka Tamura, Takuji Yamamoto, Satoshi Matsubara, Masaya Kibune, Yoshiyasu Doi, Takayuki Shibasaki, Nestoras Tzartzanis, Anders Kristensson, Samir Parikh, Satoshi Ide, Yukito Tsunoda, Tetsuji Yamabana, Mariko Sugawara, Naoki Kuwata, Tadashi Ikeuchi, Junji Ogawa, William W. Walker
2008 J jnl
Event-Driven Modeling of CDR Jitter Induced by Power-Supply Noise, Finite Decision-Circuit Bandwidth, and Channel ISI.
IEEE Trans. Circuits Syst. I Regul. Pap.
Marcus van Ierssel, Hisakatsu Yamaguchi, Ali Sheikholeslami, Hirotaka Tamura, William W. Walker
2007 J jnl
A 3.2 Gb/s CDR Using Semi-Blind Oversampling to Achieve High Jitter Tolerance.
IEEE J. Solid State Circuits
Marcus van Ierssel, Ali Sheikholeslami, Hirotaka Tamura, William W. Walker
2007 J jnl
A 40-44 Gb/s 3 × Oversampling CMOS CDR/1: 16 DEMUX.
IEEE J. Solid State Circuits
Nikola Nedovic, Nestoras Tzartzanis, Hirotaka Tamura, Francis M. Rotella, Magnus Wiklund, Yuma Mizutani, Yusuke Okaniwa, Tadahiro Kuroda, Junji Ogawa, William W. Walker
2007 — conf
A 40-to-44Gb/s 3�? Oversampling CMOS CDR/1: 16 DEMUX.
ISSCC
Nikola Nedovic, Nestoras Tzartzanis, Hirotaka Tamura, Francis M. Rotella, Magnus Wiklund, Yuma Mizutani, Yusuke Okaniwa, Tadahiro Kuroda, Junji Ogawa, William W. Walker
2007 J jnl
A Leakage Current Replica Keeper for Dynamic Circuits.
IEEE J. Solid State Circuits
Yolin Lih, Nestoras Tzartzanis, William W. Walker
2007 Misc conf
An Efficient Uncertainty- and Skew-aware Methodology for Clock Tree Synthesis and Analysis.
VLSI Design
Vineet Wason, Rajeev Murgai, William W. Walker
2006 — conf
A 3.2Gb/s Semi-Blind-Oversampling CDR.
ISSCC
Marcus van Ierssel, Ali Sheikholeslami, Hirotaka Tamura, William W. Walker
2006 — conf
A 5Gb/s Transmitter with Reflection Cancellation for Backplane Transceivers.
CICC
Ricky Yuen, Marcus van Ierssel, Ali Sheikholeslami, William W. Walker, Hirotaka Tamura
2006 J jnl
A Case Study: Energy Efficient High Throughput Chip Multi-Processor Using Reduced-complexity Cores for Transaction Processing Workload.
Inf. Media Technol.
Hisashige Ando, Akira Asato, Motoyuki Kawaba, Hideki Okawara, William W. Walker
2006 — conf
A Reversible Poly-Phase Distributed VCO.
ISSCC
Nestoras Tzartzanis, William W. Walker
2006 — conf
A leakage current replica keeper for dynamic circuits.
ISSCC
Yolin Lih, Nestoras Tzartzanis, William W. Walker
2006 — conf
Clock Distribution Architectures: A Comparative Study.
ISQED
Chao-Yang Yeh, Gustavo R. Wilke, Hongyu Chen, Subodh M. Reddy, Hoa-van Nguyen, Takashi Miyoshi, William W. Walker, Rajeev Murgai
2005 J jnl
A 10-Gb/s receiver with series equalizer and on-chip ISI monitor in 0.11-μm CMOS.
IEEE J. Solid State Circuits
Yasumoto Tomita, Masaya Kibune, Junji Ogawa, William W. Walker, Hirotaka Tamura, Tadahiro Kuroda
2005 J jnl
A 40-Gb/s CMOS clocked comparator with bandwidth modulation technique.
IEEE J. Solid State Circuits
Yusuke Okaniwa, Hirotaka Tamura, Masaya Kibune, Daisuke Yamazaki, Tsz-Shing Cheung, Junji Ogawa, Nestoras Tzartzanis, William W. Walker, Tadahiro Kuroda
2005 J jnl
A Case Study: Power and Performance Improvement of a Chip Multiprocessor for Transaction Processing.
IEEE Trans. Very Large Scale Integr. Syst.
Hisashige Ando, Nestoras Tzartzanis, William W. Walker
2005 A conf
A sliding window scheme for accurate clock mesh analysis.
ICCAD
Hongyu Chen, Chao-Yang Yeh, Gustavo R. Wilke, Subodh M. Reddy, Hoa-van Nguyen, William W. Walker, Rajeev Murgai
2005 J jnl
Differential current-mode sensing for efficient on-chip global signaling.
IEEE J. Solid State Circuits
Nestoras Tzartzanis, William W. Walker
2004 J jnl
A test circuit for measurement of clocked storage element characteristics.
IEEE J. Solid State Circuits
Nikola Nedovic, William W. Walker, Vojin G. Oklobdzija
2004 — conf
Analysis techniques for obtaining the steady-state solution of MOS LC oscillators.
ISCAS (5)
Makram M. Mansour, Amit Mehrotra, William W. Walker, Amit Narayan
2003 C conf
A Transparent Voltage Conversion Method and Its Application to a Dual-Supply-Voltage Register File.
ICCD
Nestoras Tzartzanis, William W. Walker
2003 — conf
An efficient transistor optimizer for custom circuits.
ISCAS (5)
Xiao Yan Yu, Vojin G. Oklobdzija, William W. Walker