William R. Reohr

11 papers Misc 1Journal 5Unranked 5
YearRankTypeTitle / Venue / Authors
2011 J jnl
A 45 nm SOI Embedded DRAM Macro for the POWER™ Processor 32 MByte On-Chip L3 Cache.
IEEE J. Solid State Circuits
John Barth, Don Plass, Erik Nelson, Charlie Hwang, Gregory Fredeman, Michael A. Sperling, Abraham Mathews, Toshiaki Kirihata, William R. Reohr, Kavita Nair, Nianzheng Cao
2010 — conf
A 45nm SOI embedded DRAM macro for POWER7TM 32MB on-chip L3 cache.
ISSCC
John Barth, Don Plass, Erik Nelson, Charlie Hwang, Gregory Fredeman, Michael A. Sperling, Abraham Mathews, William R. Reohr, Kavita Nair, Nianzheng Cao
2009 J jnl
A 1 MB Cache Subsystem Prototype With 1.8 ns Embedded DRAMs in 45 nm SOI CMOS.
IEEE J. Solid State Circuits
Peter J. Klim, John Barth, William R. Reohr, David Dick, Gregory Fredeman, Gary Koch, Hien M. Le, Aditya Khargonekar, Pamela Wilcox, John Golz, Jente B. Kuang, Abraham Mathews, Jethro C. Law, Trong Luong, Hung C. Ngo, Ryan Freese, Hillery C. Hunter, Erik Nelson, Paul C. Parries, Toshiaki Kirihata, Subramanian S. Iyer
2009 — conf
Statistical yield analysis of silicon-on-insulator embedded DRAM.
ISQED
Rouwaida Kanj, Rajiv V. Joshi, Jente B. Kuang, J. Kim, Mesut Meterelliyoz, William R. Reohr, Sani R. Nassif, Kevin J. Nowka
2008 J jnl
A 500 MHz Random Cycle, 1.5 ns Latency, SOI Embedded DRAM Macro Featuring a Three-Transistor Micro Sense Amplifier.
IEEE J. Solid State Circuits
John Barth, William R. Reohr, Paul C. Parries, Gregory Fredeman, John Golz, Stanley Schuster, Richard E. Matick, Hillery C. Hunter, Charles Tanner, Joseph Harig, Hoki Kim, Babar A. Khan, John Griesemer, Robert Havreluk, Kenji Yanagisawa, Toshiaki Kirihata, Subramanian S. Iyer
2008 — conf
An on-chip dual supply charge pump system for 45nm PD SOI eDRAM.
ESSCIRC
Jente B. Kuang, Abraham Mathews, John Barth, Fadi H. Gebara, Tuyet Nguyen, Jeremy D. Schaub, Kevin J. Nowka, Gary D. Carpenter, Don Plass, Erik Nelson, Ivan Vo, William R. Reohr, Toshiaki Kirihata
2008 J jnl
Rethinking Refresh: Increasing Availability and Reducing Power in DRAM for Cache Applications.
IEEE Micro
Philip G. Emma, William R. Reohr, Mesut Meterelliyoz
2007 — conf
A 500MHz Random Cycle 1.5ns-Latency, SOI Embedded DRAM Macro Featuring a 3T Micro Sense Amplifier.
ISSCC
John Barth, William R. Reohr, Paul C. Parries, Gregory Fredeman, John Golz, Stanley Schuster, Richard E. Matick, Hillery C. Hunter, Charles Tanner, Joseph Harig, Hoki Kim, Babar A. Khan, John Griesemer, Robert Havreluk, Kenji Yanagisawa, Toshiaki Kirihata, Subramanian S. Iyer
2006 — conf
Memories: Exploiting Them and Developing Them.
SoCC
William R. Reohr
2004 J jnl
A high-speed 128-kb MRAM core for future universal memory applications.
IEEE J. Solid State Circuits
John K. DeBrosse, Dietmar Gogl, Alexander Bette, Heinz Hoenigschmid, Raphael Robertazzi, Christian Arndt, Daniel Braun, D. Casarotto, Robert Havreluk, Stefan Lammers, Werner Obermaier, William R. Reohr, Hans Viehmann, William J. Gallagher, Gerhard Müller
1993 Misc conf
Design SRAMs for burn-in.
VTS
William R. Reohr, Yuen H. Chan, Donald W. Plass, Antonio Pelella, Philip T. Wu